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x86: Convert to use driver model timer

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Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
master
Bin Meng 9 years ago committed by Simon Glass
parent 881c124ab8
commit 80af39842e
27 changed files with 42 additions and 39 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 3
      arch/x86/cpu/baytrail/valleyview.c
  2. 22
      arch/x86/cpu/coreboot/timestamp.c
  3. 4
      arch/x86/cpu/efi/efi.c
  4. 1
      arch/x86/cpu/ivybridge/cpu.c
  5. 3
      arch/x86/cpu/qemu/qemu.c
  6. 3
      arch/x86/cpu/quark/quark.c
  7. 3
      arch/x86/cpu/queensbay/tnc.c
  8. 1
      arch/x86/dts/bayleybay.dts
  9. 1
      arch/x86/dts/broadwell_som-6896.dts
  10. 1
      arch/x86/dts/chromebook_link.dts
  11. 1
      arch/x86/dts/chromebox_panther.dts
  12. 1
      arch/x86/dts/crownbay.dts
  13. 5
      arch/x86/dts/efi.dts
  14. 5
      arch/x86/dts/galileo.dts
  15. 1
      arch/x86/dts/minnowmax.dts
  16. 5
      arch/x86/dts/qemu-x86_i440fx.dts
  17. 5
      arch/x86/dts/qemu-x86_q35.dts
  18. 6
      arch/x86/dts/tsc_timer.dtsi
  19. 1
      configs/bayleybay_defconfig
  20. 1
      configs/chromebook_link_defconfig
  21. 1
      configs/chromebox_panther_defconfig
  22. 1
      configs/coreboot-x86_defconfig
  23. 1
      configs/crownbay_defconfig
  24. 2
      configs/efi-x86_defconfig
  25. 1
      configs/galileo_defconfig
  26. 1
      configs/minnowmax_defconfig
  27. 1
      configs/qemu-x86_defconfig

3
arch/x86/cpu/baytrail/valleyview.c
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@ -28,9 +28,6 @@ int arch_cpu_init(void)
int ret;
post_code(POST_CPU_INIT);
#ifdef CONFIG_SYS_X86_TSC_TIMER
timer_set_base(rdtsc());
#endif
ret = x86_cpu_init_f();
if (ret)

22
arch/x86/cpu/coreboot/timestamp.c
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@ -27,28 +27,6 @@ static struct timestamp_table *ts_table __attribute__((section(".data")));
void timestamp_init(void)
{
#ifdef CONFIG_SYS_X86_TSC_TIMER
uint64_t base_time;
#endif
ts_table = lib_sysinfo.tstamp_table;
#ifdef CONFIG_SYS_X86_TSC_TIMER
/*
* If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
* of base_time in coreboot's timestamp table as our timer base,
* otherwise TSC counter value will be used.
*
* Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
* the value of base_time in the timestamp table is still zero, so
* we must exclude this case too (this is currently seen on booting
* coreboot in qemu)
*/
if (ts_table && ts_table->base_time)
base_time = ts_table->base_time;
else
base_time = rdtsc();
timer_set_base(base_time);
#endif
timestamp_add_now(TS_U_BOOT_INITTED);
}

4
arch/x86/cpu/efi/efi.c
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@ -10,10 +10,6 @@
int arch_cpu_init(void)
{
#ifdef CONFIG_SYS_X86_TSC_TIMER
timer_set_base(rdtsc());
#endif
return 0;
}

1
arch/x86/cpu/ivybridge/cpu.c
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@ -118,7 +118,6 @@ static void set_spi_speed(void)
int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
timer_set_base(rdtsc());
return x86_cpu_init_f();
}

3
arch/x86/cpu/qemu/qemu.c
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@ -64,9 +64,6 @@ int arch_cpu_init(void)
int ret;
post_code(POST_CPU_INIT);
#ifdef CONFIG_SYS_X86_TSC_TIMER
timer_set_base(rdtsc());
#endif
ret = x86_cpu_init_f();
if (ret)

3
arch/x86/cpu/quark/quark.c
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@ -233,9 +233,6 @@ int arch_cpu_init(void)
int ret;
post_code(POST_CPU_INIT);
#ifdef CONFIG_SYS_X86_TSC_TIMER
timer_set_base(rdtsc());
#endif
ret = x86_cpu_init_f();
if (ret)

3
arch/x86/cpu/queensbay/tnc.c
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@ -52,9 +52,6 @@ int arch_cpu_init(void)
int ret;
post_code(POST_CPU_INIT);
#ifdef CONFIG_SYS_X86_TSC_TIMER
timer_set_base(rdtsc());
#endif
ret = x86_cpu_init_f();
if (ret)

1
arch/x86/dts/bayleybay.dts
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@ -13,6 +13,7 @@
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Intel Bayley Bay";

1
arch/x86/dts/broadwell_som-6896.dts
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@ -3,6 +3,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Advantech SOM-6896";

1
arch/x86/dts/chromebook_link.dts
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@ -4,6 +4,7 @@
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Google Link";

1
arch/x86/dts/chromebox_panther.dts
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@ -3,6 +3,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Google Panther";

1
arch/x86/dts/crownbay.dts
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@ -12,6 +12,7 @@
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Intel Crown Bay";

5
arch/x86/dts/efi.dts
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@ -7,6 +7,7 @@
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "EFI";
@ -16,6 +17,10 @@
stdout-path = &serial;
};
tsc-timer {
clock-frequency = <1000000000>;
};
serial: serial {
compatible = "efi,uart";
};

5
arch/x86/dts/galileo.dts
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@ -11,6 +11,7 @@
/include/ "skeleton.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Intel Galileo";
@ -28,6 +29,10 @@
stdout-path = &pciuart0;
};
tsc-timer {
clock-frequency = <400000000>;
};
mrc {
compatible = "intel,quark-mrc";
flags = <MRC_FLAG_SCRAMBLE_EN>;

1
arch/x86/dts/minnowmax.dts
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@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Intel Minnowboard Max";

5
arch/x86/dts/qemu-x86_i440fx.dts
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@ -12,6 +12,7 @@
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "QEMU x86 (I440FX)";
@ -44,6 +45,10 @@
};
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
#address-cells = <3>;

5
arch/x86/dts/qemu-x86_q35.dts
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@ -22,6 +22,7 @@
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "QEMU x86 (Q35)";
@ -55,6 +56,10 @@
};
};
tsc-timer {
clock-frequency = <1000000000>;
};
pci {
compatible = "pci-x86";
#address-cells = <3>;

6
arch/x86/dts/tsc_timer.dtsi
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@ -0,0 +1,6 @@
/ {
tsc-timer {
compatible = "x86,tsc-timer";
u-boot,dm-pre-reloc;
};
};

1
configs/bayleybay_defconfig
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@ -30,6 +30,7 @@ CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y

1
configs/chromebook_link_defconfig
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@ -32,6 +32,7 @@ CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y

1
configs/chromebox_panther_defconfig
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@ -27,6 +27,7 @@ CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y

1
configs/coreboot-x86_defconfig
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@ -21,6 +21,7 @@ CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y

1
configs/crownbay_defconfig
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@ -30,6 +30,7 @@ CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y

2
configs/efi-x86_defconfig
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@ -14,4 +14,6 @@ CONFIG_DEBUG_EFI_CONSOLE=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_ICH_SPI=y
# CONFIG_X86_SERIAL is not set
CONFIG_TIMER=y
CONFIG_EFI=y

1
configs/galileo_defconfig
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@ -24,6 +24,7 @@ CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y

1
configs/minnowmax_defconfig
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@ -32,6 +32,7 @@ CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y

1
configs/qemu-x86_defconfig
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@ -23,6 +23,7 @@ CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y

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