Merge branch 'master' of http://git.denx.de/u-boot-sunxi
commit
80d307d115
@ -0,0 +1,469 @@ |
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/*
|
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* sun8i H3 platform dram controller init |
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* |
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* (C) Copyright 2007-2015 Allwinner Technology Co. |
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* Jerry Wang <wangflord@allwinnertech.com> |
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* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> |
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> |
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* (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/dram.h> |
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#include <linux/kconfig.h> |
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struct dram_para { |
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u32 read_delays; |
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u32 write_delays; |
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u16 page_size; |
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u8 bus_width; |
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u8 dual_rank; |
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u8 row_bits; |
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}; |
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static inline int ns_to_t(int nanoseconds) |
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{ |
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const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; |
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return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); |
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} |
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static u32 bin_to_mgray(int val) |
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{ |
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static const u8 lookup_table[32] = { |
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0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, |
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0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, |
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0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d, |
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0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11, |
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}; |
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return lookup_table[clamp(val, 0, 31)]; |
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} |
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static int mgray_to_bin(u32 val) |
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{ |
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static const u8 lookup_table[32] = { |
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0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, |
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0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b, |
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0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b, |
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0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15, |
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}; |
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return lookup_table[val & 0x1f]; |
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} |
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static void mctl_phy_init(u32 val) |
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{ |
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struct sunxi_mctl_ctl_reg * const mctl_ctl = |
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
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writel(val | PIR_INIT, &mctl_ctl->pir); |
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mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); |
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} |
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static void mctl_dq_delay(u32 read, u32 write) |
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{ |
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struct sunxi_mctl_ctl_reg * const mctl_ctl = |
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
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int i, j; |
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u32 val; |
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for (i = 0; i < 4; i++) { |
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val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) | |
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DATX_IOCR_READ_DELAY((read >> (i * 4)) & 0xf); |
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for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++) |
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setbits_le32(&mctl_ctl->datx[i].iocr[j], val); |
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} |
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clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); |
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for (i = 0; i < 4; i++) { |
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val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) | |
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DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf); |
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setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQS], val); |
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setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN], val); |
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} |
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setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); |
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udelay(1); |
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} |
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static void mctl_set_master_priority(void) |
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{ |
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struct sunxi_mctl_com_reg * const mctl_com = |
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
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/* enable bandwidth limit windows and set windows size 1us */ |
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writel(0x00010190, &mctl_com->bwcr); |
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/* set cpu high priority */ |
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writel(0x00000001, &mctl_com->mapr); |
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writel(0x0200000d, &mctl_com->mcr[0][0]); |
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writel(0x00800100, &mctl_com->mcr[0][1]); |
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writel(0x06000009, &mctl_com->mcr[1][0]); |
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writel(0x01000400, &mctl_com->mcr[1][1]); |
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writel(0x0200000d, &mctl_com->mcr[2][0]); |
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writel(0x00600100, &mctl_com->mcr[2][1]); |
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writel(0x0100000d, &mctl_com->mcr[3][0]); |
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writel(0x00200080, &mctl_com->mcr[3][1]); |
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writel(0x07000009, &mctl_com->mcr[4][0]); |
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writel(0x01000640, &mctl_com->mcr[4][1]); |
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writel(0x0100000d, &mctl_com->mcr[5][0]); |
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writel(0x00200080, &mctl_com->mcr[5][1]); |
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writel(0x01000009, &mctl_com->mcr[6][0]); |
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writel(0x00400080, &mctl_com->mcr[6][1]); |
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writel(0x0100000d, &mctl_com->mcr[7][0]); |
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writel(0x00400080, &mctl_com->mcr[7][1]); |
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writel(0x0100000d, &mctl_com->mcr[8][0]); |
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writel(0x00400080, &mctl_com->mcr[8][1]); |
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writel(0x04000009, &mctl_com->mcr[9][0]); |
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writel(0x00400100, &mctl_com->mcr[9][1]); |
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writel(0x2000030d, &mctl_com->mcr[10][0]); |
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writel(0x04001800, &mctl_com->mcr[10][1]); |
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writel(0x04000009, &mctl_com->mcr[11][0]); |
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writel(0x00400120, &mctl_com->mcr[11][1]); |
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} |
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static void mctl_set_timing_params(struct dram_para *para) |
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{ |
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struct sunxi_mctl_ctl_reg * const mctl_ctl = |
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
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u8 tccd = 2; |
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u8 tfaw = ns_to_t(50); |
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u8 trrd = max(ns_to_t(10), 4); |
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u8 trcd = ns_to_t(15); |
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u8 trc = ns_to_t(53); |
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u8 txp = max(ns_to_t(8), 3); |
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u8 twtr = max(ns_to_t(8), 4); |
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u8 trtp = max(ns_to_t(8), 4); |
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u8 twr = max(ns_to_t(15), 3); |
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u8 trp = ns_to_t(15); |
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u8 tras = ns_to_t(38); |
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u16 trefi = ns_to_t(7800) / 32; |
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u16 trfc = ns_to_t(350); |
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u8 tmrw = 0; |
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u8 tmrd = 4; |
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u8 tmod = 12; |
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u8 tcke = 3; |
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u8 tcksrx = 5; |
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u8 tcksre = 5; |
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u8 tckesr = 4; |
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u8 trasmax = 24; |
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u8 tcl = 6; /* CL 12 */ |
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u8 tcwl = 4; /* CWL 8 */ |
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u8 t_rdata_en = 4; |
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u8 wr_latency = 2; |
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u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ |
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u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ |
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u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ |
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u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ |
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u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ |
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u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ |
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u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ |
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/* set mode register */ |
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writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ |
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writel(0x40, &mctl_ctl->mr[1]); |
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writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ |
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writel(0x0, &mctl_ctl->mr[3]); |
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/* set DRAM timing */ |
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writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | |
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DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), |
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&mctl_ctl->dramtmg[0]); |
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writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), |
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&mctl_ctl->dramtmg[1]); |
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writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | |
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DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), |
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&mctl_ctl->dramtmg[2]); |
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writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), |
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&mctl_ctl->dramtmg[3]); |
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writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | |
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DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); |
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writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | |
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DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), |
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&mctl_ctl->dramtmg[5]); |
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/* set two rank timing */ |
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clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), |
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(0x66 << 8) | (0x10 << 0)); |
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/* set PHY interface timing, write latency and read latency configure */ |
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writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | |
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(wr_latency << 0), &mctl_ctl->pitmg[0]); |
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/* set PHY timing, PTR0-2 use default */ |
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writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); |
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writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); |
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/* set refresh timing */ |
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writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); |
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} |
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static void mctl_zq_calibration(struct dram_para *para) |
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{ |
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struct sunxi_mctl_ctl_reg * const mctl_ctl = |
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
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int i; |
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u16 zq_val[6]; |
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u8 val; |
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writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); |
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for (i = 0; i < 6; i++) { |
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u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; |
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writel((zq << 20) | (zq << 16) | (zq << 12) | |
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(zq << 8) | (zq << 4) | (zq << 0), |
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&mctl_ctl->zqcr); |
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writel(PIR_CLRSR, &mctl_ctl->pir); |
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mctl_phy_init(PIR_ZCAL); |
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zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; |
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writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); |
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writel(PIR_CLRSR, &mctl_ctl->pir); |
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mctl_phy_init(PIR_ZCAL); |
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val = readl(&mctl_ctl->zqdr[0]) >> 24; |
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zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; |
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} |
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writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); |
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writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); |
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writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); |
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} |
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static void mctl_set_cr(struct dram_para *para) |
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{ |
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struct sunxi_mctl_com_reg * const mctl_com = |
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
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writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | |
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MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) | |
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(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | |
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MCTL_CR_PAGE_SIZE(para->page_size) | |
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MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); |
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} |
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static void mctl_sys_init(struct dram_para *para) |
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{ |
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struct sunxi_ccm_reg * const ccm = |
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
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struct sunxi_mctl_ctl_reg * const mctl_ctl = |
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
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clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); |
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clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); |
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clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); |
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clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); |
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clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); |
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udelay(10); |
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clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); |
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udelay(1000); |
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clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false); |
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clrsetbits_le32(&ccm->dram_clk_cfg, |
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CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK, |
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CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 | |
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CCM_DRAMCLK_CFG_UPD); |
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mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); |
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); |
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); |
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setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); |
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setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); |
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setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); |
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udelay(10); |
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writel(0xc00e, &mctl_ctl->clken); |
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udelay(500); |
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} |
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static int mctl_channel_init(struct dram_para *para) |
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{ |
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struct sunxi_mctl_com_reg * const mctl_com = |
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
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struct sunxi_mctl_ctl_reg * const mctl_ctl = |
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
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|
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unsigned int i; |
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mctl_set_cr(para); |
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mctl_set_timing_params(para); |
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mctl_set_master_priority(); |
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/* setting VTC, default disable all VT */ |
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clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); |
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clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); |
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|
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/* increase DFI_PHY_UPD clock */ |
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writel(PROTECT_MAGIC, &mctl_com->protect); |
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udelay(100); |
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clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16); |
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writel(0x0, &mctl_com->protect); |
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udelay(100); |
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|
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/* set dramc odt */ |
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for (i = 0; i < 4; i++) |
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clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) | |
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(0x1 << 1) | (0x3 << 2) | (0x3 << 12) | |
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(0x3 << 14), |
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IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2); |
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|
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/* AC PDR should always ON */ |
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setbits_le32(&mctl_ctl->aciocr, 0x1 << 1); |
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|
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/* set DQS auto gating PD mode */ |
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setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); |
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|
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/* dx ddr_clk & hdr_clk dynamic mode */ |
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clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); |
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|
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/* dphy & aphy phase select 270 degree */ |
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clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), |
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(0x1 << 10) | (0x2 << 8)); |
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|
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/* set half DQ */ |
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if (para->bus_width != 32) { |
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writel(0x0, &mctl_ctl->datx[2].gcr); |
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writel(0x0, &mctl_ctl->datx[3].gcr); |
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} |
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|
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/* data training configuration */ |
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clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, |
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(para->dual_rank ? 0x3 : 0x1) << 24); |
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|
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|
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if (para->read_delays || para->write_delays) { |
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mctl_dq_delay(para->read_delays, para->write_delays); |
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udelay(50); |
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} |
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|
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mctl_zq_calibration(para); |
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|
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mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST | |
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PIR_DRAMINIT | PIR_QSGATE); |
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|
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/* detect ranks and bus width */ |
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if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { |
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/* only one rank */ |
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if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) || |
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((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) { |
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clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); |
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para->dual_rank = 0; |
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} |
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|
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/* only half DQ width */ |
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if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) || |
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((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) { |
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writel(0x0, &mctl_ctl->datx[2].gcr); |
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writel(0x0, &mctl_ctl->datx[3].gcr); |
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para->bus_width = 16; |
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} |
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|
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mctl_set_cr(para); |
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udelay(20); |
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|
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/* re-train */ |
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mctl_phy_init(PIR_QSGATE); |
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if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) |
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return 1; |
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} |
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|
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/* check the dramc status */ |
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mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); |
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|
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/* liuke added for refresh debug */ |
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setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); |
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udelay(10); |
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clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); |
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udelay(10); |
||||
|
||||
/* set PGCR3, CKE polarity */ |
||||
writel(0x00aa0060, &mctl_ctl->pgcr[3]); |
||||
|
||||
/* power down zq calibration module for power save */ |
||||
setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN); |
||||
|
||||
/* enable master access */ |
||||
writel(0xffffffff, &mctl_com->maer); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void mctl_auto_detect_dram_size(struct dram_para *para) |
||||
{ |
||||
/* detect row address bits */ |
||||
para->page_size = 512; |
||||
para->row_bits = 16; |
||||
mctl_set_cr(para); |
||||
|
||||
for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) |
||||
if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) |
||||
break; |
||||
|
||||
/* detect page size */ |
||||
para->page_size = 8192; |
||||
mctl_set_cr(para); |
||||
|
||||
for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2) |
||||
if (mctl_mem_matches(para->page_size)) |
||||
break; |
||||
} |
||||
|
||||
unsigned long sunxi_dram_init(void) |
||||
{ |
||||
struct sunxi_mctl_com_reg * const mctl_com = |
||||
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
||||
struct sunxi_mctl_ctl_reg * const mctl_ctl = |
||||
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
||||
|
||||
struct dram_para para = { |
||||
.read_delays = 0x00007979, |
||||
.write_delays = 0x6aaa0000, |
||||
.dual_rank = 0, |
||||
.bus_width = 32, |
||||
.row_bits = 15, |
||||
.page_size = 4096, |
||||
}; |
||||
|
||||
mctl_sys_init(¶); |
||||
if (mctl_channel_init(¶)) |
||||
return 0; |
||||
|
||||
if (para.dual_rank) |
||||
writel(0x00000303, &mctl_ctl->odtmap); |
||||
else |
||||
writel(0x00000201, &mctl_ctl->odtmap); |
||||
udelay(1); |
||||
|
||||
/* odt delay */ |
||||
writel(0x0c000400, &mctl_ctl->odtcfg); |
||||
|
||||
/* clear credit value */ |
||||
setbits_le32(&mctl_com->cccr, 1 << 31); |
||||
udelay(10); |
||||
|
||||
mctl_auto_detect_dram_size(¶); |
||||
mctl_set_cr(¶); |
||||
|
||||
return (1 << (para.row_bits + 3)) * para.page_size * |
||||
(para.dual_rank ? 2 : 1); |
||||
} |
@ -0,0 +1,297 @@ |
||||
/* |
||||
* Copyright 2015 Jelle de Jong <jelledejong@powercraft.nl> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include "sun7i-a20.dtsi" |
||||
#include "sunxi-common-regulators.dtsi" |
||||
|
||||
#include <dt-bindings/gpio/gpio.h> |
||||
#include <dt-bindings/interrupt-controller/irq.h> |
||||
#include <dt-bindings/pinctrl/sun4i-a10.h> |
||||
|
||||
/ { |
||||
model = "Lamobo R1"; |
||||
compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20"; |
||||
|
||||
aliases { |
||||
serial0 = &uart0; |
||||
serial1 = &uart3; |
||||
serial2 = &uart7; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
leds { |
||||
compatible = "gpio-leds"; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&led_pins_lamobo_r1>; |
||||
|
||||
green { |
||||
label = "lamobo_r1:green:usr"; |
||||
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
}; |
||||
|
||||
reg_gmac_3v3: gmac-3v3 { |
||||
compatible = "regulator-fixed"; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&gmac_power_pin_lamobo_r1>; |
||||
regulator-name = "gmac-3v3"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
startup-delay-us = <100000>; |
||||
enable-active-high; |
||||
gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ |
||||
}; |
||||
}; |
||||
|
||||
&ahci_pwr_pin_a { |
||||
allwinner,pins = "PB3"; |
||||
}; |
||||
|
||||
&ahci { |
||||
target-supply = <®_ahci_5v>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&cpu0 { |
||||
cpu-supply = <®_dcdc2>; |
||||
operating-points = < |
||||
/* kHz uV */ |
||||
960000 1400000 |
||||
912000 1400000 |
||||
864000 1350000 |
||||
720000 1250000 |
||||
528000 1150000 |
||||
312000 1100000 |
||||
144000 1050000 |
||||
>; |
||||
}; |
||||
|
||||
&ehci0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&gmac { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&gmac_pins_rgmii_a>; |
||||
phy = <&phy1>; |
||||
phy-mode = "rgmii"; |
||||
phy-supply = <®_gmac_3v3>; |
||||
status = "okay"; |
||||
|
||||
phy1: ethernet-phy@1 { |
||||
reg = <1>; |
||||
}; |
||||
}; |
||||
|
||||
&i2c0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&i2c0_pins_a>; |
||||
status = "okay"; |
||||
|
||||
axp209: pmic@34 { |
||||
reg = <0x34>; |
||||
interrupt-parent = <&nmi_intc>; |
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
||||
}; |
||||
}; |
||||
|
||||
&i2c2 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&i2c2_pins_a>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ir0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&ir0_rx_pins_a>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&mmc0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>; |
||||
vmmc-supply = <®_vcc3v3>; |
||||
bus-width = <4>; |
||||
cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ |
||||
cd-inverted; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&otg_sram { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&pio { |
||||
usb0_id_detect_pin: usb0_id_detect_pin@0 { |
||||
allwinner,pins = "PH4"; |
||||
allwinner,function = "gpio_in"; |
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; |
||||
}; |
||||
|
||||
mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 { |
||||
allwinner,pins = "PH10"; |
||||
allwinner,function = "gpio_in"; |
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; |
||||
}; |
||||
|
||||
gmac_power_pin_lamobo_r1: gmac_power_pin@0 { |
||||
allwinner,pins = "PH23"; |
||||
allwinner,function = "gpio_out"; |
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
||||
}; |
||||
|
||||
led_pins_lamobo_r1: led_pins@0 { |
||||
allwinner,pins = "PH24"; |
||||
allwinner,function = "gpio_out"; |
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
||||
}; |
||||
}; |
||||
|
||||
#include "axp209.dtsi" |
||||
|
||||
®_ahci_5v { |
||||
gpio = <&pio 1 3 0>; /* PB3 */ |
||||
status = "okay"; |
||||
}; |
||||
|
||||
®_dcdc2 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1000000>; |
||||
regulator-max-microvolt = <1400000>; |
||||
regulator-name = "vdd-cpu"; |
||||
}; |
||||
|
||||
®_dcdc3 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1000000>; |
||||
regulator-max-microvolt = <1400000>; |
||||
regulator-name = "vdd-int-dll"; |
||||
}; |
||||
|
||||
®_ldo1 { |
||||
regulator-name = "vdd-rtc"; |
||||
}; |
||||
|
||||
®_ldo2 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <3000000>; |
||||
regulator-max-microvolt = <3000000>; |
||||
regulator-name = "avcc"; |
||||
}; |
||||
|
||||
®_usb0_vbus { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
®_usb1_vbus { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
®_usb2_vbus { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&spi0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&spi0_pins_a>, |
||||
<&spi0_cs0_pins_a>, |
||||
<&spi0_cs1_pins_a>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart0_pins_a>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart3 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart3_pins_b>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart7 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart7_pins_a>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb_otg { |
||||
dr_mode = "otg"; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb_power_supply { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usbphy { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&usb0_id_detect_pin>; |
||||
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ |
||||
usb0_vbus_power-supply = <&usb_power_supply>; |
||||
usb0_vbus-supply = <®_usb0_vbus>; |
||||
usb1_vbus-supply = <®_usb1_vbus>; |
||||
usb2_vbus-supply = <®_usb2_vbus>; |
||||
status = "okay"; |
||||
}; |
@ -0,0 +1,106 @@ |
||||
/* |
||||
* Copyright (C) 2015 Chen-Yu Tsai <wens@csie.org> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include "sun8i-h3.dtsi" |
||||
#include "sunxi-common-regulators.dtsi" |
||||
|
||||
#include <dt-bindings/gpio/gpio.h> |
||||
#include <dt-bindings/pinctrl/sun4i-a10.h> |
||||
|
||||
/ { |
||||
model = "Xunlong Orange Pi PC"; |
||||
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; |
||||
|
||||
aliases { |
||||
serial0 = &uart0; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
}; |
||||
|
||||
&ehci1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci3 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&mmc0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; |
||||
vmmc-supply = <®_vcc3v3>; |
||||
bus-width = <4>; |
||||
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ |
||||
cd-inverted; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci3 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart0_pins_a>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usbphy { |
||||
/* USB VBUS is always on */ |
||||
status = "okay"; |
||||
}; |
@ -0,0 +1,121 @@ |
||||
/* |
||||
* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include "sun8i-h3.dtsi" |
||||
#include "sunxi-common-regulators.dtsi" |
||||
|
||||
#include <dt-bindings/gpio/gpio.h> |
||||
#include <dt-bindings/pinctrl/sun4i-a10.h> |
||||
|
||||
/ { |
||||
model = "Xunlong Orange Pi Plus"; |
||||
compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; |
||||
|
||||
aliases { |
||||
serial0 = &uart0; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
reg_usb3_vbus: usb3-vbus { |
||||
compatible = "regulator-fixed"; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&usb3_vbus_pin_a>; |
||||
regulator-name = "usb3-vbus"; |
||||
regulator-min-microvolt = <5000000>; |
||||
regulator-max-microvolt = <5000000>; |
||||
regulator-boot-on; |
||||
enable-active-high; |
||||
gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
}; |
||||
|
||||
&ehci1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci3 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&pio { |
||||
usb3_vbus_pin_a: usb3_vbus_pin@0 { |
||||
allwinner,pins = "PG11"; |
||||
allwinner,function = "gpio_out"; |
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
||||
}; |
||||
}; |
||||
|
||||
&mmc0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; |
||||
vmmc-supply = <®_vcc3v3>; |
||||
bus-width = <4>; |
||||
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ |
||||
cd-inverted; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
®_usb1_vbus { |
||||
gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart0_pins_a>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb1_vbus_pin_a { |
||||
allwinner,pins = "PG13"; |
||||
}; |
||||
|
||||
&usbphy { |
||||
usb1_vbus-supply = <®_usb1_vbus>; |
||||
usb3_vbus-supply = <®_usb3_vbus>; |
||||
status = "okay"; |
||||
}; |
@ -0,0 +1,595 @@ |
||||
/* |
||||
* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#include "skeleton.dtsi" |
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h> |
||||
#include <dt-bindings/pinctrl/sun4i-a10.h> |
||||
|
||||
/ { |
||||
interrupt-parent = <&gic>; |
||||
|
||||
cpus { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
cpu@0 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <0>; |
||||
}; |
||||
|
||||
cpu@1 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <1>; |
||||
}; |
||||
|
||||
cpu@2 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <2>; |
||||
}; |
||||
|
||||
cpu@3 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <3>; |
||||
}; |
||||
}; |
||||
|
||||
timer { |
||||
compatible = "arm,armv7-timer"; |
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
||||
clock-frequency = <24000000>; |
||||
arm,cpu-registers-not-fw-configured; |
||||
}; |
||||
|
||||
memory { |
||||
reg = <0x40000000 0x80000000>; |
||||
}; |
||||
|
||||
clocks { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
|
||||
osc24M: osc24M_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <24000000>; |
||||
clock-output-names = "osc24M"; |
||||
}; |
||||
|
||||
osc32k: osc32k_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <32768>; |
||||
clock-output-names = "osc32k"; |
||||
}; |
||||
|
||||
pll1: clk@01c20000 { |
||||
#clock-cells = <0>; |
||||
compatible = "allwinner,sun8i-a23-pll1-clk"; |
||||
reg = <0x01c20000 0x4>; |
||||
clocks = <&osc24M>; |
||||
clock-output-names = "pll1"; |
||||
}; |
||||
|
||||
/* dummy clock until actually implemented */ |
||||
pll5: pll5_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <0>; |
||||
clock-output-names = "pll5"; |
||||
}; |
||||
|
||||
pll6: clk@01c20028 { |
||||
#clock-cells = <1>; |
||||
compatible = "allwinner,sun6i-a31-pll6-clk"; |
||||
reg = <0x01c20028 0x4>; |
||||
clocks = <&osc24M>; |
||||
clock-output-names = "pll6", "pll6x2", "pll6d2"; |
||||
}; |
||||
|
||||
pll8: clk@01c20044 { |
||||
#clock-cells = <1>; |
||||
compatible = "allwinner,sun6i-a31-pll6-clk"; |
||||
reg = <0x01c20044 0x4>; |
||||
clocks = <&osc24M>; |
||||
clock-output-names = "pll8", "pll8x2"; |
||||
}; |
||||
|
||||
cpu: cpu_clk@01c20050 { |
||||
#clock-cells = <0>; |
||||
compatible = "allwinner,sun4i-a10-cpu-clk"; |
||||
reg = <0x01c20050 0x4>; |
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; |
||||
clock-output-names = "cpu"; |
||||
}; |
||||
|
||||
axi: axi_clk@01c20050 { |
||||
#clock-cells = <0>; |
||||
compatible = "allwinner,sun4i-a10-axi-clk"; |
||||
reg = <0x01c20050 0x4>; |
||||
clocks = <&cpu>; |
||||
clock-output-names = "axi"; |
||||
}; |
||||
|
||||
ahb1: ahb1_clk@01c20054 { |
||||
#clock-cells = <0>; |
||||
compatible = "allwinner,sun6i-a31-ahb1-clk"; |
||||
reg = <0x01c20054 0x4>; |
||||
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; |
||||
clock-output-names = "ahb1"; |
||||
}; |
||||
|
||||
ahb2: ahb2_clk@01c2005c { |
||||
#clock-cells = <0>; |
||||
compatible = "allwinner,sun8i-h3-ahb2-clk"; |
||||
reg = <0x01c2005c 0x4>; |
||||
clocks = <&ahb1>, <&pll6 2>; |
||||
clock-output-names = "ahb2"; |
||||
}; |
||||
|
||||
apb1: apb1_clk@01c20054 { |
||||
#clock-cells = <0>; |
||||
compatible = "allwinner,sun4i-a10-apb0-clk"; |
||||
reg = <0x01c20054 0x4>; |
||||
clocks = <&ahb1>; |
||||
clock-output-names = "apb1"; |
||||
}; |
||||
|
||||
apb2: apb2_clk@01c20058 { |
||||
#clock-cells = <0>; |
||||
compatible = "allwinner,sun4i-a10-apb1-clk"; |
||||
reg = <0x01c20058 0x4>; |
||||
clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; |
||||
clock-output-names = "apb2"; |
||||
}; |
||||
|
||||
bus_gates: clk@01c20060 { |
||||
#clock-cells = <1>; |
||||
compatible = "allwinner,sun8i-h3-bus-gates-clk"; |
||||
reg = <0x01c20060 0x14>; |
||||
clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; |
||||
clock-names = "ahb1", "ahb2", "apb1", "apb2"; |
||||
clock-indices = <5>, <6>, <8>, |
||||
<9>, <10>, <13>, |
||||
<14>, <17>, <18>, |
||||
<19>, <20>, |
||||
<21>, <23>, |
||||
<24>, <25>, |
||||
<26>, <27>, |
||||
<28>, <29>, |
||||
<30>, <31>, <32>, |
||||
<35>, <36>, <37>, |
||||
<40>, <41>, <43>, |
||||
<44>, <52>, <53>, |
||||
<54>, <64>, |
||||
<65>, <69>, <72>, |
||||
<76>, <77>, <78>, |
||||
<96>, <97>, <98>, |
||||
<112>, <113>, |
||||
<114>, <115>, <116>, |
||||
<128>, <135>; |
||||
clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", |
||||
"ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", |
||||
"ahb1_sdram", "ahb2_gmac", "ahb1_ts", |
||||
"ahb1_hstimer", "ahb1_spi0", |
||||
"ahb1_spi1", "ahb1_otg", |
||||
"ahb1_otg_ehci0", "ahb1_ehic1", |
||||
"ahb1_ehic2", "ahb1_ehic3", |
||||
"ahb1_otg_ohci0", "ahb2_ohic1", |
||||
"ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", |
||||
"ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", |
||||
"ahb1_csi", "ahb1_tve", "ahb1_hdmi", |
||||
"ahb1_de", "ahb1_gpu", "ahb1_msgbox", |
||||
"ahb1_spinlock", "apb1_codec", |
||||
"apb1_spdif", "apb1_pio", "apb1_ths", |
||||
"apb1_i2s0", "apb1_i2s1", "apb1_i2s2", |
||||
"apb2_i2c0", "apb2_i2c1", "apb2_i2c2", |
||||
"apb2_uart0", "apb2_uart1", |
||||
"apb2_uart2", "apb2_uart3", "apb2_scr", |
||||
"ahb1_ephy", "ahb1_dbg"; |
||||
}; |
||||
|
||||
mmc0_clk: clk@01c20088 { |
||||
#clock-cells = <1>; |
||||
compatible = "allwinner,sun4i-a10-mmc-clk"; |
||||
reg = <0x01c20088 0x4>; |
||||
clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; |
||||
clock-output-names = "mmc0", |
||||
"mmc0_output", |
||||
"mmc0_sample"; |
||||
}; |
||||
|
||||
mmc1_clk: clk@01c2008c { |
||||
#clock-cells = <1>; |
||||
compatible = "allwinner,sun4i-a10-mmc-clk"; |
||||
reg = <0x01c2008c 0x4>; |
||||
clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; |
||||
clock-output-names = "mmc1", |
||||
"mmc1_output", |
||||
"mmc1_sample"; |
||||
}; |
||||
|
||||
mmc2_clk: clk@01c20090 { |
||||
#clock-cells = <1>; |
||||
compatible = "allwinner,sun4i-a10-mmc-clk"; |
||||
reg = <0x01c20090 0x4>; |
||||
clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; |
||||
clock-output-names = "mmc2", |
||||
"mmc2_output", |
||||
"mmc2_sample"; |
||||
}; |
||||
|
||||
usb_clk: clk@01c200cc { |
||||
#clock-cells = <1>; |
||||
#reset-cells = <1>; |
||||
compatible = "allwinner,sun8i-h3-usb-clk"; |
||||
reg = <0x01c200cc 0x4>; |
||||
clocks = <&osc24M>; |
||||
clock-output-names = "usb_phy0", "usb_phy1", |
||||
"usb_phy2", "usb_phy3", |
||||
"usb_ohci0", "usb_ohci1", |
||||
"usb_ohci2", "usb_ohci3"; |
||||
}; |
||||
|
||||
mbus_clk: clk@01c2015c { |
||||
#clock-cells = <0>; |
||||
compatible = "allwinner,sun8i-a23-mbus-clk"; |
||||
reg = <0x01c2015c 0x4>; |
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5>; |
||||
clock-output-names = "mbus"; |
||||
}; |
||||
}; |
||||
|
||||
soc { |
||||
compatible = "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
|
||||
dma: dma-controller@01c02000 { |
||||
compatible = "allwinner,sun8i-h3-dma"; |
||||
reg = <0x01c02000 0x1000>; |
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&bus_gates 6>; |
||||
resets = <&bus_rst 6>; |
||||
#dma-cells = <1>; |
||||
}; |
||||
|
||||
mmc0: mmc@01c0f000 { |
||||
compatible = "allwinner,sun5i-a13-mmc"; |
||||
reg = <0x01c0f000 0x1000>; |
||||
clocks = <&bus_gates 8>, |
||||
<&mmc0_clk 0>, |
||||
<&mmc0_clk 1>, |
||||
<&mmc0_clk 2>; |
||||
clock-names = "ahb", |
||||
"mmc", |
||||
"output", |
||||
"sample"; |
||||
resets = <&bus_rst 8>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
mmc1: mmc@01c10000 { |
||||
compatible = "allwinner,sun5i-a13-mmc"; |
||||
reg = <0x01c10000 0x1000>; |
||||
clocks = <&bus_gates 9>, |
||||
<&mmc1_clk 0>, |
||||
<&mmc1_clk 1>, |
||||
<&mmc1_clk 2>; |
||||
clock-names = "ahb", |
||||
"mmc", |
||||
"output", |
||||
"sample"; |
||||
resets = <&bus_rst 9>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
mmc2: mmc@01c11000 { |
||||
compatible = "allwinner,sun5i-a13-mmc"; |
||||
reg = <0x01c11000 0x1000>; |
||||
clocks = <&bus_gates 10>, |
||||
<&mmc2_clk 0>, |
||||
<&mmc2_clk 1>, |
||||
<&mmc2_clk 2>; |
||||
clock-names = "ahb", |
||||
"mmc", |
||||
"output", |
||||
"sample"; |
||||
resets = <&bus_rst 10>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
usbphy: phy@01c19400 { |
||||
compatible = "allwinner,sun8i-h3-usb-phy"; |
||||
reg = <0x01c19400 0x2c>, |
||||
<0x01c1a800 0x4>, |
||||
<0x01c1b800 0x4>, |
||||
<0x01c1c800 0x4>, |
||||
<0x01c1d800 0x4>; |
||||
reg-names = "phy_ctrl", |
||||
"pmu0", |
||||
"pmu1", |
||||
"pmu2", |
||||
"pmu3"; |
||||
clocks = <&usb_clk 8>, |
||||
<&usb_clk 9>, |
||||
<&usb_clk 10>, |
||||
<&usb_clk 11>; |
||||
clock-names = "usb0_phy", |
||||
"usb1_phy", |
||||
"usb2_phy", |
||||
"usb3_phy"; |
||||
resets = <&usb_clk 0>, |
||||
<&usb_clk 1>, |
||||
<&usb_clk 2>, |
||||
<&usb_clk 3>; |
||||
reset-names = "usb0_reset", |
||||
"usb1_reset", |
||||
"usb2_reset", |
||||
"usb3_reset"; |
||||
status = "disabled"; |
||||
#phy-cells = <1>; |
||||
}; |
||||
|
||||
ehci1: usb@01c1b000 { |
||||
compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; |
||||
reg = <0x01c1b000 0x100>; |
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&bus_gates 25>, <&bus_gates 29>; |
||||
resets = <&bus_rst 25>, <&bus_rst 29>; |
||||
phys = <&usbphy 1>; |
||||
phy-names = "usb"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
ohci1: usb@01c1b400 { |
||||
compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; |
||||
reg = <0x01c1b400 0x100>; |
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&bus_gates 29>, <&bus_gates 25>, |
||||
<&usb_clk 17>; |
||||
resets = <&bus_rst 29>, <&bus_rst 25>; |
||||
phys = <&usbphy 1>; |
||||
phy-names = "usb"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
ehci2: usb@01c1c000 { |
||||
compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; |
||||
reg = <0x01c1c000 0x100>; |
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&bus_gates 26>, <&bus_gates 30>; |
||||
resets = <&bus_rst 26>, <&bus_rst 30>; |
||||
phys = <&usbphy 2>; |
||||
phy-names = "usb"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
ohci2: usb@01c1c400 { |
||||
compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; |
||||
reg = <0x01c1c400 0x100>; |
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&bus_gates 30>, <&bus_gates 26>, |
||||
<&usb_clk 18>; |
||||
resets = <&bus_rst 30>, <&bus_rst 26>; |
||||
phys = <&usbphy 2>; |
||||
phy-names = "usb"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
ehci3: usb@01c1d000 { |
||||
compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; |
||||
reg = <0x01c1d000 0x100>; |
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&bus_gates 27>, <&bus_gates 31>; |
||||
resets = <&bus_rst 27>, <&bus_rst 31>; |
||||
phys = <&usbphy 3>; |
||||
phy-names = "usb"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
ohci3: usb@01c1d400 { |
||||
compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; |
||||
reg = <0x01c1d400 0x100>; |
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&bus_gates 31>, <&bus_gates 27>, |
||||
<&usb_clk 19>; |
||||
resets = <&bus_rst 31>, <&bus_rst 27>; |
||||
phys = <&usbphy 3>; |
||||
phy-names = "usb"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
pio: pinctrl@01c20800 { |
||||
compatible = "allwinner,sun8i-h3-pinctrl"; |
||||
reg = <0x01c20800 0x400>; |
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&bus_gates 69>; |
||||
gpio-controller; |
||||
#gpio-cells = <3>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
|
||||
uart0_pins_a: uart0@0 { |
||||
allwinner,pins = "PA4", "PA5"; |
||||
allwinner,function = "uart0"; |
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
||||
}; |
||||
|
||||
mmc0_pins_a: mmc0@0 { |
||||
allwinner,pins = "PF0", "PF1", "PF2", "PF3", |
||||
"PF4", "PF5"; |
||||
allwinner,function = "mmc0"; |
||||
allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
||||
}; |
||||
|
||||
mmc0_cd_pin: mmc0_cd_pin@0 { |
||||
allwinner,pins = "PF6"; |
||||
allwinner,function = "gpio_in"; |
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; |
||||
}; |
||||
|
||||
mmc1_pins_a: mmc1@0 { |
||||
allwinner,pins = "PG0", "PG1", "PG2", "PG3", |
||||
"PG4", "PG5"; |
||||
allwinner,function = "mmc1"; |
||||
allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
||||
}; |
||||
}; |
||||
|
||||
bus_rst: reset@01c202c0 { |
||||
#reset-cells = <1>; |
||||
compatible = "allwinner,sun8i-h3-bus-reset"; |
||||
reg = <0x01c202c0 0x1c>; |
||||
}; |
||||
|
||||
timer@01c20c00 { |
||||
compatible = "allwinner,sun4i-a10-timer"; |
||||
reg = <0x01c20c00 0xa0>; |
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&osc24M>; |
||||
}; |
||||
|
||||
wdt0: watchdog@01c20ca0 { |
||||
compatible = "allwinner,sun6i-a31-wdt"; |
||||
reg = <0x01c20ca0 0x20>; |
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
||||
}; |
||||
|
||||
uart0: serial@01c28000 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28000 0x400>; |
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&bus_gates 112>; |
||||
resets = <&bus_rst 144>; |
||||
dmas = <&dma 6>, <&dma 6>; |
||||
dma-names = "rx", "tx"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart1: serial@01c28400 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28400 0x400>; |
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&bus_gates 113>; |
||||
resets = <&bus_rst 145>; |
||||
dmas = <&dma 7>, <&dma 7>; |
||||
dma-names = "rx", "tx"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart2: serial@01c28800 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28800 0x400>; |
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&bus_gates 114>; |
||||
resets = <&bus_rst 146>; |
||||
dmas = <&dma 8>, <&dma 8>; |
||||
dma-names = "rx", "tx"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart3: serial@01c28c00 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28c00 0x400>; |
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&bus_gates 115>; |
||||
resets = <&bus_rst 147>; |
||||
dmas = <&dma 9>, <&dma 9>; |
||||
dma-names = "rx", "tx"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
gic: interrupt-controller@01c81000 { |
||||
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
||||
reg = <0x01c81000 0x1000>, |
||||
<0x01c82000 0x1000>, |
||||
<0x01c84000 0x2000>, |
||||
<0x01c86000 0x2000>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
||||
}; |
||||
|
||||
rtc: rtc@01f00000 { |
||||
compatible = "allwinner,sun6i-a31-rtc"; |
||||
reg = <0x01f00000 0x54>; |
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
||||
}; |
||||
}; |
||||
}; |
@ -0,0 +1,185 @@ |
||||
/*
|
||||
* sun8i H3 platform dram controller register and constant defines |
||||
* |
||||
* (C) Copyright 2007-2015 Allwinner Technology Co. |
||||
* Jerry Wang <wangflord@allwinnertech.com> |
||||
* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> |
||||
* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> |
||||
* (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _SUNXI_DRAM_SUN8I_H3_H |
||||
#define _SUNXI_DRAM_SUN8I_H3_H |
||||
|
||||
struct sunxi_mctl_com_reg { |
||||
u32 cr; /* 0x00 control register */ |
||||
u8 res0[0xc]; /* 0x04 */ |
||||
u32 mcr[16][2]; /* 0x10 */ |
||||
u32 bwcr; /* 0x90 bandwidth control register */ |
||||
u32 maer; /* 0x94 master enable register */ |
||||
u32 mapr; /* 0x98 master priority register */ |
||||
u32 mcgcr; /* 0x9c */ |
||||
u32 cpu_bwcr; /* 0xa0 */ |
||||
u32 gpu_bwcr; /* 0xa4 */ |
||||
u32 ve_bwcr; /* 0xa8 */ |
||||
u32 disp_bwcr; /* 0xac */ |
||||
u32 other_bwcr; /* 0xb0 */ |
||||
u32 total_bwcr; /* 0xb4 */ |
||||
u8 res1[0x8]; /* 0xb8 */ |
||||
u32 swonr; /* 0xc0 */ |
||||
u32 swoffr; /* 0xc4 */ |
||||
u8 res2[0x8]; /* 0xc8 */ |
||||
u32 cccr; /* 0xd0 */ |
||||
u8 res3[0x72c]; /* 0xd4 */ |
||||
u32 protect; /* 0x800 */ |
||||
}; |
||||
|
||||
#define MCTL_CR_BL8 (0x4 << 20) |
||||
|
||||
#define MCTL_CR_1T (0x1 << 19) |
||||
#define MCTL_CR_2T (0x0 << 19) |
||||
|
||||
#define MCTL_CR_LPDDR3 (0x7 << 16) |
||||
#define MCTL_CR_LPDDR2 (0x6 << 16) |
||||
#define MCTL_CR_DDR3 (0x3 << 16) |
||||
#define MCTL_CR_DDR2 (0x2 << 16) |
||||
|
||||
#define MCTL_CR_SEQUENTIAL (0x1 << 15) |
||||
#define MCTL_CR_INTERLEAVED (0x0 << 15) |
||||
|
||||
#define MCTL_CR_32BIT (0x1 << 12) |
||||
#define MCTL_CR_16BIT (0x0 << 12) |
||||
#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT) |
||||
|
||||
#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) |
||||
#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) |
||||
#define MCTL_CR_EIGHT_BANKS (0x1 << 2) |
||||
#define MCTL_CR_FOUR_BANKS (0x0 << 2) |
||||
#define MCTL_CR_DUAL_RANK (0x1 << 0) |
||||
#define MCTL_CR_SINGLE_RANK (0x0 << 0) |
||||
|
||||
#define PROTECT_MAGIC (0x94be6fa3) |
||||
|
||||
struct sunxi_mctl_ctl_reg { |
||||
u32 pir; /* 0x00 PHY initialization register */ |
||||
u32 pwrctl; /* 0x04 */ |
||||
u32 mrctrl; /* 0x08 */ |
||||
u32 clken; /* 0x0c */ |
||||
u32 pgsr[2]; /* 0x10 PHY general status registers */ |
||||
u32 statr; /* 0x18 */ |
||||
u8 res1[0x14]; /* 0x1c */ |
||||
u32 mr[4]; /* 0x30 mode registers */ |
||||
u32 pllgcr; /* 0x40 */ |
||||
u32 ptr[5]; /* 0x44 PHY timing registers */ |
||||
u32 dramtmg[9]; /* 0x58 DRAM timing registers */ |
||||
u32 odtcfg; /* 0x7c */ |
||||
u32 pitmg[2]; /* 0x80 PHY interface timing registers */ |
||||
u8 res2[0x4]; /* 0x88 */ |
||||
u32 rfshctl0; /* 0x8c */ |
||||
u32 rfshtmg; /* 0x90 refresh timing */ |
||||
u32 rfshctl1; /* 0x94 */ |
||||
u32 pwrtmg; /* 0x98 */ |
||||
u8 res3[0x20]; /* 0x9c */ |
||||
u32 dqsgmr; /* 0xbc */ |
||||
u32 dtcr; /* 0xc0 */ |
||||
u32 dtar[4]; /* 0xc4 */ |
||||
u32 dtdr[2]; /* 0xd4 */ |
||||
u32 dtmr[2]; /* 0xdc */ |
||||
u32 dtbmr; /* 0xe4 */ |
||||
u32 catr[2]; /* 0xe8 */ |
||||
u32 dtedr[2]; /* 0xf0 */ |
||||
u8 res4[0x8]; /* 0xf8 */ |
||||
u32 pgcr[4]; /* 0x100 PHY general configuration registers */ |
||||
u32 iovcr[2]; /* 0x110 */ |
||||
u32 dqsdr; /* 0x118 */ |
||||
u32 dxccr; /* 0x11c */ |
||||
u32 odtmap; /* 0x120 */ |
||||
u32 zqctl[2]; /* 0x124 */ |
||||
u8 res6[0x14]; /* 0x12c */ |
||||
u32 zqcr; /* 0x140 ZQ control register */ |
||||
u32 zqsr; /* 0x144 ZQ status register */ |
||||
u32 zqdr[3]; /* 0x148 ZQ data registers */ |
||||
u8 res7[0x6c]; /* 0x154 */ |
||||
u32 sched; /* 0x1c0 */ |
||||
u32 perfhpr[2]; /* 0x1c4 */ |
||||
u32 perflpr[2]; /* 0x1cc */ |
||||
u32 perfwr[2]; /* 0x1d4 */ |
||||
u8 res8[0x2c]; /* 0x1dc */ |
||||
u32 aciocr; /* 0x208 */ |
||||
u8 res9[0xf4]; /* 0x20c */ |
||||
struct { /* 0x300 DATX8 modules*/ |
||||
u32 mdlr; /* 0x00 */ |
||||
u32 lcdlr[3]; /* 0x04 */ |
||||
u32 iocr[11]; /* 0x10 IO configuration register */ |
||||
u32 bdlr6; /* 0x3c */ |
||||
u32 gtr; /* 0x40 */ |
||||
u32 gcr; /* 0x44 */ |
||||
u32 gsr[3]; /* 0x48 */ |
||||
u8 res0[0x2c]; /* 0x54 */ |
||||
} datx[4]; |
||||
u8 res10[0x388]; /* 0x500 */ |
||||
u32 upd2; /* 0x888 */ |
||||
}; |
||||
|
||||
#define PTR3_TDINIT1(x) ((x) << 20) |
||||
#define PTR3_TDINIT0(x) ((x) << 0) |
||||
|
||||
#define PTR4_TDINIT3(x) ((x) << 20) |
||||
#define PTR4_TDINIT2(x) ((x) << 0) |
||||
|
||||
#define DRAMTMG0_TWTP(x) ((x) << 24) |
||||
#define DRAMTMG0_TFAW(x) ((x) << 16) |
||||
#define DRAMTMG0_TRAS_MAX(x) ((x) << 8) |
||||
#define DRAMTMG0_TRAS(x) ((x) << 0) |
||||
|
||||
#define DRAMTMG1_TXP(x) ((x) << 16) |
||||
#define DRAMTMG1_TRTP(x) ((x) << 8) |
||||
#define DRAMTMG1_TRC(x) ((x) << 0) |
||||
|
||||
#define DRAMTMG2_TCWL(x) ((x) << 24) |
||||
#define DRAMTMG2_TCL(x) ((x) << 16) |
||||
#define DRAMTMG2_TRD2WR(x) ((x) << 8) |
||||
#define DRAMTMG2_TWR2RD(x) ((x) << 0) |
||||
|
||||
#define DRAMTMG3_TMRW(x) ((x) << 16) |
||||
#define DRAMTMG3_TMRD(x) ((x) << 12) |
||||
#define DRAMTMG3_TMOD(x) ((x) << 0) |
||||
|
||||
#define DRAMTMG4_TRCD(x) ((x) << 24) |
||||
#define DRAMTMG4_TCCD(x) ((x) << 16) |
||||
#define DRAMTMG4_TRRD(x) ((x) << 8) |
||||
#define DRAMTMG4_TRP(x) ((x) << 0) |
||||
|
||||
#define DRAMTMG5_TCKSRX(x) ((x) << 24) |
||||
#define DRAMTMG5_TCKSRE(x) ((x) << 16) |
||||
#define DRAMTMG5_TCKESR(x) ((x) << 8) |
||||
#define DRAMTMG5_TCKE(x) ((x) << 0) |
||||
|
||||
#define RFSHTMG_TREFI(x) ((x) << 16) |
||||
#define RFSHTMG_TRFC(x) ((x) << 0) |
||||
|
||||
#define PIR_CLRSR (0x1 << 27) /* clear status registers */ |
||||
#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */ |
||||
#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */ |
||||
#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */ |
||||
#define PIR_PHYRST (0x1 << 6) /* PHY reset */ |
||||
#define PIR_DCAL (0x1 << 5) /* DDL calibration */ |
||||
#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */ |
||||
#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */ |
||||
#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */ |
||||
|
||||
#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */ |
||||
|
||||
#define ZQCR_PWRDOWN (0x1 << 31) /* ZQ power down */ |
||||
|
||||
#define DATX_IOCR_DQ(x) (x) /* DQ0-7 IOCR index */ |
||||
#define DATX_IOCR_DM (8) /* DM IOCR index */ |
||||
#define DATX_IOCR_DQS (9) /* DQS IOCR index */ |
||||
#define DATX_IOCR_DQSN (10) /* DQSN IOCR index */ |
||||
|
||||
#define DATX_IOCR_WRITE_DELAY(x) ((x) << 8) |
||||
#define DATX_IOCR_READ_DELAY(x) ((x) << 0) |
||||
|
||||
#endif /* _SUNXI_DRAM_SUN8I_H3_H */ |
@ -0,0 +1,16 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_SUNXI=y |
||||
CONFIG_MACH_SUN7I=y |
||||
CONFIG_DRAM_CLK=432 |
||||
CONFIG_MMC0_CD_PIN="PH10" |
||||
CONFIG_GMAC_TX_DELAY=4 |
||||
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1" |
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)" |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_ETH_DESIGNWARE=y |
||||
CONFIG_USB_EHCI_HCD=y |
@ -0,0 +1,15 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_SUNXI=y |
||||
CONFIG_MACH_SUN8I_H3=y |
||||
CONFIG_DRAM_CLK=672 |
||||
CONFIG_DRAM_ZQ=3881979 |
||||
CONFIG_DRAM_ODT_EN=y |
||||
# CONFIG_VIDEO is not set |
||||
# CONFIG_USB_KEYBOARD is not set |
||||
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" |
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
||||
CONFIG_SPL=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
@ -0,0 +1,15 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_SUNXI=y |
||||
CONFIG_MACH_SUN8I_H3=y |
||||
CONFIG_DRAM_CLK=672 |
||||
CONFIG_DRAM_ZQ=3881979 |
||||
CONFIG_DRAM_ODT_EN=y |
||||
# CONFIG_VIDEO is not set |
||||
# CONFIG_USB_KEYBOARD is not set |
||||
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus" |
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
||||
CONFIG_SPL=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
Loading…
Reference in new issue