* 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E powerpc/mpc85xx: Workaround for erratum CPU_A011 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER() powerpc/P4080: Check SVR for CPU22 workaround lib/powerpc: addrmap_phys_to_virt() should return a pointer powerpc/85xx: clean up P1022DS board configuration header file powerpc/85xx: fdt_set_phy_handle() should return an error code powerpc/85xx: minor clean-ups to the P2020DS board header file powerpc/p1010rdb: add readme document for p1010rdb powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting powerpc/mpc85xx:Add debugger support for e500v2 SoC powerpc/85xx:Fix NAND code base to support debugger powerpc/85xx:Make debug exception vector accessible powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger PATCH 1/4][v4] doc:Add documentation for e500 external debugger support powerpc/p1010rdb: update mux config of p1010rdb board powerpc/mpc85xx:Add BSC9131 RDB Support powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support powerpc/85xx: Add USB device-tree fixup for various platforms Signed-off-by: Wolfgang Denk <wd@denx.de>master
Wolfgang Denk
13 years ago
commit
8246ff864d
@ -0,0 +1,53 @@ |
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#
|
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# Copyright 2011-2012 Freescale Semiconductor, Inc.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
|
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#
|
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|
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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#COBJS-y += bsc9131rdb_mux.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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|
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS))
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clean: |
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rm -f $(OBJS) $(SOBJS)
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|
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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|
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#########################################################################
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|
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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|
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sinclude $(obj).depend |
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|
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#########################################################################
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@ -0,0 +1,137 @@ |
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Overview |
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-------- |
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- BSC9131 is integrated device that targets Femto base station market. |
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It combines Power Architecture e500v2 and DSP StarCore SC3850 core |
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technologies with MAPLE-B2F baseband acceleration processing elements. |
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- It's MAPLE disabled personality is called 9231. |
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|
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The BSC9131 SoC includes the following function and features: |
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. Power Architecture subsystem including a e500 processor with 256-Kbyte shared |
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L2 cache |
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. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache |
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. The Multi Accelerator Platform Engine for Femto BaseStation Baseband |
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Processing (MAPLE-B2F) |
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. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, |
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Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, |
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and CRC algorithms |
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. Consists of accelerators for Convolution, Filtering, Turbo Encoding, |
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Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion |
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operations |
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. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with |
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ECC, up to 400-MHz clock/800 MHz data rate |
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. Dedicated security engine featuring trusted boot |
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. DMA controller |
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. OCNDMA with four bidirectional channels |
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. Interfaces |
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. Two triple-speed Gigabit Ethernet controllers featuring network acceleration |
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including IEEE 1588. v2 hardware support and virtualization (eTSEC) |
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. eTSEC 1 supports RGMII/RMII |
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. eTSEC 2 supports RGMII |
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. High-speed USB 2.0 host and device controller with ULPI interface |
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. Enhanced secure digital (SD/MMC) host controller (eSDHC) |
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. Antenna interface controller (AIC), supporting three industry standard |
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JESD207/three custom ADI RF interfaces (two dual port and one single port) |
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and three MAXIM's MaxPHY serial interfaces |
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. ADI lanes support both full duplex FDD support and half duplex TDD support |
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. Universal Subscriber Identity Module (USIM) interface that facilitates |
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communication to SIM cards or Eurochip pre-paid phone cards |
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. TDM with one TDM port |
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. Two DUART, four eSPI, and two I2C controllers |
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. Integrated Flash memory controller (IFC) |
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. TDM with 256 channels |
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. GPIO |
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. Sixteen 32-bit timers |
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|
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The e500 core subsystem within the Power Architecture consists of the following: |
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. 32-Kbyte L1 instruction cache |
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. 32-Kbyte L1 data cache |
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. 256-Kbyte L2 cache/L2 memory/L2 stash |
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. programmable interrupt controller (PIC) |
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. Debug support |
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. Timers |
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|
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The SC3850 core subsystem consists of the following: |
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. 32 Kbyte 8-way level 1 instruction cache (L1 ICache) |
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. 32 Kbyte 8-way level 1 data cache (L1 DCache) |
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. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory) |
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. Memory management unit (MMU) |
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. Enhanced programmable interrupt controller (EPIC) |
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. Debug and profiling unit (DPU) |
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. Two 32-bit timers |
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|
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BSC9131RDB board Overview |
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------------------------- |
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1Gbyte DDR3 (on board DDR) |
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128Mbyte 2K page size NAND Flash |
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256 Kbit M24256 I2C EEPROM |
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128 Mbit SPI Flash memory |
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USB-ULPI |
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eTSEC1: Connected to RGMII PHY |
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eTSEC2: Connected to RGMII PHY |
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DUART interface: supports one UARTs up to 115200 bps for console display |
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USIM connector |
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|
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Frequency Combinations Supported |
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-------------------------------- |
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Core MHz/CCB MHz/DDR(MT/s) |
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1. 1000/500/800 |
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2. 800/400/667 |
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|
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Boot Methods Supported |
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----------------------- |
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1. NAND Flash |
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2. SPI Flash |
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|
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Default Boot Method |
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-------------------- |
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NAND boot |
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|
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Building U-boot |
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-------------- |
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To build the u-boot for BSC9131RDB: |
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1. NAND Flash |
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make BSC9131RDB_NAND |
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2. SPI Flash |
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make BSC9131RDB_SPIFLASH |
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|
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Memory map |
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----------- |
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0x0000_0000 0x7FFF_FFFF DDR 1G cacheable |
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0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M |
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0xC100_0000 0xC13F_FFFF MAPLE-2F 4M |
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0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K |
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0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K |
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0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K |
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0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K |
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0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M |
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0xFF70_0000 0xFF7F_FFFF PA CCSR 1M |
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0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M |
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|
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Flashing Images |
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--------------- |
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To place a new u-boot image in the NAND flash and then boot |
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with that new image temporarily, use this: |
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tftp 1000000 u-boot-nand.bin |
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nand erase 0 100000 |
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nand write 1000000 0 100000 |
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reset |
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|
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Using the Device Tree Source File |
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--------------------------------- |
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To create the DTB (Device Tree Binary) image file, |
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use a command similar to this: |
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dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb |
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|
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Likely, that .dts file will come from here; |
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|
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linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts |
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|
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Booting Linux |
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------------- |
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Place a linux uImage in the TFTP disk area. |
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|
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tftp 1000000 uImage |
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tftp 2000000 rootfs.ext2.gz.uboot |
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tftp c00000 bsc9131rdb.dtb |
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bootm 1000000 2000000 c00000 |
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@ -0,0 +1,83 @@ |
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/*
|
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* Copyright 2011-2012 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
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#include <common.h> |
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#include <asm/processor.h> |
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#include <asm/mmu.h> |
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#include <asm/cache.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/io.h> |
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#include <miiphy.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#include <fsl_mdio.h> |
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#include <tsec.h> |
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#include <netdev.h> |
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|
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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int board_early_init_f(void) |
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{ |
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
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|
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clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42); |
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setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS); |
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|
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clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43); |
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setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK | |
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MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD); |
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setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0); |
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clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK | |
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MPC85xx_PMUXCR_IFC_AD17_GPO_MASK, |
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MPC85xx_PMUXCR_IFC_AD_GPIO | |
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MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM); |
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|
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return 0; |
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} |
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|
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int checkboard(void) |
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{ |
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struct cpu_type *cpu; |
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|
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cpu = gd->cpu; |
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printf("Board: %sRDB\n", cpu->name); |
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|
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return 0; |
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} |
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|
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#if defined(CONFIG_OF_BOARD_SETUP) |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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phys_addr_t base; |
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phys_size_t size; |
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ft_cpu_setup(blob, bd); |
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|
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base = getenv_bootm_low(); |
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size = getenv_bootm_size(); |
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fdt_fixup_memory(blob, (u64)base, (u64)size); |
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|
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fdt_fixup_dr_usb(blob, bd); |
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} |
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#endif |
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@ -0,0 +1,187 @@ |
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/*
|
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* Copyright 2011-2012 Freescale Semiconductor, Inc. |
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* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/mmu.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/processor.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include <asm/fsl_ddr_dimm_params.h> |
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#include <asm/io.h> |
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#include <asm/fsl_law.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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#ifndef CONFIG_SYS_DDR_RAW_TIMING |
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#define CONFIG_SYS_DRAM_SIZE 1024 |
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|
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { |
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, |
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, |
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, |
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, |
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, |
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, |
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, |
||||
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, |
||||
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, |
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, |
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, |
||||
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, |
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, |
||||
.ddr_data_init = CONFIG_MEM_INIT_VALUE, |
||||
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, |
||||
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, |
||||
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, |
||||
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, |
||||
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, |
||||
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, |
||||
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, |
||||
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, |
||||
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, |
||||
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 |
||||
}; |
||||
|
||||
fixed_ddr_parm_t fixed_ddr_parm_0[] = { |
||||
{750, 850, &ddr_cfg_regs_800}, |
||||
{0, 0, NULL} |
||||
}; |
||||
|
||||
unsigned long get_sdram_size(void) |
||||
{ |
||||
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE); |
||||
} |
||||
|
||||
/*
|
||||
* Fixed sdram init -- doesn't use serial presence detect. |
||||
*/ |
||||
phys_size_t fixed_sdram(void) |
||||
{ |
||||
int i; |
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char buf[32]; |
||||
fsl_ddr_cfg_regs_t ddr_cfg_regs; |
||||
phys_size_t ddr_size; |
||||
ulong ddr_freq, ddr_freq_mhz; |
||||
|
||||
ddr_freq = get_ddr_freq(0); |
||||
ddr_freq_mhz = ddr_freq / 1000000; |
||||
|
||||
printf("Configuring DDR for %s MT/s data rate\n", |
||||
strmhz(buf, ddr_freq)); |
||||
|
||||
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { |
||||
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && |
||||
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { |
||||
memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, |
||||
sizeof(ddr_cfg_regs)); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if (fixed_ddr_parm_0[i].max_freq == 0) { |
||||
panic("Unsupported DDR data rate %s MT/s data rate\n", |
||||
strmhz(buf, ddr_freq)); |
||||
} |
||||
|
||||
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
||||
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); |
||||
|
||||
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, |
||||
LAW_TRGT_IF_DDR_1) < 0) { |
||||
printf("ERROR setting Local Access Windows for DDR\n"); |
||||
return 0; |
||||
} |
||||
|
||||
return ddr_size; |
||||
} |
||||
|
||||
#else /* CONFIG_SYS_DDR_RAW_TIMING */ |
||||
/* Micron MT41J256M8HX-15E */ |
||||
dimm_params_t ddr_raw_timing = { |
||||
.n_ranks = 1, |
||||
.rank_density = 1073741824u, |
||||
.capacity = 1073741824u, |
||||
.primary_sdram_width = 32, |
||||
.ec_sdram_width = 0, |
||||
.registered_dimm = 0, |
||||
.mirrored_dimm = 0, |
||||
.n_row_addr = 15, |
||||
.n_col_addr = 10, |
||||
.n_banks_per_sdram_device = 8, |
||||
.edc_config = 0, |
||||
.burst_lengths_bitmask = 0x0c, |
||||
|
||||
.tCKmin_X_ps = 1870, |
||||
.caslat_X = 0x1e << 4, /* 5,6,7,8 */ |
||||
.tAA_ps = 13125, |
||||
.tWR_ps = 15000, |
||||
.tRCD_ps = 13125, |
||||
.tRRD_ps = 7500, |
||||
.tRP_ps = 13125, |
||||
.tRAS_ps = 37500, |
||||
.tRC_ps = 50625, |
||||
.tRFC_ps = 160000, |
||||
.tWTR_ps = 7500, |
||||
.tRTP_ps = 7500, |
||||
.refresh_rate_ps = 7800000, |
||||
.tFAW_ps = 37500, |
||||
}; |
||||
|
||||
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, |
||||
unsigned int controller_number, |
||||
unsigned int dimm_number) |
||||
{ |
||||
const char dimm_model[] = "Fixed DDR on board"; |
||||
|
||||
if ((controller_number == 0) && (dimm_number == 0)) { |
||||
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); |
||||
memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); |
||||
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
int i; |
||||
popts->clk_adjust = 6; |
||||
popts->cpo_override = 0x1f; |
||||
popts->write_data_delay = 2; |
||||
popts->half_strength_driver_enable = 1; |
||||
/* Write leveling override */ |
||||
popts->wrlvl_en = 1; |
||||
popts->wrlvl_override = 1; |
||||
popts->wrlvl_sample = 0xf; |
||||
popts->wrlvl_start = 0x8; |
||||
popts->trwt_override = 1; |
||||
popts->trwt = 0; |
||||
|
||||
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
||||
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; |
||||
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; |
||||
} |
||||
} |
||||
|
||||
#endif /* CONFIG_SYS_DDR_RAW_TIMING */ |
||||
@ -0,0 +1,31 @@ |
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,67 @@ |
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , |
||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , |
||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , |
||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/* TLB 1 */ |
||||
/* *I*** - Covers boot page */ |
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_4K, 1), |
||||
|
||||
/* *I*G* - CCSRBAR (PA) */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 8, BOOKE_PAGESZ_1G, 1), |
||||
#endif |
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_1M, 1) |
||||
|
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -0,0 +1,212 @@ |
||||
Overview |
||||
========= |
||||
The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. |
||||
|
||||
The P1010 is a cost-effective, low-power, highly integrated host processor |
||||
based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), |
||||
that addresses the requirements of several routing, gateways, storage, consumer, |
||||
and industrial applications. Applications of interest include the main CPUs and |
||||
I/O processors in network attached storage (NAS), the voice over IP (VoIP) |
||||
router/gateway, and wireless LAN (WLAN) and industrial controllers. |
||||
|
||||
The P1010RDB board features are as follows: |
||||
Memory subsystem: |
||||
- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) |
||||
- 32 Mbyte NOR flash single-chip memory |
||||
- 32 Mbyte NAND flash memory |
||||
- 256 Kbit M24256 I2C EEPROM |
||||
- 16 Mbyte SPI memory |
||||
- I2C Board EEPROM 128x8 bit memory |
||||
- SD/MMC connector to interface with the SD memory card |
||||
Interfaces: |
||||
- PCIe: |
||||
- Lane0: x1 mini-PCIe slot |
||||
- Lane1: x1 PCIe standard slot |
||||
- SATA: |
||||
- 1 internal SATA connector to 2.5” 160G SATA2 HDD |
||||
- 1 eSATA connector to rear panel |
||||
- 10/100/1000 BaseT Ethernet ports: |
||||
- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO |
||||
- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 |
||||
- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 |
||||
- USB 2.0 port: |
||||
- x1 USB2.0 port via an external ULPI PHY to micro-AB connector |
||||
- x1 USB2.0 port via an internal UTMI PHY to micro-AB connector |
||||
- FlexCAN ports: |
||||
- 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) |
||||
interface; |
||||
- DUART interface: |
||||
- DUART interface: supports two UARTs up to 115200 bps for |
||||
console display |
||||
- RJ45 connectors are used for these 2 UART ports. |
||||
- TDM |
||||
- 2 FXS ports connected via an external SLIC to the TDM interface. |
||||
SLIC is controllled via SPI. |
||||
- 1 FXO port connected via a relay to FXS for switchover to POTS |
||||
Board connectors: |
||||
- Mini-ITX power supply connector |
||||
- JTAG/COP for debugging |
||||
IEEE Std. 1588 signals for test and measurement |
||||
Real-time clock on I2C bus |
||||
POR |
||||
- support critical POR setting changed via switch on board |
||||
PCB |
||||
- 6-layer routing (4-layer signals, 2-layer power and ground) |
||||
|
||||
|
||||
Physical Memory Map on P1010RDB |
||||
=============================== |
||||
Address Start Address End Memory type Attributes |
||||
0x0000_0000 0x3fff_ffff DDR 1G Cacheable |
||||
0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable |
||||
0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable |
||||
0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable |
||||
0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable |
||||
0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable |
||||
0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 |
||||
0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
||||
|
||||
|
||||
Serial Port Configuration on P1010RDB |
||||
===================================== |
||||
Configure the serial port of the attached computer with the following values: |
||||
-Data rate: 115200 bps |
||||
-Number of data bits: 8 |
||||
-Parity: None |
||||
-Number of Stop bits: 1 |
||||
-Flow Control: Hardware/None |
||||
|
||||
|
||||
Settings of DIP-switch |
||||
====================== |
||||
SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash |
||||
SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash |
||||
SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash |
||||
Note: 1 stands for 'on', 0 stands for 'off' |
||||
|
||||
|
||||
Setting of hwconfig |
||||
=================== |
||||
If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or |
||||
"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: |
||||
setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" |
||||
By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection |
||||
is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM |
||||
instead of to CAN/UART1. |
||||
|
||||
|
||||
Build and burn u-boot to NOR flash |
||||
================================== |
||||
1. Build u-boot.bin image |
||||
export ARCH=powerpc |
||||
export CROSS_COMPILE=/your_path/powerpc-linux-gnu- |
||||
make P1010RDB_NOR |
||||
|
||||
2. Burn u-boot.bin into NOR flash |
||||
=> tftp $loadaddr $uboot |
||||
=> protect off eff80000 +$filesize |
||||
=> erase eff80000 +$filesize |
||||
=> cp.b $loadaddr eff80000 $filesize |
||||
|
||||
3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. |
||||
|
||||
|
||||
Alternate NOR bank |
||||
================== |
||||
1. Burn u-boot.bin into alternate NOR bank |
||||
=> tftp $loadaddr $uboot |
||||
=> protect off eef80000 +$filesize |
||||
=> erase eef80000 +$filesize |
||||
=> cp.b $loadaddr eef80000 $filesize |
||||
|
||||
2. Switch to alternate NOR bank |
||||
=> mw.b ffb00009 1 |
||||
=> reset |
||||
or set SW1[8]= ON |
||||
|
||||
SW1[8]= OFF: Upper bank used for booting start |
||||
SW1[8]= ON: Lower bank used for booting start |
||||
CPLD NOR bank selection register address 0xFFB00009 Bit[0]: |
||||
0 - boot from upper 4 sectors |
||||
1 - boot from lower 4 sectors |
||||
|
||||
|
||||
Build and burn u-boot to NAND flash |
||||
=================================== |
||||
1. Build u-boot.bin image |
||||
export ARCH=powerpc |
||||
export CROSS_COMPILE=/your_path/powerpc-linux-gnu- |
||||
make P1010RDB_NAND |
||||
|
||||
2. Burn u-boot-nand.bin into NAND flash |
||||
=> tftp $loadaddr $uboot-nand |
||||
=> nand erase 0 $filesize |
||||
=> nand write $loadaddr 0 $filesize |
||||
|
||||
3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. |
||||
|
||||
|
||||
|
||||
Build and burn u-boot to SPI flash |
||||
================================== |
||||
1. Build u-boot-spi.bin image |
||||
make P1010RDB_SPIFLASH_config; make |
||||
Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb |
||||
Download u-boot.bin to linux and you can find some config files |
||||
under /usr/share such as config_xx.dat. Do below command: |
||||
boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ |
||||
u-boot-spi.bin |
||||
to generate u-boot-spi.bin. |
||||
|
||||
2. Burn u-boot-spi.bin into SPI flash |
||||
=> tftp $loadaddr $uboot-spi |
||||
=> sf erase 0 100000 |
||||
=> sf write $loadaddr 0 $filesize |
||||
|
||||
3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. |
||||
|
||||
|
||||
|
||||
CPLD POR setting registers |
||||
========================== |
||||
1. Set POR switch selection register (addr 0xFFB00011) to 0. |
||||
2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with |
||||
proper values. |
||||
If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 |
||||
switch command by I2C. |
||||
3. Send reset command. |
||||
After reset, the new POR setting will be implemented. |
||||
|
||||
Two examples are given in below: |
||||
Switch from NOR to NAND boot with default frequency: |
||||
=> i2c dev 0 |
||||
=> i2c mw 18 1 f9 |
||||
=> i2c mw 18 3 f0 |
||||
=> mw.b ffb00011 0 |
||||
=> mw.b ffb00017 1 |
||||
=> reset |
||||
Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): |
||||
=> i2c dev 0 |
||||
=> i2c mw 18 1 f1 |
||||
=> i2c mw 18 3 f0 |
||||
=> mw.b ffb00011 0 |
||||
=> mw.b ffb00014 2 |
||||
=> mw.b ffb00015 5 |
||||
=> mw.b ffb00016 3 |
||||
=> mw.b ffb00017 f |
||||
=> reset |
||||
|
||||
|
||||
|
||||
Boot Linux from network using TFTP on P1010RDB |
||||
============================================== |
||||
Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. |
||||
=> tftp 1000000 uImage |
||||
=> tftp 2000000 p1010rdb.dtb |
||||
=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb |
||||
=> bootm 1000000 3000000 2000000 |
||||
|
||||
|
||||
Please contact your local field applications engineer or sales representative |
||||
to obtain related documents, such as P1010-RDB User Guide for details. |
||||
|
||||
@ -0,0 +1,166 @@ |
||||
External Debug Support |
||||
---------------------- |
||||
|
||||
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some |
||||
restrictions on external debugging (JTAG). In particular, for the debugger to |
||||
be able to receive control after a single step or breakpoint: |
||||
- MSR[DE] must be set |
||||
- A valid opcode must be fetchable, through the MMU, from the debug |
||||
exception vector (IVPR + IVOR15). |
||||
|
||||
To maximize the time during which this requirement is met, U-Boot sets MSR[DE] |
||||
immediately on entry and keeps it set. It also uses a temporary TLB to keep a |
||||
mapping to a valid opcode at the debug exception vector, even if we normally |
||||
don't support exception vectors being used that early, and that's not the area |
||||
where U-Boot currently executes from. |
||||
|
||||
Note that there may still be some small windows where debugging will not work, |
||||
such as in between updating IVPR and IVOR15. |
||||
|
||||
Config Switches: |
||||
---------------- |
||||
|
||||
Please refer README section "MPC85xx External Debug Support" |
||||
|
||||
Major Config Switches during various boot Modes |
||||
---------------------------------------------- |
||||
|
||||
NOR boot |
||||
!defined(CONFIG_SYS_RAMBOOT) |
||||
NOR boot Secure |
||||
!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) |
||||
RAMBOOT(SD, SPI & NAND boot) |
||||
defined(CONFIG_SYS_RAMBOOT) |
||||
RAMBOOT Secure (SD, SPI & NAND) |
||||
defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) |
||||
NAND SPL BOOT |
||||
defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL) |
||||
|
||||
|
||||
TLB Entries during u-boot execution |
||||
----------------------------------- |
||||
|
||||
Note: Sequence number is in order of execution |
||||
|
||||
A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot |
||||
|
||||
1) TLB entry to overcome e500 v1/v2 debug restriction |
||||
Location : Label "_start_e500" |
||||
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB |
||||
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE |
||||
Properties : 256K, AS0, I, IPROT |
||||
|
||||
2) TLB entry for working in AS1 |
||||
Location : Label "create_init_ram_area" |
||||
TLB Entry : 15 |
||||
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE |
||||
Properties : 1M, AS1, I, G, IPROT |
||||
|
||||
3) TLB entry for the stack during AS1 |
||||
Location : Lable "create_init_ram_area" |
||||
TLB Entry : 14 |
||||
EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR |
||||
Properties : 16K, AS1, IPROT |
||||
|
||||
4) TLB entry for CCSRBAR during AS1 execution |
||||
Location : cpu_init_early_f |
||||
TLB Entry : 13 |
||||
EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR |
||||
Properties : 1M, AS1, I, G |
||||
|
||||
5) Invalidate unproctected TLB Entries |
||||
Location : cpu_init_early_f |
||||
Invalidated: 13 |
||||
|
||||
6) Create TLB entries as per boards/freescale/<board>/tlb.c |
||||
Location : cpu_init_early_f --> init_tlbs() |
||||
Properties : ..., AS0, ... |
||||
Please note It can overwrites previous TLB Entries. |
||||
|
||||
7) Disable TLB Entries of AS1 |
||||
Location : cpu_init_f --> disable_tlb() |
||||
Disable : 15, 14 |
||||
|
||||
8) Update Flash's TLB entry |
||||
Location : Board_init_r |
||||
TLB entry : Search from TLB entries |
||||
EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS |
||||
Properties : Board specific size, AS0, I, G, IPROT |
||||
|
||||
|
||||
B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot |
||||
|
||||
1) TLB entry to overcome e500 v1/v2 debug restriction |
||||
Location : Label "_start_e500" |
||||
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB |
||||
#if defined(CONFIG_SECURE_BOOT) |
||||
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW |
||||
Properties : 1M, AS1, I, G, IPROT |
||||
#else |
||||
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 |
||||
Properties : 4M, AS0, I, G, IPROT |
||||
#endif |
||||
|
||||
2) TLB entry for working in AS1 |
||||
Location : Label "create_init_ram_area" |
||||
TLB Entry : 15 |
||||
#if defined(CONFIG_SECURE_BOOT) |
||||
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW |
||||
Properties : 1M, AS1, I, G, IPROT |
||||
#else |
||||
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 |
||||
Properties : 4M, AS1, I, G, IPROT |
||||
#endif |
||||
|
||||
3) TLB entry for the stack during AS1 |
||||
Location : Lable "create_init_ram_area" |
||||
TLB Entry : 14 |
||||
EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR |
||||
Properties : 16K, AS1, IPROT |
||||
|
||||
4) TLB entry for CCSRBAR during AS1 execution |
||||
Location : cpu_init_early_f |
||||
TLB Entry : 13 |
||||
EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR |
||||
Properties : 1M, AS1, I, G |
||||
|
||||
5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
||||
Location : cpu_init_early_f |
||||
TLB Entry : 9 |
||||
EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR |
||||
Properties : 1M, AS1, I |
||||
|
||||
6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr |
||||
Location : cpu_init_early_f --> setup_ifc |
||||
TLB Entry : Get Flash TLB |
||||
EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys |
||||
Properties : 4M, AS1, I, G, IPROT |
||||
|
||||
7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction |
||||
Location : cpu_init_early_f --> setup_ifc |
||||
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB |
||||
EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys |
||||
Properties : 4M, AS0, I, G, IPROT |
||||
|
||||
8) Invalidate unproctected TLB Entries |
||||
Location : cpu_init_early_f |
||||
Invalidated: 13, 9 |
||||
|
||||
9) Create TLB entries as per boards/freescale/<board>/tlb.c |
||||
Location : cpu_init_early_f --> init_tlbs() |
||||
Properties : ..., AS0, ... |
||||
Note: It can overwrites previous TLB Entries |
||||
|
||||
10) Disable TLB Entries of AS1 |
||||
Location : cpu_init_f --> disable_tlb() |
||||
Disable : 15, 14 |
||||
|
||||
11) Create DDR's TLB entriy |
||||
Location : Board_init_f -> init_func_ram -> initdram |
||||
TLB entry : Search free TLB entry |
||||
|
||||
12) Update Flash's TLB entry |
||||
Location : Board_init_r |
||||
TLB entry : Search from TLB entries |
||||
EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS |
||||
Properties : Board specific size, AS0, I, G, IPROT |
||||
@ -0,0 +1,428 @@ |
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* BSC9131 RDB board configuration file |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#ifdef CONFIG_BSC9131RDB |
||||
#define CONFIG_BSC9131 |
||||
#define CONFIG_NAND_FSL_IFC |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SPIFLASH |
||||
#define CONFIG_RAMBOOT_SPIFLASH |
||||
#define CONFIG_SYS_RAMBOOT |
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||
#define CONFIG_SYS_TEXT_BASE 0x11000000 |
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_BASE |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
||||
#endif |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE /* BOOKE */ |
||||
#define CONFIG_E500 /* BOOKE e500 family */ |
||||
#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ |
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */ |
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */ |
||||
#define CONFIG_TSEC_ENET |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ |
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ |
||||
|
||||
#define CONFIG_HWCONFIG |
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||
#define CONFIG_BTB /* enable branch predition */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x01ffffff |
||||
|
||||
/* DDR Setup */ |
||||
#define CONFIG_FSL_DDR3 |
||||
#undef CONFIG_SYS_DDR_RAW_TIMING |
||||
#undef CONFIG_DDR_SPD |
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 |
||||
#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ |
||||
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned long get_sdram_size(void); |
||||
#endif |
||||
#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1 |
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1 |
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f |
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 |
||||
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 |
||||
|
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
||||
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 |
||||
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 |
||||
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 |
||||
|
||||
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
||||
#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 |
||||
#define CONFIG_SYS_DDR_RCW_1 0x00000000 |
||||
#define CONFIG_SYS_DDR_RCW_2 0x00000000 |
||||
#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ |
||||
#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 |
||||
#define CONFIG_SYS_DDR_TIMING_4 0x00000001 |
||||
#define CONFIG_SYS_DDR_TIMING_5 0x02401400 |
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 |
||||
#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 |
||||
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 |
||||
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf |
||||
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 |
||||
#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 |
||||
#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 |
||||
#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 |
||||
#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
/* relocated CCSRBAR */ |
||||
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT |
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT |
||||
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ |
||||
/* CONFIG_SYS_IMMR */ |
||||
|
||||
/*
|
||||
* Memory map |
||||
* |
||||
* 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable |
||||
* 0x8800_0000 0x8810_0000 IFC internal SRAM 1M |
||||
* 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M |
||||
* 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K |
||||
* 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K |
||||
* 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K |
||||
* 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M |
||||
* 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M |
||||
* |
||||
*/ |
||||
|
||||
/*
|
||||
* IFC Definitions |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/* NAND Flash on IFC */ |
||||
#define CONFIG_SYS_NAND_BASE 0xff800000 |
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
||||
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V) |
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
||||
|
||||
/* NAND Flash Timing Params */ |
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ |
||||
| FTIM0_NAND_TWP(0x06) \
|
||||
| FTIM0_NAND_TWCHT(0x03) \
|
||||
| FTIM0_NAND_TWH(0x04)) |
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ |
||||
| FTIM1_NAND_TWBE(0x23) \
|
||||
| FTIM1_NAND_TRR(0x08) \
|
||||
| FTIM1_NAND_TRP(0x05)) |
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ |
||||
| FTIM2_NAND_TREH(0x04) \
|
||||
| FTIM2_NAND_TWHRE(0x3f)) |
||||
#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) |
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11 |
||||
|
||||
/* Set up IFC registers for boot location NAND */ |
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ |
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ |
||||
#define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ |
||||
- GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#ifdef CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/*
|
||||
* Pass open firmware flat tree |
||||
*/ |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
||||
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ |
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000 |
||||
|
||||
/* I2C EEPROM */ |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
||||
|
||||
#define CONFIG_CMD_I2C |
||||
|
||||
|
||||
#define CONFIG_FSL_ESPI |
||||
/* eSPI - Enhanced SPI */ |
||||
#ifdef CONFIG_FSL_ESPI |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000 |
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
||||
#endif |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
|
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
||||
#define CONFIG_TSEC1 1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC1" |
||||
#define CONFIG_TSEC2 1 |
||||
#define CONFIG_TSEC2_NAME "eTSEC2" |
||||
|
||||
#define TSEC1_PHY_ADDR 0 |
||||
#define TSEC2_PHY_ADDR 3 |
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
||||
|
||||
#define TSEC1_PHYIDX 0 |
||||
|
||||
#define TSEC2_PHYIDX 0 |
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1" |
||||
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
||||
|
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#if defined(CONFIG_SYS_RAMBOOT) |
||||
#if defined(CONFIG_RAMBOOT_SPIFLASH) |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SPI_BUS 0 |
||||
#define CONFIG_ENV_SPI_CS 0 |
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000 |
||||
#define CONFIG_ENV_SPI_MODE 0 |
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#endif |
||||
#else |
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
||||
#define CONFIG_ENV_SIZE 0x400 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ERRATA |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_SETEXPR |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 64 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ |
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
#define CONFIG_USB_EHCI |
||||
|
||||
#ifdef CONFIG_USB_EHCI |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#define CONFIG_USB_EHCI_FSL |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_HAS_FSL_DR_USB |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_HAS_ETH0 |
||||
#endif |
||||
|
||||
#define CONFIG_HOSTNAME BSC9131rdb |
||||
#define CONFIG_ROOTPATH "/opt/nfsroot" |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"uboot=" CONFIG_UBOOTPATH "\0" \
|
||||
"loadaddr=1000000\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=bsc9131rdb.dtb\0" \
|
||||
"bdev=sda1\0" \
|
||||
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
|
||||
"othbootargs=ramdisk_size=600000 \0" \
|
||||
"usbext2boot=setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"usb start;" \
|
||||
"ext2load usb 0:4 $loadaddr $bootfile;" \
|
||||
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
|
||||
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue