This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, installed on the congatec Qseven 2.0 evaluation carrier board (conga-QEVAL). Its port is very similar to the MinnowboardMAX port and also uses the Intel FSP as described in doc/README.x86. Currently supported are the following interfaces / devices: - UART (via Winbond legacy SuperIO chip on carrier board) - Ethernet (PCIe Intel I210 / E1000) - SPI including SPI NOR as boot-device - USB 2.0 - SATA via U-Boot SCSI IF - eMMC - Video (HDMI output @ 800x600) - PCIe Not supported yet is: - I2C - USB 3.0 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>master
Stefan Roese
9 years ago
committed by
Bin Meng
parent
374e78efb0
commit
82ceba2ca2
@ -0,0 +1,278 @@ |
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/* |
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
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* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/dts-v1/; |
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|
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#include <dt-bindings/gpio/x86-gpio.h> |
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#include <dt-bindings/interrupt-router/intel-irq.h> |
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|
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/include/ "skeleton.dtsi" |
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/include/ "serial.dtsi" |
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/include/ "rtc.dtsi" |
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/include/ "tsc_timer.dtsi" |
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|
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/ { |
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model = "congatec-QEVAL20-QA3-E3845"; |
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compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail"; |
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|
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aliases { |
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serial0 = &serial; |
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spi0 = &spi; |
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}; |
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|
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config { |
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silent_console = <0>; |
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}; |
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|
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pch_pinctrl { |
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compatible = "intel,x86-pinctrl"; |
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}; |
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|
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chosen { |
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stdout-path = "/serial"; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "intel,baytrail-cpu"; |
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reg = <0>; |
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intel,apic-id = <0>; |
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}; |
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|
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "intel,baytrail-cpu"; |
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reg = <1>; |
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intel,apic-id = <2>; |
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}; |
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|
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cpu@2 { |
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device_type = "cpu"; |
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compatible = "intel,baytrail-cpu"; |
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reg = <2>; |
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intel,apic-id = <4>; |
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}; |
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|
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cpu@3 { |
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device_type = "cpu"; |
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compatible = "intel,baytrail-cpu"; |
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reg = <3>; |
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intel,apic-id = <6>; |
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}; |
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}; |
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|
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pci { |
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compatible = "intel,pci-baytrail", "pci-x86"; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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u-boot,dm-pre-reloc; |
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 |
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 |
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0x01000000 0x0 0x2000 0x2000 0 0xe000>; |
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|
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pch@1f,0 { |
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reg = <0x0000f800 0 0 0 0>; |
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compatible = "pci8086,0f1c", "intel,pch9"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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|
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irq-router { |
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compatible = "intel,irq-router"; |
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intel,pirq-config = "ibase"; |
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intel,ibase-offset = <0x50>; |
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intel,pirq-link = <8 8>; |
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intel,pirq-mask = <0xdee0>; |
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intel,pirq-routing = < |
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/* BayTrail PCI devices */ |
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PCI_BDF(0, 2, 0) INTA PIRQA |
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PCI_BDF(0, 3, 0) INTA PIRQA |
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PCI_BDF(0, 16, 0) INTA PIRQA |
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PCI_BDF(0, 17, 0) INTA PIRQA |
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PCI_BDF(0, 18, 0) INTA PIRQA |
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PCI_BDF(0, 19, 0) INTA PIRQA |
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PCI_BDF(0, 20, 0) INTA PIRQA |
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PCI_BDF(0, 21, 0) INTA PIRQA |
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PCI_BDF(0, 22, 0) INTA PIRQA |
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PCI_BDF(0, 23, 0) INTA PIRQA |
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PCI_BDF(0, 24, 0) INTA PIRQA |
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PCI_BDF(0, 24, 1) INTC PIRQC |
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PCI_BDF(0, 24, 2) INTD PIRQD |
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PCI_BDF(0, 24, 3) INTB PIRQB |
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PCI_BDF(0, 24, 4) INTA PIRQA |
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PCI_BDF(0, 24, 5) INTC PIRQC |
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PCI_BDF(0, 24, 6) INTD PIRQD |
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PCI_BDF(0, 24, 7) INTB PIRQB |
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PCI_BDF(0, 26, 0) INTA PIRQA |
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PCI_BDF(0, 27, 0) INTA PIRQA |
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PCI_BDF(0, 28, 0) INTA PIRQA |
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PCI_BDF(0, 28, 1) INTB PIRQB |
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PCI_BDF(0, 28, 2) INTC PIRQC |
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PCI_BDF(0, 28, 3) INTD PIRQD |
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PCI_BDF(0, 29, 0) INTA PIRQA |
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PCI_BDF(0, 30, 0) INTA PIRQA |
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PCI_BDF(0, 30, 1) INTD PIRQD |
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PCI_BDF(0, 30, 2) INTB PIRQB |
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PCI_BDF(0, 30, 3) INTC PIRQC |
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PCI_BDF(0, 30, 4) INTD PIRQD |
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PCI_BDF(0, 30, 5) INTB PIRQB |
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PCI_BDF(0, 31, 3) INTB PIRQB |
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|
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/* |
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* PCIe root ports downstream |
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* interrupts |
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*/ |
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PCI_BDF(1, 0, 0) INTA PIRQA |
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PCI_BDF(1, 0, 0) INTB PIRQB |
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PCI_BDF(1, 0, 0) INTC PIRQC |
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PCI_BDF(1, 0, 0) INTD PIRQD |
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PCI_BDF(2, 0, 0) INTA PIRQB |
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PCI_BDF(2, 0, 0) INTB PIRQC |
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PCI_BDF(2, 0, 0) INTC PIRQD |
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PCI_BDF(2, 0, 0) INTD PIRQA |
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PCI_BDF(3, 0, 0) INTA PIRQC |
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PCI_BDF(3, 0, 0) INTB PIRQD |
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PCI_BDF(3, 0, 0) INTC PIRQA |
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PCI_BDF(3, 0, 0) INTD PIRQB |
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PCI_BDF(4, 0, 0) INTA PIRQD |
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PCI_BDF(4, 0, 0) INTB PIRQA |
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PCI_BDF(4, 0, 0) INTC PIRQB |
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PCI_BDF(4, 0, 0) INTD PIRQC |
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>; |
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}; |
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spi: spi { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "intel,ich9-spi"; |
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spi-flash@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0>; |
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compatible = "stmicro,n25q064a", |
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"spi-flash"; |
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memory-map = <0xff800000 0x00800000>; |
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rw-mrc-cache { |
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label = "rw-mrc-cache"; |
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reg = <0x006f0000 0x00010000>; |
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}; |
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}; |
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}; |
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gpioa { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0 0x20>; |
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bank-name = "A"; |
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}; |
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gpiob { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0x20 0x20>; |
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bank-name = "B"; |
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}; |
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gpioc { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0x40 0x20>; |
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bank-name = "C"; |
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}; |
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gpiod { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0x60 0x20>; |
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bank-name = "D"; |
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}; |
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gpioe { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0x80 0x20>; |
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bank-name = "E"; |
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}; |
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gpiof { |
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compatible = "intel,ich6-gpio"; |
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u-boot,dm-pre-reloc; |
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reg = <0xA0 0x20>; |
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bank-name = "F"; |
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}; |
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}; |
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}; |
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fsp { |
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compatible = "intel,baytrail-fsp"; |
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fsp,mrc-init-tseg-size = <0>; |
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fsp,mrc-init-mmio-size = <0x800>; |
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fsp,mrc-init-spd-addr1 = <0xa0>; |
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fsp,mrc-init-spd-addr2 = <0xa2>; |
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fsp,emmc-boot-mode = <2>; |
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fsp,enable-sdio; |
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fsp,enable-sdcard; |
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fsp,enable-hsuart1; |
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fsp,enable-spi; |
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fsp,enable-sata; |
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fsp,sata-mode = <1>; |
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fsp,enable-lpe; |
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fsp,lpss-sio-enable-pci-mode; |
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fsp,enable-dma0; |
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fsp,enable-dma1; |
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fsp,enable-i2c0; |
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fsp,enable-i2c1; |
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fsp,enable-i2c2; |
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fsp,enable-i2c3; |
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fsp,enable-i2c4; |
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fsp,enable-i2c5; |
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fsp,enable-i2c6; |
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fsp,enable-pwm0; |
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fsp,enable-pwm1; |
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fsp,igd-dvmt50-pre-alloc = <2>; |
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fsp,aperture-size = <2>; |
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fsp,gtt-size = <2>; |
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fsp,scc-enable-pci-mode; |
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fsp,os-selection = <4>; |
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fsp,emmc45-ddr50-enabled; |
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fsp,emmc45-retune-timer-value = <8>; |
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fsp,enable-igd; |
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fsp,enable-memory-down; |
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fsp,memory-down-params { |
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compatible = "intel,baytrail-fsp-mdp"; |
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fsp,dram-speed = <2>; /* 2=1333MHz */ |
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fsp,dram-type = <1>; /* 1=DDR3L */ |
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fsp,dimm-0-enable; |
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fsp,dimm-1-enable; |
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fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ |
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fsp,dimm-density = <2>; /* 2=4Gbit */ |
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fsp,dimm-bus-width = <3>; /* 3=64bits */ |
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fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ |
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/* These following values might need a re-visit */ |
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fsp,dimm-tcl = <8>; |
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fsp,dimm-trpt-rcd = <8>; |
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fsp,dimm-twr = <8>; |
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fsp,dimm-twtr = <4>; |
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fsp,dimm-trrd = <6>; |
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fsp,dimm-trtp = <4>; |
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fsp,dimm-tfaw = <22>; |
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}; |
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}; |
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microcode { |
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update@0 { |
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#include "microcode/m0130673322.dtsi" |
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}; |
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update@1 { |
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#include "microcode/m0130679901.dtsi" |
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}; |
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}; |
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}; |
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@ -0,0 +1,29 @@ |
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# |
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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if VENDOR_CONGATEC |
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choice |
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prompt "Mainboard model" |
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optional |
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config TARGET_CONGA_QEVAL20_QA3_E3845 |
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bool "congatec QEVAL 2.0 & conga-QA3/E3845" |
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help |
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This is the congatec Qseven 2.0 evaluation carrier board |
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(conga-QEVAL) equipped with the conga-QA3/E3845-4G SoM. |
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It contains an Atom E3845 with Ethernet, micro-SD, USB 2, |
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USB 3, SATA, serial console and HDMI 1.3 video out. |
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It requires some binary blobs - see README.x86 for details. |
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Note that PCIE_ECAM_BASE is set up by the FSP so the value used |
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by U-Boot matches that value. |
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endchoice |
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source "board/congatec/conga-qeval20-qa3-e3845/Kconfig" |
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endif |
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@ -0,0 +1,28 @@ |
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if TARGET_CONGA_QEVAL20_QA3_E3845 |
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config SYS_BOARD |
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default "conga-qeval20-qa3-e3845" |
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config SYS_VENDOR |
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default "congatec" |
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config SYS_SOC |
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default "baytrail" |
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config SYS_CONFIG_NAME |
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default "conga-qeval20-qa3-e3845" |
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config SYS_TEXT_BASE |
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default 0xfff00000 if !EFI_STUB |
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default 0x01110000 if EFI_STUB |
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config BOARD_SPECIFIC_OPTIONS # dummy |
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def_bool y |
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select X86_RESET_VECTOR if !EFI_STUB |
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select INTEL_BAYTRAIL |
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select BOARD_ROMSIZE_KB_8192 |
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config PCIE_ECAM_BASE |
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default 0xe0000000 |
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endif |
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@ -0,0 +1,7 @@ |
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congatec EVAL20-QA3-E3845 |
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M: Stefan Roese <sr@denx.de> |
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S: Maintained |
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F: board/congatec/conga-qeval20-qa3-e3845 |
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F: include/configs/conga-qeval20-qa3-e3845.h |
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F: configs/conga-qeval20-qa3-e3845_defconfig |
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F: arch/x86/dts/conga-qeval20-qa3-e3845.dts |
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@ -0,0 +1,7 @@ |
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#
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# Copyright (C) 2015, Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += conga-qeval20-qa3.o start.o
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@ -0,0 +1,31 @@ |
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <winbond_w83627.h> |
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#include <asm/gpio.h> |
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#include <asm/ibmpc.h> |
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#include <asm/pnp_def.h> |
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int board_early_init_f(void) |
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{ |
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/*
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* The FSP enables the BayTrail internal legacy UART (again). |
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* Disable it again, so that the Winbond one can be used. |
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*/ |
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setup_internal_uart(0); |
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/* Enable the legacy UART in the Winbond W83627 Super IO chip */ |
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winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1), |
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UART0_BASE, UART0_IRQ); |
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return 0; |
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} |
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int arch_early_init_r(void) |
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{ |
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return 0; |
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} |
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@ -0,0 +1,9 @@ |
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/* |
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* Copyright (C) 2015, Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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.globl early_board_init
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early_board_init: |
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jmp early_board_init_ret |
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@ -0,0 +1,47 @@ |
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CONFIG_X86=y |
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CONFIG_VENDOR_CONGATEC=y |
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CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y |
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CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845" |
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CONFIG_HAVE_INTEL_ME=y |
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CONFIG_ENABLE_MRC_CACHE=y |
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CONFIG_SMP=y |
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CONFIG_HAVE_VGA_BIOS=y |
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CONFIG_GENERATE_PIRQ_TABLE=y |
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CONFIG_GENERATE_MP_TABLE=y |
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CONFIG_FIT=y |
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CONFIG_FIT_SIGNATURE=y |
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CONFIG_BOOTSTAGE=y |
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CONFIG_BOOTSTAGE_REPORT=y |
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CONFIG_CMD_CPU=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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CONFIG_CMD_GPIO=y |
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# CONFIG_CMD_SETEXPR is not set |
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# CONFIG_CMD_NFS is not set |
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CONFIG_CMD_BOOTSTAGE=y |
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CONFIG_OF_CONTROL=y |
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CONFIG_REGMAP=y |
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CONFIG_SYSCON=y |
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CONFIG_CPU=y |
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CONFIG_WINBOND_W83627=y |
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CONFIG_SPI_FLASH=y |
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CONFIG_SPI_FLASH_GIGADEVICE=y |
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CONFIG_SPI_FLASH_MACRONIX=y |
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CONFIG_SPI_FLASH_STMICRO=y |
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CONFIG_SPI_FLASH_WINBOND=y |
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CONFIG_DM_ETH=y |
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CONFIG_E1000=y |
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CONFIG_DM_PCI=y |
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CONFIG_DM_RTC=y |
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CONFIG_DEBUG_UART=y |
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CONFIG_DEBUG_UART_BASE=0x3f8 |
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CONFIG_DEBUG_UART_CLOCK=1843200 |
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CONFIG_SYS_NS16550=y |
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CONFIG_ICH_SPI=y |
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CONFIG_TIMER=y |
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CONFIG_USB=y |
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CONFIG_DM_USB=y |
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CONFIG_VIDEO_VESA=y |
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y |
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CONFIG_FRAMEBUFFER_VESA_MODE_114=y |
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CONFIG_USE_PRIVATE_LIBGCC=y |
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@ -0,0 +1,65 @@ |
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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|
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <configs/x86-common.h> |
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#define CONFIG_SYS_MONITOR_LEN (1 << 20) |
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#define CONFIG_BOARD_EARLY_INIT_F |
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#define CONFIG_ARCH_EARLY_INIT_R |
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#define CONFIG_ARCH_MISC_INIT |
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|
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#define CONFIG_PCI_PNP |
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|
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ |
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"stdout=serial\0" \
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"stderr=serial\0" |
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|
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#define CONFIG_SCSI_DEV_LIST \ |
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} |
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|
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#define CONFIG_MMC |
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#define CONFIG_SDHCI |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_MMC_SDMA |
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#define CONFIG_CMD_MMC |
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#undef CONFIG_USB_MAX_CONTROLLER_COUNT |
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
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#define VIDEO_IO_OFFSET 0 |
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#define CONFIG_X86EMU_RAW_IO |
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#define CONFIG_CMD_BMP |
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#define CONFIG_ENV_SECT_SIZE 0x1000 |
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#define CONFIG_ENV_OFFSET 0x007fe000 |
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|
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#undef CONFIG_BOOTARGS |
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#undef CONFIG_BOOTCOMMAND |
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#define CONFIG_BOOTARGS \ |
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"root=/dev/sda1 ro quiet" |
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#define CONFIG_BOOTCOMMAND \ |
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"load scsi 0:1 03000000 /boot/vmlinuz-4.2.0-26-generic;" \
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"load scsi 0:1 04000000 /boot/initrd.img-4.2.0-26-generic;" \
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"run boot" |
||||
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"boot=zboot 03000000 0 04000000 ${filesize}\0" \
|
||||
"upd_uboot=tftp 100000 conga/u-boot.rom;" \
|
||||
"sf probe;sf update 100000 0 7fe000\0" |
||||
|
||||
#define CONFIG_PREBOOT |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue