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@ -28,8 +28,7 @@ |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/mx35_pins.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/iomux-mx35.h> |
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#include <i2c.h> |
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#include <power/pmic.h> |
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#include <fsl_pmic.h> |
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@ -74,25 +73,29 @@ static void board_setup_sdram(void) |
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static void setup_iomux_fec(void) |
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{ |
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static const iomux_v3_cfg_t fec_pads[] = { |
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MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, |
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MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, |
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MX35_PAD_FEC_RX_DV__FEC_RX_DV, |
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MX35_PAD_FEC_COL__FEC_COL, |
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0, |
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0, |
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MX35_PAD_FEC_TX_EN__FEC_TX_EN, |
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MX35_PAD_FEC_MDC__FEC_MDC, |
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MX35_PAD_FEC_MDIO__FEC_MDIO, |
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MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, |
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MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, |
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MX35_PAD_FEC_CRS__FEC_CRS, |
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MX35_PAD_FEC_RDATA1__FEC_RDATA_1, |
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MX35_PAD_FEC_TDATA1__FEC_TDATA_1, |
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MX35_PAD_FEC_RDATA2__FEC_RDATA_2, |
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MX35_PAD_FEC_TDATA2__FEC_TDATA_2, |
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MX35_PAD_FEC_RDATA3__FEC_RDATA_3, |
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MX35_PAD_FEC_TDATA3__FEC_TDATA_3, |
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}; |
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/* setup pins for FEC */ |
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mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); |
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
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} |
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int woodburn_init(void) |
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@ -130,9 +133,9 @@ int woodburn_init(void) |
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setup_iomux_fec(); |
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/* setup GPIO1_4 FEC_ENABLE signal */ |
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mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5); |
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imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4); |
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gpio_direction_output(4, 1); |
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mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5); |
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imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9); |
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gpio_direction_output(9, 1); |
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return 0; |
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@ -228,22 +231,24 @@ struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; |
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int board_mmc_init(bd_t *bis) |
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{ |
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static const iomux_v3_cfg_t sdhc1_pads[] = { |
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MX35_PAD_SD1_CMD__ESDHC1_CMD, |
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MX35_PAD_SD1_CLK__ESDHC1_CLK, |
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MX35_PAD_SD1_DATA0__ESDHC1_DAT0, |
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MX35_PAD_SD1_DATA1__ESDHC1_DAT1, |
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MX35_PAD_SD1_DATA2__ESDHC1_DAT2, |
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MX35_PAD_SD1_DATA3__ESDHC1_DAT3, |
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}; |
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/* configure pins for SDHC1 only */ |
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mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); |
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mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); |
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imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); |
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/* MMC Card Detect on GPIO1_7 */ |
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mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5); |
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mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1); |
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imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7); |
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gpio_direction_input(GPIO_MMC_CD); |
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/* MMC Write Protection on GPIO1_8 */ |
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mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5); |
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mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1); |
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imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8); |
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gpio_direction_input(GPIO_MMC_WP); |
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esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); |
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