usb: dra7xx: Add support for dra7xx xhci USB host

Add the support for the dra7xx xhci usb host.
dra7xx does not contain an EHCI controller so the headers
can be removed from the board file.

The xHCI host on dra7xx is connected to a usb2 phy so need to
add support to enable those clocks.

Signed-off-by: Dan Murphy <dmurphy@ti.com>

arch/arm/cpu/armv7/omap5/prcm-regs.c

@@ -793,6 +793,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_clkmode_dpll_dsp			= 0x4a005234,
 	.cm_shadow_freq_config1			= 0x4a005260,
 	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
+	.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
 
 	/* cm1.mpu */
 	.cm_mpu_mpu_clkctrl			= 0x4a005320,

arch/arm/include/asm/arch-omap5/clock.h

@@ -202,6 +202,10 @@
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
 
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET	(1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR	0x12
 #define SMPS_REG_ADDR_12_MPU	0x23

arch/arm/include/asm/omap_common.h

@@ -144,6 +144,7 @@ struct prcm_regs {
 	u32 cm_ssc_deltamstep_dpll_unipro;
 	u32 cm_ssc_modfreqdiv_dpll_unipro;
 	u32 cm_coreaon_usb_phy_core_clkctrl;
+	u32 cm_coreaon_usb_phy2_core_clkctrl;
 
 	/* cm2.core */
 	u32 cm_coreaon_bandgap_clkctrl;

board/ti/dra7xx/evm.c

@@ -17,12 +17,6 @@
 
 #include "mux_data.h"
 
-#ifdef CONFIG_USB_EHCI
-#include <usb.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#endif
-
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include <cpsw.h>
 #endif

board/ti/dra7xx/mux_data.h

@@ -61,5 +61,6 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
 	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
 	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
+	{USB2_DRVVBUS, (M0 | IEN | FSC) },
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */

drivers/usb/host/xhci-omap.c

@@ -98,9 +98,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
 {
 	int ret = 0;
 
-	omap_enable_phy_clocks(omap);
-
-	omap_usb3_phy_init(omap->usb3_phy);
+	omap_enable_phy(omap);
 
 	ret = dwc3_core_init(omap->dwc3_reg);
 	if (ret) {
@@ -116,7 +114,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
 
 static void omap_xhci_core_exit(struct omap_xhci *omap)
 {
-	usb3_phy_power(0);
+	usb_phy_power(0);
 }
 
 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)

drivers/usb/phy/omap_usb_phy.c

@@ -22,6 +22,7 @@
 
 #include "../host/xhci.h"
 
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
 struct usb_dpll_params {
 	u16	m;
 	u8	n;
@@ -99,7 +100,7 @@ static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
 	writel(val, (*ctrl)->control_phy_power_usb);
 }
 
-void usb3_phy_power(int on)
+void usb_phy_power(int on)
 {
 	u32 val;
 
@@ -128,7 +129,7 @@ void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
 	usb3_phy_power(1);
 }
 
-void omap_enable_phy_clocks(struct omap_xhci *omap)
+static void omap_enable_usb3_phy(struct omap_xhci *omap)
 {
 	u32	val;
 
@@ -176,6 +177,35 @@ void omap_enable_phy_clocks(struct omap_xhci *omap)
 	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
 
 };
+#endif /* CONFIG_OMAP_USB3PHY1_HOST */
+
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+static void omap_enable_usb2_phy2(struct omap_xhci *omap)
+{
+	u32 reg, val;
+
+	val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
+	writel(val, (*ctrl)->control_srcomp_north_side);
+
+	setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+			USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
+					(USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
+					 OTG_SS_CLKCTRL_MODULEMODE_HW));
+
+	/* This is an undocumented Reserved register */
+	reg = 0x4a0086c0;
+	val = readl(reg);
+	val |= 0x100;
+	setbits_le32(reg, val);
+}
+
+void usb_phy_power(int on)
+{
+	return;
+}
+#endif /* CONFIG_OMAP_USB2PHY2_HOST */
 
 void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
 {
@@ -195,3 +225,14 @@ void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
 
 }
 
+void omap_enable_phy(struct omap_xhci *omap)
+{
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+	omap_enable_usb2_phy2(omap);
+#endif
+
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
+	omap_enable_usb3_phy(omap);
+	omap_usb3_phy_init(omap->usb3_phy);
+#endif
+}

include/configs/dra7xx_evm.h

@@ -67,4 +67,15 @@
 #define CONFIG_SPL_SPI_CS              0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
 
+/* USB xHCI HOST */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB2PHY2_HOST
+
 #endif /* __CONFIG_DRA7XX_EVM_H */

include/linux/usb/xhci-omap.h

@@ -10,9 +10,16 @@
 #ifndef _ASM_ARCH_XHCI_OMAP_H_
 #define _ASM_ARCH_XHCI_OMAP_H_
 
+#ifdef CONFIG_DRA7XX
+#define OMAP_XHCI_BASE 0x488d0000
+#define OMAP_OCP1_SCP_BASE 0x4A081000
+#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#else
+/* Default to the OMAP5 XHCI defines */
 #define OMAP_XHCI_BASE 0x4a030000
 #define OMAP_OCP1_SCP_BASE 0x4a084c00
 #define OMAP_OTG_WRAPPER_BASE 0x4A020000
+#endif
 
 /* Phy register MACRO definitions */
 #define	PLL_REGM_MASK		0x001FFE00
@@ -122,9 +129,8 @@ struct omap_xhci {
 };
 
 /* USB PHY functions */
-void omap_enable_phy_clocks(struct omap_xhci *omap);
-void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs);
+void omap_enable_phy(struct omap_xhci *omap);
 void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
-void usb3_phy_power(int on);
+void usb_phy_power(int on);
 
 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */