- Add NAND boot target - defines constants - Add spl_minimal.c to initialise DDR - update TLB, LAW entries as per NAND boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>master
Prabhakar Kushwaha
11 years ago
committed by
Andy Fleming
parent
f159326926
commit
83e0c2bbe3
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <ns16550.h> |
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#include <asm/io.h> |
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#include <nand.h> |
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#include <linux/compiler.h> |
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#include <asm/fsl_law.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include <asm/global_data.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static void sdram_init(void) |
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{ |
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ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; |
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#if CONFIG_DDR_CLK_FREQ == 100000000 |
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); |
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); |
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__raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); |
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__raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); |
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); |
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__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); |
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__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); |
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__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); |
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); |
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5); |
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__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); |
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#elif CONFIG_DDR_CLK_FREQ == 133000000 |
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); |
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); |
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__raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); |
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__raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2); |
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2); |
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__raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode); |
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__raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2); |
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__raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval); |
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl); |
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4); |
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__raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5); |
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__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); |
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#else |
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puts("Not a valid DDR Freq Found! Please Reset\n"); |
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#endif |
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asm volatile("sync;isync"); |
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udelay(500); |
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/* Let the controller go */ |
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out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); |
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set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); |
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} |
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void board_init_f(ulong bootflag) |
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{ |
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u32 plat_ratio; |
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
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/* initialize selected port with appropriate baud rate */ |
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; |
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plat_ratio >>= 1; |
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; |
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
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gd->bus_clk / 16 / CONFIG_BAUDRATE); |
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puts("\nNAND boot... "); |
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/* Initialize the DDR3 */ |
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sdram_init(); |
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/* copy code to RAM and jump to it - this should not return */ |
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read. |
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*/ |
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relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); |
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} |
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void board_init_r(gd_t *gd, ulong dest_addr) |
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{ |
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nand_boot(); |
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} |
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void putc(char c) |
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{ |
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if (c == '\n') |
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); |
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); |
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} |
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void puts(const char *str) |
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{ |
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while (*str) |
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putc(*str++); |
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} |
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