DaVinci DM6467: Added ET1011C (LSI) PHY support

Added arch/arm/cpu/arm926ejs/davinci/et1011c.c for handling
ET1011C gigabit phy. which overrides get_link_speed function
from default implementation. This enables output of 125 MHz
reference clock on SYS_CLK pin.

Signed-off-by: Prakash PM <prakash.pm@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

arch/arm/cpu/arm926ejs/davinci/Makefile

@@ -32,7 +32,7 @@ COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
 COBJS-$(CONFIG_SOC_DM365)	+= dm365.o
 COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
 COBJS-$(CONFIG_SOC_DM646X)	+= dm646x.o
-COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o
+COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o
 
 SOBJS	= reset.o
 

arch/arm/cpu/arm926ejs/davinci/et1011c.c

@@ -0,0 +1,55 @@
+/*
+ * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <miiphy.h>
+#include <asm/arch/emac_defs.h>
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_CMD_NET
+
+/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
+
+#define MII_PHY_CONFIG_REG		22
+
+/* PHY Config bits */
+#define PHY_SYS_CLK_EN			(1 << 4)
+
+int et1011c_get_link_speed(int phy_addr)
+{
+	u_int16_t	data;
+
+	if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
+		davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
+				MII_PHY_CONFIG_REG, &data);
+		/* Enable 125MHz clock sourced from PHY */
+		davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
+			MII_PHY_CONFIG_REG,
+			data | PHY_SYS_CLK_EN);
+		return (1);
+	}
+	return (0);
+}
+
+#endif	/* CONFIG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */

arch/arm/include/asm/arch-davinci/emac_defs.h

@@ -389,4 +389,7 @@ int dp83848_get_link_speed(int phy_addr);
 int dp83848_init_phy(int phy_addr);
 int dp83848_auto_negotiate(int phy_addr);
 
+#define PHY_ET1011C	(0x282f013)
+int et1011c_get_link_speed(int phy_addr);
+
 #endif  /* _DM644X_EMAC_H_ */

drivers/net/davinci_emac.c

@@ -725,6 +725,13 @@ int davinci_emac_initialize(void)
 			phy.get_link_speed = dp83848_get_link_speed;
 			phy.auto_negotiate = dp83848_auto_negotiate;
 			break;
+		case PHY_ET1011C:
+			sprintf(phy.name, "ET1011C @ 0x%02x", active_phy_addr);
+			phy.init = gen_init_phy;
+			phy.is_phy_connected = gen_is_phy_connected;
+			phy.get_link_speed = et1011c_get_link_speed;
+			phy.auto_negotiate = gen_auto_negotiate;
+			break;
 		default:
 			sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr);
 			phy.init = gen_init_phy;