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Changed CONFIG_440_xx to CONFIG_440xx for a consistent design (405 and linux)

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Patch by Stefan Roese, 08 Aug 2005
master
Stefan Roese 20 years ago
parent 700a0c648d
commit 846b0dd2dc
28 changed files with 151 additions and 146 deletions
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  1. 9
      CHANGELOG
  2. 8
      common/cmd_bdinfo.c
  3. 2
      common/lynxkdi.c
  4. 4
      cpu/ppc4xx/405gp_enet.c
  5. 6
      cpu/ppc4xx/405gp_pci.c
  6. 50
      cpu/ppc4xx/440gx_enet.c
  7. 2
      cpu/ppc4xx/cpu.c
  8. 2
      cpu/ppc4xx/cpu_init.c
  9. 44
      cpu/ppc4xx/interrupts.c
  10. 8
      cpu/ppc4xx/miiphy_440.c
  11. 20
      cpu/ppc4xx/serial.c
  12. 2
      cpu/ppc4xx/spd_sdram.c
  13. 4
      cpu/ppc4xx/speed.c
  14. 18
      cpu/ppc4xx/start.S
  15. 2
      cpu/ppc4xx/usb_ohci.c
  16. 4
      cpu/ppc4xx/usbdev.c
  17. 2
      drivers/pci_indirect.c
  18. 4
      include/405gp_enet.h
  19. 4
      include/440_i2c.h
  20. 22
      include/440gx_enet.h
  21. 8
      include/asm-ppc/u-boot.h
  22. 2
      include/configs/XPEDITE1K.h
  23. 6
      include/configs/bamboo.h
  24. 2
      include/configs/ocotea.h
  25. 8
      include/configs/yellowstone.h
  26. 8
      include/configs/yosemite.h
  27. 44
      include/ppc440.h
  28. 2
      lib_ppc/board.c

9
CHANGELOG
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@ -2,6 +2,11 @@
Changes for U-Boot 1.1.3:
======================================================================
* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to
CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design
with the 405 defines and the linux kernel defines.
Patch by Stefan Roese, 08 Aug 2005
* Add common (with Linux) MTD partition scheme and "mtdparts" command
Old, obsolete and duplicated code was cleaned up and replace by the
@ -34,13 +39,13 @@ Changes for U-Boot 1.1.3:
* Fix errors that occur when accessing SystemACE CF
Patch by Jeff Angielski, 09 Jan 2005
* Document switching between U-Boot and PlanetCore on RPXlite
by Sam Song, 24 Dec 2004
* Fix PowerQUICC II mask detection.
Patch by Eugene Surovegin, 20 Dec 2004
* Add support for Altera NIOS DK1C20 board
Patch by Shlomo Kut, 13 Dec 2004

8
common/cmd_bdinfo.c
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@ -62,14 +62,14 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_num ("bootflags", bd->bi_bootflags );
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
defined(CONFIG_440EP) || defined(CONFIG_440GR)
print_str ("procfreq", strmhz(buf, bd->bi_procfreq));
print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq));
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
defined(CONFIG_440EP) || defined(CONFIG_440GR)
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440_EP CONFIG_440_GR */
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_CPM2)
print_str ("vco", strmhz(buf, bd->bi_vco));
print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq));
@ -80,7 +80,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq));
#endif
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440_EP CONFIG_440_GR */
#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_MPC8220)
print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq));
print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq));

2
common/lynxkdi.c
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@ -20,7 +20,7 @@
#if defined(CONFIG_LYNXKDI)
#include <lynxkdi.h>
#if defined(CONFIG_MPC8260) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
void lynxkdi_boot ( image_header_t *hdr )
{
void (*lynxkdi)(void) = (void(*)(void))hdr->ih_ep;

4
cpu/ppc4xx/405gp_enet.c
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@ -227,7 +227,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
while (mfdcr (malmcr) & MAL_CR_MMSR) {
};
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
out32 (ZMII_FER, 0);
udelay(100);
/* set RII mode */
@ -464,7 +464,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
else
out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_mfr, reg);
/* set speed */
if (speed == _100BASET) {

6
cpu/ppc4xx/405gp_pci.c
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@ -437,7 +437,7 @@ void pci_440_init (struct pci_controller *hose)
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
#if defined (CONFIG_440_GX) || defined (CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_sdstp1,strap);
if ( (strap & 0x00010000) == 0 ){
printf("PCI: SDR0_STRP1[PISE] not set.\n");
@ -495,7 +495,7 @@ void pci_440_init (struct pci_controller *hose)
out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
#elif defined(PCIX0_BRDGOPT1)
@ -531,7 +531,7 @@ void pci_440_init (struct pci_controller *hose)
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
#if !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
#endif
hose->last_busno = pci_hose_scan(hose);

50
cpu/ppc4xx/440gx_enet.c
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@ -175,7 +175,7 @@ static void ppc_440x_eth_halt (struct eth_device *dev)
extern int phy_setup_aneg (unsigned char addr);
extern int miiphy_reset (unsigned char addr);
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long pfc1;
@ -279,7 +279,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
unsigned short devnum;
unsigned short reg_short;
sys_info_t sysinfo;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
int ethgroup;
#endif
@ -323,7 +323,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* MAL Channel RESET */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
@ -362,9 +362,9 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
out32 (ZMII_FER, 0);
udelay (100);
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#elif defined(CONFIG_440_GX)
#elif defined(CONFIG_440GX)
ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
#else
if ((devnum == 0) || (devnum == 1)) {
@ -391,7 +391,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
failsafe--;
}
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
@ -406,7 +406,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
mode_reg |= EMAC_M1_OBCI_GT100;
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440_GX) */
#endif /* defined(CONFIG_440GX) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
@ -418,7 +418,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
case 1:
reg = CONFIG_PHY1_ADDR;
break;
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
case 2:
reg = CONFIG_PHY2_ADDR;
break;
@ -441,7 +441,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
if (hw_p->first_init == 0) {
miiphy_reset (reg);
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#if defined(CONFIG_CIS8201_PHY)
/*
* Cicada 8201 PHY needs to have an extended register whacked
@ -512,7 +512,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_mfr, reg);
if (speed == 100) {
reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
@ -541,7 +541,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
}
/* set the Mal configuration reg */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
@ -642,7 +642,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
#if defined (CONFIG_440_EP) || defined (CONFIG_440_GR)
#if defined (CONFIG_440EP) || defined (CONFIG_440GR)
mtdcr (maltxctp2r, hw_p->tx);
#else
mtdcr (maltxctp1r, hw_p->tx);
@ -653,7 +653,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* set RX buffer size */
mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
break;
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
case 2:
/* setup MAL tx & rx channel pointers */
mtdcr (maltxbattr, 0x0);
@ -672,7 +672,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* set RX buffer size */
mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
break;
#endif /*CONFIG_440_GX */
#endif /*CONFIG_440GX */
case 0:
default:
/* setup MAL tx & rx channel pointers */
@ -686,7 +686,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
}
/* Enable MAL transmit and receive channels */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
@ -836,7 +836,7 @@ int enetInt (struct eth_device *dev)
unsigned long mal_rx_eob;
unsigned long my_uic0msr, my_uic1msr;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
unsigned long my_uic2msr;
#endif
EMAC_440GX_HW_PST hw_p;
@ -856,7 +856,7 @@ int enetInt (struct eth_device *dev)
my_uic0msr = mfdcr (uic0msr);
my_uic1msr = mfdcr (uic1msr);
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
my_uic2msr = mfdcr (uic2msr);
#endif
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
@ -866,7 +866,7 @@ int enetInt (struct eth_device *dev)
/* not for us */
return (rc);
}
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
&& !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
/* not for us */
@ -922,7 +922,7 @@ int enetInt (struct eth_device *dev)
return (rc); /* we had errors so get out */
}
}
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
if (hw_p->devnum == 2) {
if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
@ -958,7 +958,7 @@ int enetInt (struct eth_device *dev)
return (rc); /* we had errors so get out */
}
}
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/* handle MAX TX EOB interrupt from a tx */
if (my_uic0msr & UIC_MTE) {
mal_rx_eob = mfdcr (maltxeobisr);
@ -987,14 +987,14 @@ int enetInt (struct eth_device *dev)
case 1:
mtdcr (uic1sr, UIC_ETH1);
break;
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
case 2:
mtdcr (uic2sr, UIC_ETH2);
break;
case 3:
mtdcr (uic2sr, UIC_ETH3);
break;
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
default:
break;
}
@ -1184,7 +1184,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
int eth_num = 0;
EMAC_440GX_HW_PST hw = NULL;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
unsigned long pfc1;
mfsdr (sdr_pfc1, pfc1);
@ -1197,7 +1197,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
#if defined(CONFIG_PHY1_ADDR)
bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
bis->bi_phymode[0] = 0;
@ -1205,7 +1205,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
bis->bi_phymode[2] = 2;
bis->bi_phymode[3] = 2;
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
ppc_440x_eth_setup_bridge(0, bis);
#endif
#endif

2
cpu/ppc4xx/cpu.c
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@ -178,7 +178,7 @@ int checkcpu (void)
case PVR_440GX_RC:
puts("GX Rev. C");
break;
#if defined(CONFIG_440_GR)
#if defined(CONFIG_440GR)
case PVR_440EP_RA:
puts("GR Rev. A");
break;

2
cpu/ppc4xx/cpu_init.c
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@ -188,7 +188,7 @@ cpu_init_f (void)
unsigned long val;
val = mfspr(tcr);
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */

44
cpu/ppc4xx/interrupts.c
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@ -54,12 +54,12 @@ static struct irq_action irq_vecs1[32]; /* For UIC1 */
void uic1_interrupt( void * parms); /* UIC1 handler */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
static struct irq_action irq_vecs2[32]; /* For UIC2 */
void uic0_interrupt( void * parms); /* UIC0 handler */
void uic2_interrupt( void * parms); /* UIC2 handler */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#endif /* CONFIG_440 */
@ -115,11 +115,11 @@ int interrupt_init_cpu (unsigned *decrementer_count)
irq_vecs1[vec].handler = NULL;
irq_vecs1[vec].arg = NULL;
irq_vecs1[vec].count = 0;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
irq_vecs2[vec].handler = NULL;
irq_vecs2[vec].arg = NULL;
irq_vecs2[vec].count = 0;
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#endif
}
@ -162,14 +162,14 @@ int interrupt_init_cpu (unsigned *decrementer_count)
set_evpr(0x00000000);
#if defined(CONFIG_440)
#if !defined(CONFIG_440_GX)
#if !defined(CONFIG_440GX)
/* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
#endif
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* Take the GX out of compatibility mode
* Travis Sawyer, 9 Mar 2004
* NOTE: 440gx user manual inconsistency here
@ -195,7 +195,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
/*
* Handle external interrupts
*/
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
void external_interrupt(struct pt_regs *regs)
{
ulong uic_msr;
@ -219,7 +219,7 @@ void external_interrupt(struct pt_regs *regs)
return;
} /* external_interrupt CONFIG_440_GX */
} /* external_interrupt CONFIG_440GX */
#else
@ -266,7 +266,7 @@ void external_interrupt(struct pt_regs *regs)
}
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* Handler for UIC0 interrupt */
void uic0_interrupt( void * parms)
{
@ -310,7 +310,7 @@ void uic0_interrupt( void * parms)
}
}
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#if defined(CONFIG_440)
/* Handler for UIC1 interrupt */
@ -357,7 +357,7 @@ void uic1_interrupt( void * parms)
}
#endif /* defined(CONFIG_440) */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* Handler for UIC1 interrupt */
void uic2_interrupt( void * parms)
{
@ -400,7 +400,7 @@ void uic2_interrupt( void * parms)
vec++;
}
}
#endif /* defined(CONFIG_440_GX) */
#endif /* defined(CONFIG_440GX) */
/****************************************************************************/
@ -414,7 +414,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
int i = vec;
#if defined(CONFIG_440)
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64)) {
i = vec - 32;
irqa = irq_vecs1;
@ -422,12 +422,12 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
i = vec - 64;
irqa = irq_vecs2;
}
#else /* CONFIG_440_GX */
#else /* CONFIG_440GX */
if (vec > 31) {
i = vec - 32;
irqa = irq_vecs1;
}
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#endif /* CONFIG_440 */
/*
@ -441,13 +441,13 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
irqa[i].arg = arg;
#if defined(CONFIG_440)
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else if (vec > 63)
mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
else
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
if (vec > 31)
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else
@ -464,7 +464,7 @@ void irq_free_handler (int vec)
int i = vec;
#if defined(CONFIG_440)
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64)) {
irqa = irq_vecs1;
i = vec - 32;
@ -472,7 +472,7 @@ void irq_free_handler (int vec)
irqa = irq_vecs2;
i = vec - 64;
}
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
if (vec > 31) {
irqa = irq_vecs1;
i = vec - 32;
@ -485,13 +485,13 @@ void irq_free_handler (int vec)
#endif
#if defined(CONFIG_440)
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else if (vec > 63)
mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
else
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
if (vec > 31)
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else
@ -553,7 +553,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("\n");
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
printf ("\nUIC 2\n");
printf ("Nr Routine Arg Count\n");

8
cpu/ppc4xx/miiphy_440.c
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@ -165,13 +165,13 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
}
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_READ;
#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
#endif
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
@ -225,13 +225,13 @@ int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
sta_reg = 0;
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_WRITE;
#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
#endif
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */

20
cpu/ppc4xx/serial.c
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@ -269,14 +269,14 @@ int serial_tstc ()
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
#if defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
#else
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
#endif
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
@ -284,7 +284,7 @@ int serial_tstc ()
#define CR0_MASK 0x3fff0000
#define CR0_EXTCLK_ENA 0x00600000
#define CR0_UDIV_POS 16
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#elif defined(CONFIG_405EP)
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
@ -306,17 +306,17 @@ int serial_tstc ()
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UART0_SDR sdr_uart1
#define UART1_SDR sdr_uart0
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#endif
#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
@ -436,7 +436,7 @@ int serial_init(void)
unsigned long tmp;
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
mfsdr(UART0_SDR,reg);
@ -451,7 +451,7 @@ int serial_init(void)
#endif
#else
reg = mfdcr(cntrl0) & ~CR0_MASK;
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#ifdef CFG_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
@ -465,7 +465,7 @@ int serial_init(void)
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {

2
cpu/ppc4xx/spd_sdram.c
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@ -734,7 +734,7 @@ long int spd_sdram(void) {
*/
check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/*
* Soft-reset SDRAM controller.
*/

4
cpu/ppc4xx/speed.c
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@ -195,7 +195,7 @@ ulong get_PCI_freq (void)
#elif defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
void get_sys_info (sys_info_t *sysInfo)
{
unsigned long temp;
@ -283,7 +283,7 @@ ulong get_PCI_freq (void)
return sys_info.freqPCI;
}
#elif !defined(CONFIG_440_GX)
#elif !defined(CONFIG_440GX)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;

18
cpu/ppc4xx/start.S
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@ -166,7 +166,7 @@ _start_440:
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
#if defined (CONFIG_440GX) /* NOTE: 440GX adds machine check status regs */
mtspr mcsrr0,r0
mtspr mcsrr1,r0
mfspr r1, mcsr
@ -340,11 +340,11 @@ _start:
mtspr tcr,r0 /* disable all */
mtspr esr,r0 /* clear exception syndrome register */
mtxer r0 /* clear integer exception register */
#if !defined(CONFIG_440_GX)
#if !defined(CONFIG_440GX)
lis r1,0x0002 /* set CE bit (Critical Exceptions) */
ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
mtmsr r1 /* change MSR */
#elif !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
bl __440gx_msr_set
b __440gx_msr_continue
@ -377,7 +377,7 @@ __440gx_msr_continue:
/* Setup the internal SRAM */
/*----------------------------------------------------------------*/
li r0,0
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* Clear Dcache to use as RAM */
addis r3,r0,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
@ -394,7 +394,7 @@ __440gx_msr_continue:
addi r3,r3,32
bdnz ..d_ag
#else
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
@ -409,7 +409,7 @@ __440gx_msr_continue:
mtdcr isram0_pmeg,r1
lis r1,0x8000 /* BAS = 8000_0000 */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
ori r1,r1,0x0980 /* first 64k */
mtdcr isram0_sb0cr,r1
lis r1,0x8001
@ -975,7 +975,7 @@ invalidate_icache:
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
#else
@ -1001,7 +1001,7 @@ flush_dcache:
mtdccr r10
/* do loop for # of congruence classes. */
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
@ -1228,7 +1228,7 @@ ppcSync:
*/
.globl relocate_code
relocate_code:
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
addi r1,r0,0x0000 /* Tlb entry #0 */

2
cpu/ppc4xx/usb_ohci.c
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@ -76,7 +76,7 @@
#define m16_swap(x) swap_16(x)
#define m32_swap(x) swap_32(x)
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
#define ohci_cpu_to_le16(x) (x)
#define ohci_cpu_to_le32(x) (x)
#else

4
cpu/ppc4xx/usbdev.c
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@ -3,7 +3,7 @@
#include <common.h>
#include <asm/processor.h>
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
#include <usb.h>
#include "usbdev.h"
@ -211,4 +211,4 @@ void usb_dev_init()
NULL);
}
#endif /*CONFIG_440_EP */
#endif /*CONFIG_440EP */

2
drivers/pci_indirect.c
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@ -52,7 +52,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \

4
include/405gp_enet.h
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@ -67,7 +67,7 @@ struct arp_entry {
/*Register addresses */
#if defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
@ -81,7 +81,7 @@ struct arp_entry {
#endif /* CONFIG_440 */
#if defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)

4
include/440_i2c.h
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@ -1,11 +1,11 @@
#ifndef _440_i2c_h_
#define _440_i2c_h_
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
#else
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
#endif /*CONFIG_440_EP CONFIG_440_GR*/
#endif /*CONFIG_440EP CONFIG_440GR*/
#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)

22
include/440gx_enet.h
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@ -130,9 +130,9 @@ typedef struct emac_440gx_hw_st {
} EMAC_440GX_HW_ST, *EMAC_440GX_HW_PST;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define EMAC_NUM_DEV 4
#elif defined(CONFIG_440) && !defined(CONFIG_440_GX)
#elif defined(CONFIG_440) && !defined(CONFIG_440GX)
#define EMAC_NUM_DEV 2
#else
#warning Bad configuration
@ -140,7 +140,7 @@ typedef struct emac_440gx_hw_st {
/*ZMII Bridge Register addresses */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
@ -212,7 +212,7 @@ typedef struct emac_440gx_hw_st {
/*---------------------------------------------------------------------------+
| TCP/IP Acceleration Hardware (TAH) 440GX Only
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50)
#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
@ -272,11 +272,11 @@ typedef struct emac_440gx_hw_st {
#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/* Ethernet MAC Regsiter Addresses */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
@ -319,7 +319,7 @@ typedef struct emac_440gx_hw_st {
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
@ -349,7 +349,7 @@ typedef struct emac_440gx_hw_st {
#define EMAC_M1_OBCI_83 (0x00000010)
#define EMAC_M1_OBCI_66 (0x00000008)
#define EMAC_M1_RSVD1 (0x00000007)
#else /* defined(CONFIG_440_GX) */
#else /* defined(CONFIG_440GX) */
/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
#define EMAC_M1_FDE 0x80000000
#define EMAC_M1_ILE 0x40000000
@ -369,10 +369,10 @@ typedef struct emac_440gx_hw_st {
#define EMAC_M1_TR0_MULTI 0x00008000
#define EMAC_M1_TR1_DEPEND 0x00004000
#define EMAC_M1_TR1_MULTI 0x00002000
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define EMAC_M1_JUMBO_ENABLE 0x00001000
#endif /* defined(CONFIG_440_EP) || defined(CONFIG_440_GR) */
#endif /* defined(CONFIG_440_GX) */
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#endif /* defined(CONFIG_440GX) */
/* Transmit Mode Register 0 */
#define EMAC_TXM0_GNP0 (0x80000000)

8
include/asm-ppc/u-boot.h
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@ -101,19 +101,19 @@ typedef struct bd_info {
unsigned char bi_enet3addr[6];
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440_GX) || \
defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
unsigned int bi_opbfreq; /* OPB clock in Hz */
int bi_iic_fast[2]; /* Use fast i2c mode */
#endif
#if defined(CONFIG_NX823)
unsigned char bi_sernum[8];
#endif
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
int bi_phynum[2]; /* Determines phy mapping */
int bi_phymode[2]; /* Determines phy mode */
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
int bi_phynum[4]; /* Determines phy mapping */
int bi_phymode[4]; /* Determines phy mode */
#endif

2
include/configs/XPEDITE1K.h
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@ -36,7 +36,7 @@
#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
#define CONFIG_440_GX 1 /* 440 GX */
#define CONFIG_440GX 1 /* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */

6
include/configs/bamboo.h
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@ -31,7 +31,7 @@
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
#define CONFIG_440_EP 1 /* Specific PPC440EP support */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
@ -219,14 +219,14 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
#endif /*CONFIG_440EP*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \

2
include/configs/ocotea.h
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@ -40,7 +40,7 @@
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_OCOTEA 1 /* Board is ebony */
#define CONFIG_440_GX 1 /* Specifc GX support */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */

8
include/configs/yellowstone.h
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@ -29,7 +29,7 @@
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */
#define CONFIG_440_GR 1 /* Specific PPC440GR support */
#define CONFIG_440GR 1 /* Specific PPC440GR support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
@ -161,14 +161,14 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
#endif /*CONFIG_440EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
@ -176,7 +176,7 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \

8
include/configs/yosemite.h
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@ -29,7 +29,7 @@
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YOSEMITE 1 /* Board is BAMBOO */
#define CONFIG_440_EP 1 /* Specific PPC440EP support */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
@ -175,14 +175,14 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
#endif /*CONFIG_440EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
@ -190,7 +190,7 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \

44
include/ppc440.h
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@ -78,7 +78,7 @@
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
@ -241,7 +241,7 @@
#define xbcfg 0x23 /* external bus configuration reg */
#define xbcid 0x23 /* external bus core id reg */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* PLB4 to PLB3 Bridge OUT */
#define P4P3_DCR_BASE 0x020
@ -504,7 +504,7 @@
/*-----------------------------------------------------------------------------
| L2 Cache
+----------------------------------------------------------------------------*/
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
#define L2_CACHE_BASE 0x030
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
@ -515,8 +515,8 @@
#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
#endif /* CONFIG_440_GX */
#endif /* !CONFIG_440_EP !CONFIG_440_GR*/
#endif /* CONFIG_440GX */
#endif /* !CONFIG_440EP !CONFIG_440GR*/
/*-----------------------------------------------------------------------------
| On-Chip Buses
@ -527,7 +527,7 @@
| Clocking, Power Management and Chip Control
+----------------------------------------------------------------------------*/
#define CNTRL_DCR_BASE 0x0b0
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
@ -573,7 +573,7 @@
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define UIC2_DCR_BASE 0x210
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
@ -594,7 +594,7 @@
#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/* The following is for compatibility with 405 code */
#define uicsr uic0sr
@ -673,16 +673,16 @@
#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
@ -770,7 +770,7 @@
/*---------------------------------------------------------------------------+
| Universal interrupt controller 2 interrupts (UIC2)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define UIC_ETH2 0x80000000 /* Ethernet 2 */
#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
#define UIC_ETH3 0x20000000 /* Ethernet 3 */
@ -803,12 +803,12 @@
#define UIC_RSVD29 0x00000004 /* Reserved */
#define UIC_RSVD30 0x00000002 /* Reserved */
#define UIC_RSVD31 0x00000001 /* Reserved */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
| Universal interrupt controller Base 0 interrupts (UICB0)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
@ -818,7 +818,7 @@
#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/*-----------------------------------------------------------------------------+
| External Bus Controller Bit Settings
@ -1194,7 +1194,7 @@
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
#if !defined (CONFIG_440_GX) && !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
@ -1212,7 +1212,7 @@
#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
#else /* !CONFIG_440_GX or CONFIG_440_EP or CONFIG_440_GR */
#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
@ -1260,7 +1260,7 @@
#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/*-----------------------------------------------------------------------------
| IIC Register Offsets
@ -1303,7 +1303,7 @@
#define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
#define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* PCI Local Configuration Registers
--------------------------------- */
@ -1387,12 +1387,12 @@
#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
#endif /* !defined(CONFIG_440_EP) !defined(CONFIG_440_GR) */
#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
/******************************************************************************
* GPIO macro register defines
******************************************************************************/
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)

2
lib_ppc/board.c
Unescape View File

@ -547,7 +547,7 @@ void board_init_f (ulong bootflag)
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = gd->bus_clk;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
bd->bi_pci_busfreq = get_PCI_freq ();
bd->bi_opbfreq = get_OPB_freq ();
#elif defined(CONFIG_XILINX_ML300)

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