ARM: rmobile: salvator-x: Adjust UART clock

The UART uses internal SCIF clock except on R8A7795 H3 WS1.0 .
Use the internal clock and ignore the early version of the chip.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

board/renesas/salvator-x/salvator-x.c

@@ -109,8 +109,8 @@ void reset_cpu(ulong addr)
 static const struct sh_serial_platdata serial_platdata = {
 	.base = SCIF2_BASE,
 	.type = PORT_SCIF,
-	.clk = 14745600,		/* 0xE10000 */
-	.clk_mode = EXT_CLK,
+	.clk = CONFIG_SH_SCIF_CLK_FREQ,
+	.clk_mode = INT_CLK,
 };
 
 U_BOOT_DEVICE(salvator_x_scif2) = {

include/configs/salvator-x.h

@@ -20,7 +20,7 @@
 #define CONFIG_SCIF_CONSOLE
 #define CONFIG_CONS_SCIF2
 #define CONFIG_CONS_INDEX	2
-#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ        CONFIG_S3D4_CLK_FREQ
 
 /* [A] Hyper Flash */
 /* use to RPC(SPI Multi I/O Bus Controller) */
@@ -31,10 +31,11 @@
 #define RCAR_XTAL_CLK		33333333u
 #define CONFIG_SYS_CLK_FREQ	RCAR_XTAL_CLK
 /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
-/* CPclk 16.66MHz, S3D2 133.33MHz                          */
+/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz          */
 #define CONFIG_CP_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
 #define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 192 / 2)
 #define CONFIG_S3D2_CLK_FREQ	(266666666u/2)
+#define CONFIG_S3D4_CLK_FREQ	(266666666u/4)
 
 /* Generic Timer Definitions (use in assembler source) */
 #define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */

scripts/config_whitelist.txt

@@ -2371,6 +2371,7 @@ CONFIG_S3C24XX_TACLS
 CONFIG_S3C24XX_TWRPH0
 CONFIG_S3C24XX_TWRPH1
 CONFIG_S3D2_CLK_FREQ
+CONFIG_S3D4_CLK_FREQ
 CONFIG_S5P
 CONFIG_S5PC100
 CONFIG_S5PC110