Add basic Xilinx ZynqMP arm64 support. Serial and SD is supported. It supports emulation platfrom ep108 and QEMU. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>master
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#
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# (C) Copyright 2014 - 2015 Xilinx, Inc.
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# Michal Simek <michal.simek@xilinx.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += clk.o
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obj-y += cpu.o
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/sys_proto.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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unsigned long get_uart_clk(int dev_id) |
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{ |
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u32 ver = zynqmp_get_silicon_version(); |
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switch (ver) { |
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case ZYNQMP_CSU_VERSION_EP108: |
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return 25000000; |
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} |
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return 133000000; |
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} |
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#ifdef CONFIG_CLOCKS |
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/**
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* set_cpu_clk_info() - Initialize clock framework |
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* Always returns zero. |
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* |
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* This function is called from common code after relocation and sets up the |
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* clock framework. The framework must not be used before this function had been |
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* called. |
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*/ |
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int set_cpu_clk_info(void) |
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{ |
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gd->cpu_clk = get_tbclk(); |
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/* Support Veloce to show at least 1MHz via bdi */ |
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if (gd->cpu_clk > 1000000) |
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gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; |
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else |
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gd->bd->bi_arm_freq = 1; |
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gd->bd->bi_dsp_freq = 0; |
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return 0; |
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} |
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#endif |
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/io.h> |
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#define ZYNQ_SILICON_VER_MASK 0xF000 |
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#define ZYNQ_SILICON_VER_SHIFT 12 |
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DECLARE_GLOBAL_DATA_PTR; |
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unsigned int zynqmp_get_silicon_version(void) |
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{ |
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gd->cpu_clk = get_tbclk(); |
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switch (gd->cpu_clk) { |
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case 50000000: |
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return ZYNQMP_CSU_VERSION_QEMU; |
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} |
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return ZYNQMP_CSU_VERSION_EP108; |
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} |
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_CLK_H_ |
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#define _ASM_ARCH_CLK_H_ |
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unsigned long get_uart_clk(int dev_id); |
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#endif /* _ASM_ARCH_CLK_H_ */ |
@ -0,0 +1,52 @@ |
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_HARDWARE_H |
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#define _ASM_ARCH_HARDWARE_H |
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#define ZYNQ_SERIAL_BASEADDR0 0xFF000000 |
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#define ZYNQ_SERIAL_BASEADDR1 0xFF001000 |
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#define ZYNQ_SDHCI_BASEADDR0 0xFF160000 |
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#define ZYNQ_SDHCI_BASEADDR1 0xFF170000 |
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#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 |
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#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 |
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struct crlapb_regs { |
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u32 reserved0[74]; |
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u32 timestamp_ref_ctrl; /* 0x128 */ |
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u32 reserved0_1[53]; |
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u32 boot_mode; /* 0x200 */ |
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u32 reserved1[26]; |
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}; |
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#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) |
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#define ZYNQMP_IOU_SCNTR 0xFF250000 |
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 |
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 |
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struct iou_scntr { |
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u32 counter_control_register; |
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u32 reserved0[7]; |
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u32 base_frequency_id_register; |
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}; |
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#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) |
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/* Bootmode setting values */ |
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#define BOOT_MODES_MASK 0x0000000F |
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#define SD_MODE 0x00000005 |
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#define JTAG_MODE 0x00000000 |
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/* Board version value */ |
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#define ZYNQMP_CSU_VERSION_SILICON 0x0 |
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#define ZYNQMP_CSU_VERSION_EP108 0x1 |
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#define ZYNQMP_CSU_VERSION_QEMU 0x3 |
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#endif /* _ASM_ARCH_HARDWARE_H */ |
@ -0,0 +1,15 @@ |
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_SYS_PROTO_H |
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#define _ASM_ARCH_SYS_PROTO_H |
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int zynq_sdhci_init(unsigned long regbase); |
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unsigned int zynqmp_get_silicon_version(void); |
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#endif /* _ASM_ARCH_SYS_PROTO_H */ |
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if TARGET_XILINX_ZYNQMP |
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config SYS_BOARD |
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default "zynqmp" |
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config SYS_VENDOR |
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default "xilinx" |
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config SYS_SOC |
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default "zynqmp" |
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config SYS_CONFIG_NAME |
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default "xilinx_zynqmp" |
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endif |
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XILINX_ZYNQMP BOARD |
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M: Michal Simek <michal.simek@xilinx.com> |
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S: Maintained |
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F: board/xilinx/zynqmp/ |
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F: include/configs/xilinx_zynqmp.h |
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F: configs/xilinx_zynqmp_defconfig |
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#
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# (C) Copyright 2014 - 2015 Xilinx, Inc.
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# Michal Simek <michal.simek@xilinx.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := zynqmp.o
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_init(void) |
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{ |
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return 0; |
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} |
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int board_early_init_r(void) |
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{ |
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u32 val; |
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val = readl(&crlapb_base->timestamp_ref_ctrl); |
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val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; |
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writel(val, &crlapb_base->timestamp_ref_ctrl); |
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/* Program freq register in System counter and enable system counter */ |
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writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); |
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writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | |
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ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, |
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&iou_scntr->counter_control_register); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
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return 0; |
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} |
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int timer_init(void) |
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{ |
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return 0; |
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} |
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void reset_cpu(ulong addr) |
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{ |
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} |
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#ifdef CONFIG_CMD_MMC |
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int board_mmc_init(bd_t *bd) |
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{ |
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int ret = 0; |
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#if defined(CONFIG_ZYNQ_SDHCI) |
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# if defined(CONFIG_ZYNQ_SDHCI0) |
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ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); |
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# endif |
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# if defined(CONFIG_ZYNQ_SDHCI1) |
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ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); |
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# endif |
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#endif |
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return ret; |
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} |
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#endif |
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int board_late_init(void) |
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{ |
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u32 reg = 0; |
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u8 bootmode; |
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reg = readl(&crlapb_base->boot_mode); |
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bootmode = reg & BOOT_MODES_MASK; |
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switch (bootmode) { |
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case SD_MODE: |
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setenv("modeboot", "sdboot"); |
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break; |
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default: |
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printf("Invalid Boot Mode:0x%x\n", bootmode); |
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break; |
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} |
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return 0; |
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} |
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CONFIG_ARM=y |
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CONFIG_TARGET_XILINX_ZYNQMP=y |
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CONFIG_CMD_BDI=y |
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CONFIG_CMD_BOOTD=y |
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CONFIG_CMD_RUN=y |
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CONFIG_CMD_IMI=y |
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CONFIG_CMD_SAVEENV=y |
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CONFIG_CMD_FLASH=y |
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CONFIG_CMD_ECHO=y |
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CONFIG_CMD_SOURCE=y |
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CONFIG_CMD_TIME=y |
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CONFIG_CMD_MISC=y |
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CONFIG_CMD_TIMER=y |
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CONFIG_DEFAULT_DEVICE_TREE="zynqmp" |
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/*
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* Configuration for Xilinx ZynqMP |
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* Based on Configuration for Versatile Express |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __XILINX_ZYNQMP_H |
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#define __XILINX_ZYNQMP_H |
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#define CONFIG_REMAKE_ELF |
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/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_SYS_GENERIC_BOARD |
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/* Generic Interrupt Controller Definitions */ |
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#define CONFIG_GICV2 |
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#define GICD_BASE 0xF9010000 |
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#define GICC_BASE 0xF9020000 |
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/* Physical Memory Map */ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define CONFIG_SYS_SDRAM_BASE 0 |
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#define CONFIG_SYS_SDRAM_SIZE 0x40000000 |
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
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#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE |
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/* Have release address at the end of 256MB for now */ |
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#define CPU_RELEASE_ADDR 0xFFFFFF0 |
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/* Cache Definitions */ |
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#define CONFIG_SYS_DCACHE_OFF |
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#define CONFIG_IDENT_STRING " Xilinx ZynqMP" |
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#define CONFIG_SYS_TEXT_BASE 0x8000000 |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) |
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/* Flat Device Tree Definitions */ |
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#define CONFIG_OF_LIBFDT |
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/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ |
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#define COUNTER_FREQUENCY 4000000 |
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/* Size of malloc() pool */ |
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x400000) |
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/* Serial setup */ |
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#define CONFIG_ZYNQ_SERIAL_UART0 |
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#define CONFIG_ZYNQ_SERIAL |
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#define CONFIG_CONS_INDEX 0 |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_SYS_BAUDRATE_TABLE \ |
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{ 4800, 9600, 19200, 38400, 57600, 115200 } |
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/* Command line configuration */ |
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#define CONFIG_CMD_ENV |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_CMD_EXT4 |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_MEMORY |
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#define CONFIG_DOS_PARTITION |
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#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) |
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# define CONFIG_MMC |
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# define CONFIG_GENERIC_MMC |
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# define CONFIG_SDHCI |
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# define CONFIG_ZYNQ_SDHCI |
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# define CONFIG_CMD_MMC |
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#endif |
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#if defined(CONFIG_ZYNQ_SDHCI) |
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# define CONFIG_FAT_WRITE |
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# define CONFIG_CMD_EXT4_WRITE |
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#endif |
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/* Miscellaneous configurable options */ |
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#define CONFIG_SYS_LOAD_ADDR 0x8000000 |
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/* Initial environment variables */ |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"kernel_addr=0x80000\0" \
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"fdt_addr=0x7000000\0" \
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"fdt_high=0x10000000\0" \
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"sdboot=mmcinfo && fatload mmc 0:0 $fdt_addr system.dtb && " \
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"fatload mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" |
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#define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \ |
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"earlycon=cdns,mmio,0xff000000,${baudrate}n8" |
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#define CONFIG_PREBOOT "run bootargs" |
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#define CONFIG_BOOTCOMMAND "run $modeboot" |
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#define CONFIG_BOOTDELAY 5 |
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#define CONFIG_BOARD_LATE_INIT |
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/* Do not preserve environment */ |
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#define CONFIG_ENV_IS_NOWHERE 1 |
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#define CONFIG_ENV_SIZE 0x1000 |
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/* Monitor Command Prompt */ |
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/* Console I/O Buffer Size */ |
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#define CONFIG_SYS_CBSIZE 2048 |
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#define CONFIG_SYS_PROMPT "ZynqMP> " |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
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sizeof(CONFIG_SYS_PROMPT) + 16) |
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#define CONFIG_SYS_HUSH_PARSER |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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#define CONFIG_SYS_LONGHELP |
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#define CONFIG_CMDLINE_EDITING |
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#define CONFIG_SYS_MAXARGS 64 |
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#define CONFIG_FIT |
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#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
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#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) |
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#define CONFIG_CMD_BOOTI |
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#define CONFIG_CMD_UNZIP |
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#define CONFIG_BOARD_EARLY_INIT_R |
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#define CONFIG_CLOCKS |
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#endif /* __XILINX_ZYNQMP_H */ |
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