nds32: Support AG101P serial DM.

Support AG101P serial device tree flow.

Signed-off-by: rick <rick@andestech.com>
master
rick 7 years ago committed by Andes
parent a375ff8e14
commit 86132af799
  1. 1
      arch/Kconfig
  2. 10
      arch/nds32/cpu/n1213/start.S
  3. 14
      arch/nds32/dts/Makefile
  4. 49
      arch/nds32/dts/ag101p.dts
  5. 1
      arch/nds32/include/asm/config.h
  6. 6
      arch/nds32/lib/bootm.c
  7. 5
      configs/adp-ag101p_defconfig
  8. 8
      include/configs/adp-ag101p.h

@ -43,6 +43,7 @@ config MIPS
config NDS32
bool "NDS32 architecture"
select SUPPORT_OF_CONTROL
config NIOS2
bool "Nios II architecture"

@ -161,9 +161,13 @@ update_gp:
*/
call_board_init_f:
li $sp, CONFIG_SYS_INIT_SP_ADDR
li $r10, GD_SIZE /* get GD size */
sub $sp, $sp, $r10 /* GD start addr */
move $r10, $sp
move $r0, $sp
bal board_init_f_alloc_reserve
move $sp, $r0
bal board_init_f_init_reserve
#ifdef CONFIG_DEBUG_UART
bal debug_uart_init
#endif
li $r0, 0x00000000
#ifdef __PIC__

@ -0,0 +1,14 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
clean-files := *.dtb

@ -0,0 +1,49 @@
/dts-v1/;
/ {
compatible = "nds32 ag101p";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
aliases {
uart0 = &serial0;
} ;
chosen {
/* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */
bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
stdout-path = "uart0:38400n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "andestech,n13";
reg = <0>;
/* FIXME: to fill correct frqeuency */
clock-frequency = <60000000>;
};
};
intc: interrupt-controller {
compatible = "andestech,atnointc010";
#interrupt-cells = <1>;
interrupt-controller;
};
serial0: serial@99600000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0x99600000 0x1000>;
interrupts = <7 4>;
clock-frequency = <14745600>;
reg-shift = <2>;
no-loopback-test = <1>;
};
};

@ -8,5 +8,6 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_LMB
#endif

@ -14,6 +14,12 @@
DECLARE_GLOBAL_DATA_PTR;
int arch_fixup_fdt(void *blob)
{
return 0;
}
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \

@ -1,5 +1,7 @@
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG101P=y
CONFIG_DEFAULT_DEVICE_TREE="ag101p"
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="NDS32 # "
CONFIG_CMD_MMC=y
@ -12,4 +14,7 @@ CONFIG_CMD_FAT=y
CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_BAUDRATE=38400
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y

@ -20,8 +20,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
/*
* Definitions related to passing arguments to kernel.
*/
@ -35,6 +33,10 @@
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0x00500000
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
#define CONFIG_OF_EMBED
#endif
#else
#ifdef CONFIG_MEM_REMAP
#define CONFIG_SYS_TEXT_BASE 0x80000000
@ -87,7 +89,9 @@
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#endif
#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
/*

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