This board is still a non-generic board. Unused code in arch/powerpc/cpu/mpc8xx/video.c should be also deleted because CONFIG_VIDEO_ENCODER_AD7176, CONFIG_VIDEO_ENCODER_AD7177, CONFIG_VIDEO_ENCODER_AD7179 are not defined any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>master
parent
72ba368f45
commit
8737fc7529
@ -1,9 +0,0 @@ |
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if TARGET_RRVISION |
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|
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config SYS_BOARD |
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default "RRvision" |
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config SYS_CONFIG_NAME |
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default "RRvision" |
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endif |
@ -1,7 +0,0 @@ |
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RRVISION BOARD |
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M: Wolfgang Denk <wd@denx.de> |
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S: Maintained |
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F: board/RRvision/ |
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F: include/configs/RRvision.h |
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F: configs/RRvision_defconfig |
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F: configs/RRvision_LCD_defconfig |
@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = RRvision.o flash.o
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@ -1,222 +0,0 @@ |
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/*
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* (C) Copyright 2001-2002 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <mpc8xx.h> |
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/* ------------------------------------------------------------------------- */ |
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static long int dram_size (long int, long int *, long int); |
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|
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/* ------------------------------------------------------------------------- */ |
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#define _NOT_USED_ 0xFFFFFFFF |
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|
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const uint sdram_table[] = |
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{ |
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/*
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* Single Read. (Offset 0 in UPMA RAM) |
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*/ |
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, |
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0x1FF77C47, /* last */ |
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM) |
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* |
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* This is no UPM entry point. The following definition uses |
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* the remaining space to establish an initialization |
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* sequence, which is executed by a RUN command. |
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* |
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*/ |
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0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ |
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/*
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* Burst Read. (Offset 8 in UPMA RAM) |
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*/ |
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, |
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Single Write. (Offset 18 in UPMA RAM) |
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*/ |
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0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Burst Write. (Offset 20 in UPMA RAM) |
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*/ |
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, |
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ |
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_NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Refresh (Offset 30 in UPMA RAM) |
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*/ |
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
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0xFFFFFC84, 0xFFFFFC07, /* last */ |
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_NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Exception. (Offset 3c in UPMA RAM) |
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*/ |
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0x7FFFFC07, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, |
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}; |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Check Board Identity: |
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* |
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* Always return 1 (no second DRAM bank). |
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*/ |
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int checkboard (void) |
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{ |
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char buf[64]; |
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int i; |
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int l = getenv_f("serial#", buf, sizeof(buf)); |
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puts ("Board: RRvision "); |
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for (i=0; i < l; ++i) { |
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if (buf[i] == ' ') |
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break; |
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putc (buf[i]); |
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} |
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putc ('\n'); |
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return (0); |
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} |
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/* ------------------------------------------------------------------------- */ |
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phys_size_t initdram (int board_type) |
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{ |
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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unsigned long reg; |
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long int size8, size9; |
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long int size = 0; |
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upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); |
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/*
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* Preliminary prescaler for refresh (depends on number of |
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* banks): This value is selected for four cycles every 62.4 us |
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* with two SDRAM banks or four cycles every 31.2 us with one |
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* bank. It will be adjusted after memory sizing. |
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*/ |
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; |
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memctl->memc_mar = 0x00000088; |
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/*
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* Map controller bank 1 the SDRAM bank 2 at physical address 0. |
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*/ |
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memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM; |
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memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM; |
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ |
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udelay (200); |
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/* perform SDRAM initializsation sequence */ |
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memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
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udelay (1); |
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memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ |
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udelay (1); |
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
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udelay (1000); |
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/*
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* Check Bank 0 Memory Size |
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* |
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* try 8 column mode |
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*/ |
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size8 = dram_size (CONFIG_SYS_MAMR_8COL, |
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SDRAM_BASE2_PRELIM, |
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SDRAM_MAX_SIZE); |
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udelay (1000); |
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/*
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* try 9 column mode |
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*/ |
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size9 = dram_size (CONFIG_SYS_MAMR_9COL, |
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SDRAM_BASE2_PRELIM, |
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SDRAM_MAX_SIZE); |
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if (size8 < size9) { /* leave configuration at 9 columns */ |
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size = size9; |
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/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ |
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} else { /* back to 8 columns */ |
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size = size8; |
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; |
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udelay (500); |
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/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ |
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} |
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udelay (1000); |
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/*
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* Adjust refresh rate depending on SDRAM type |
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* For types > 128 MBit leave it at the current (fast) rate |
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*/ |
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if (size < 0x02000000) { |
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/* reduce to 15.6 us (62.4 us / quad) */ |
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; |
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udelay (1000); |
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} |
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/*
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* Final mapping |
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*/ |
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memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; |
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memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; |
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/*
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* No bank 1 |
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* |
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* invalidate bank |
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*/ |
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memctl->memc_br3 = 0; |
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/* adjust refresh rate depending on SDRAM type, one bank */ |
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reg = memctl->memc_mptpr; |
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reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ |
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memctl->memc_mptpr = reg; |
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udelay (10000); |
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return (size); |
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} |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Check memory range for valid RAM. A simple memory test determines |
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* the actually available RAM size between addresses `base' and |
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* `base + maxsize'. Some (not all) hardware errors are detected: |
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* - short between address lines |
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* - short between data lines |
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*/ |
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static long int dram_size (long int mamr_value, long int *base, |
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long int maxsize) |
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{ |
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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memctl->memc_mamr = mamr_value; |
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return (get_ram_size(base, maxsize)); |
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} |
@ -1,506 +0,0 @@ |
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/*
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* (C) Copyright 2000-2002 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#define DEBUG |
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#include <common.h> |
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#include <mpc8xx.h> |
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#ifndef CONFIG_ENV_ADDR |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
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#endif |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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unsigned long size; |
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int i; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size, size<<20); |
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} |
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/* Remap FLASH according to real size */ |
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memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK); |
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memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; |
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/* Re-do sizing to get full correct info */ |
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size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, |
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&flash_info[0]); |
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#endif |
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#ifdef CONFIG_ENV_IS_IN_FLASH |
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/* ENV protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, |
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&flash_info[0]); |
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#endif |
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flash_info[0].size = size; |
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return (size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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puts ("missing or unknown FLASH type\n"); |
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return; |
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} |
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|
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_AMD: puts ("AMD "); break; |
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case FLASH_MAN_FUJ: puts ("FUJITSU "); break; |
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default: puts ("Unknown Vendor "); break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); |
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break; |
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default: puts ("Unknown Chip Type\n"); |
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break; |
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} |
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|
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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|
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puts (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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puts ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " " |
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); |
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} |
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puts ("\n"); |
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return; |
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} |
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|
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/*-----------------------------------------------------------------------
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*/ |
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|
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|
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/*-----------------------------------------------------------------------
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*/ |
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|
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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|
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static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
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{ |
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short i; |
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ulong value; |
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ulong base = (ulong)addr; |
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|
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/* Write auto select command: read Manufacturer ID */ |
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addr[0x0555] = 0x00AA00AA; |
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addr[0x02AA] = 0x00550055; |
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addr[0x0555] = 0x00900090; |
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value = addr[0]; |
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|
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switch (value) { |
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case AMD_MANUFACT: |
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info->flash_id = FLASH_MAN_AMD; |
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break; |
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case FUJ_MANUFACT: |
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info->flash_id = FLASH_MAN_FUJ; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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} |
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|
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value = addr[1]; /* device ID */ |
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|
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switch (value) { |
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case AMD_ID_LV400T: |
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info->flash_id += FLASH_AM400T; |
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info->sector_count = 11; |
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info->size = 0x00100000; |
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break; /* => 1 MB */ |
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|
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case AMD_ID_LV400B: |
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info->flash_id += FLASH_AM400B; |
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info->sector_count = 11; |
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info->size = 0x00100000; |
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break; /* => 1 MB */ |
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|
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case AMD_ID_LV800T: |
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info->flash_id += FLASH_AM800T; |
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info->sector_count = 19; |
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info->size = 0x00200000; |
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break; /* => 2 MB */ |
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|
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case AMD_ID_LV800B: |
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info->flash_id += FLASH_AM800B; |
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info->sector_count = 19; |
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info->size = 0x00200000; |
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break; /* => 2 MB */ |
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|
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case AMD_ID_LV160T: |
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info->flash_id += FLASH_AM160T; |
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info->sector_count = 35; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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|
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case AMD_ID_LV160B: |
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info->flash_id += FLASH_AM160B; |
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info->sector_count = 35; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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case AMD_ID_LV320T: |
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info->flash_id += FLASH_AM320T; |
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info->sector_count = 71; |
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info->size = 0x00800000; |
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break; /* => 8 MB */ |
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|
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case AMD_ID_LV320B: |
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info->flash_id += FLASH_AM320B; |
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info->sector_count = 71; |
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info->size = 0x00800000; |
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break; /* => 8 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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} |
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|
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/* set up sector start address table */ |
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switch (value) { |
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case AMD_ID_LV400B: |
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case AMD_ID_LV800B: |
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case AMD_ID_LV160B: |
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/* set sector offsets for bottom boot block type */ |
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info->start[0] = base + 0x00000000; |
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info->start[1] = base + 0x00008000; |
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info->start[2] = base + 0x0000C000; |
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info->start[3] = base + 0x00010000; |
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for (i = 4; i < info->sector_count; i++) { |
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info->start[i] = base + (i * 0x00020000) - 0x00060000; |
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} |
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break; |
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case AMD_ID_LV400T: |
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case AMD_ID_LV800T: |
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case AMD_ID_LV160T: |
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/* set sector offsets for top boot block type */ |
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i = info->sector_count - 1; |
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info->start[i--] = base + info->size - 0x00008000; |
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info->start[i--] = base + info->size - 0x0000C000; |
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info->start[i--] = base + info->size - 0x00010000; |
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for (; i >= 0; i--) { |
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info->start[i] = base + i * 0x00020000; |
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} |
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break; |
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case AMD_ID_LV320B: |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base; |
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/*
|
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* The first 8 sectors are 8 kB, |
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* all the other ones are 64 kB |
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*/ |
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base += (i < 8) |
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? 2 * ( 8 << 10) |
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: 2 * (64 << 10); |
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} |
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break; |
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case AMD_ID_LV320T: |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base; |
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/*
|
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* The last 8 sectors are 8 kB, |
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* all the other ones are 64 kB |
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*/ |
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base += (i < (info->sector_count - 8)) |
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? 2 * (64 << 10) |
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: 2 * ( 8 << 10); |
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} |
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break; |
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default: |
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return (0); |
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break; |
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} |
||||
|
||||
/* check for protected sectors */ |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
||||
/* D0 = 1 if protected */ |
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addr = (volatile unsigned long *)(info->start[i]); |
||||
info->protect[i] = addr[2] & 1; |
||||
} |
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH. |
||||
*/ |
||||
if (info->flash_id != FLASH_UNKNOWN) { |
||||
addr = (volatile unsigned long *)info->start[0]; |
||||
|
||||
*addr = 0x00F000F0; /* reset bank */ |
||||
} |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
vu_long *addr = (vu_long*)(info->start[0]); |
||||
int flag, prot, sect, l_sect; |
||||
ulong start, now, last; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
puts ("- missing\n"); |
||||
} else { |
||||
puts ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) || |
||||
(info->flash_id > FLASH_AMD_COMP)) { |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
puts ("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0x00AA00AA; |
||||
addr[0x02AA] = 0x00550055; |
||||
addr[0x0555] = 0x00800080; |
||||
addr[0x0555] = 0x00AA00AA; |
||||
addr[0x02AA] = 0x00550055; |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr = (vu_long*)(info->start[sect]); |
||||
addr[0] = 0x00300030; |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
addr = (vu_long*)(info->start[l_sect]); |
||||
while ((addr[0] & 0x00800080) != 0x00800080) { |
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
||||
puts ("Timeout\n"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
DONE: |
||||
/* reset to read mode */ |
||||
addr = (volatile unsigned long *)info->start[0]; |
||||
addr[0] = 0x00F000F0; /* reset bank */ |
||||
|
||||
puts (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
vu_long *addr = (vu_long*)(info->start[0]); |
||||
ulong start; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((vu_long *)dest) & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0x00AA00AA; |
||||
addr[0x02AA] = 0x00550055; |
||||
addr[0x0555] = 0x00A000A0; |
||||
|
||||
*((vu_long *)dest) = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { |
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
@ -1,87 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000-2010 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
|
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
||||
|
||||
. = env_offset; |
||||
common/env_embedded.o (.ppcenv) |
||||
|
||||
*(.text*) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
_GOT2_TABLE_ = .; |
||||
KEEP(*(.got2)) |
||||
KEEP(*(.got)) |
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
||||
_FIXUP_TABLE_ = .; |
||||
KEEP(*(.fixup)) |
||||
} |
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data*) |
||||
*(.sdata*) |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
. = ALIGN(4); |
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -1,52 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#define VIDEO_ENCODER_NAME "Analog Devices AD7179" |
||||
|
||||
#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */ |
||||
#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ |
||||
|
||||
#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ |
||||
#undef VIDEO_MODE_RGB |
||||
#define VIDEO_MODE_BPP 16 |
||||
|
||||
#ifdef VIDEO_MODE_PAL |
||||
#define VIDEO_ACTIVE_COLS 720 |
||||
#define VIDEO_ACTIVE_ROWS 576 |
||||
#define VIDEO_VISIBLE_COLS 640 |
||||
#define VIDEO_VISIBLE_ROWS 480 |
||||
#else |
||||
#error "NTSC mode is not supported" |
||||
#endif |
||||
|
||||
static unsigned char video_encoder_data[] = { |
||||
0x05, /* Mode Register 0 */ |
||||
0x11, /* Mode Register 1 */ |
||||
0x20, /* Mode Register 2 */ |
||||
0x0C, /* Mode Register 3 */ |
||||
0x01, /* Mode Register 4 */ |
||||
0x00, /* Reserved */ |
||||
0x00, /* Reserved */ |
||||
0x04, /* Timing Register 0 */ |
||||
0x00, /* Timing Register 1 */ |
||||
0xCB, /* Subcarrier Frequency Register 0 */ |
||||
0x0A, /* Subcarrier Frequency Register 1 */ |
||||
0x09, /* Subcarrier Frequency Register 2 */ |
||||
0x2A, /* Subcarrier Frequency Register 3 */ |
||||
0x00, /* Subcarrier Phase */ |
||||
0x00, /* Closed Captioning Ext Reg 0 */ |
||||
0x00, /* Closed Captioning Ext Reg 1 */ |
||||
0x00, /* Closed Captioning Reg 0 */ |
||||
0x00, /* Closed Captioning Reg 1 */ |
||||
0x00, /* Pedestal Control Reg 0 */ |
||||
0x00, /* Pedestal Control Reg 1 */ |
||||
0x00, /* Pedestal Control Reg 2 */ |
||||
0x00, /* Pedestal Control Reg 3 */ |
||||
0x00, /* CGMS_WSS Reg 0 */ |
||||
0x00, /* CGMS_WSS Reg 0 */ |
||||
0x00, /* CGMS_WSS Reg 0 */ |
||||
0x00 /* Teletext Req. Control Reg */ |
||||
} ; |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01" |
||||
CONFIG_PPC=y |
||||
CONFIG_8xx=y |
||||
CONFIG_TARGET_RRVISION=y |
@ -1,3 +0,0 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_8xx=y |
||||
CONFIG_TARGET_RRVISION=y |
@ -1,450 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000, 2001, 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
||||
#define CONFIG_RRVISION 1 /* ...on a RRvision board */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000 |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ 64000000 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "setenv stdout serial" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_ETHADDR 00:50:C2:00:E0:70 |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 |
||||
#define CONFIG_IPADDR 10.0.0.5 |
||||
#define CONFIG_SERVERIP 10.0.0.2 |
||||
#define CONFIG_NETMASK 255.0.0.0 |
||||
#define CONFIG_ROOTPATH "/opt/eldk/ppc_8xx" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \
|
||||
":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"load=tftp 100000 /tftpboot/u-boot.bin\0" \
|
||||
"update=protect off 1:0-8;era 1:0-8;" \
|
||||
"cp.b 100000 40000000 ${filesize};" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"kernel_addr=40040000\0" \
|
||||
"ramdisk_addr=40100000\0" \
|
||||
"kernel_img=/tftpboot/uImage\0" \
|
||||
"kernel_load=tftp 200000 ${kernel_img}\0" \
|
||||
"net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
|
||||
"flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" |
||||
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#undef CONFIG_STATUS_LED /* disturbs display */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
|
||||
#ifdef CONFIG_LCD |
||||
#define CONFIG_MPC8XX_LCD |
||||
#else |
||||
#define CONFIG_VIDEO 1 /* To enable the video initialization */ |
||||
|
||||
/* Video related */ |
||||
#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ |
||||
#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */ |
||||
#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */ |
||||
#endif |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL 0x00000020 /* PB 26 */ |
||||
#define PB_SDA 0x00000010 /* PB 27 */ |
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
||||
#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */ |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_DATE |
||||
|
||||
#undef CONFIG_CMD_PCMCIA |
||||
#undef CONFIG_CMD_IDE |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000 |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
||||
|
||||
/* timeout values are in ticks = ms */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (120*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (1 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
*/ |
||||
|
||||
/* for 64 MHz, we use a 16 MHz clock * 4 */ |
||||
#define CONFIG_SYS_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_RTSEL | SCCR_RTDIV | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CONFIG_SYS_DER 0x2002000F*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: |
||||
*/ |
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI) |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
||||
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
||||
#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
||||
#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
||||
#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) |
||||
#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ |
||||
BR_PS_8 | BR_MS_UPMB | BR_V ) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
* |
||||
* The Divider for PTA (refresh timer) configuration is based on an |
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to |
||||
* the number of chip selects (NCS) and the actually needed refresh |
||||
* rate is done by setting MPTPR. |
||||
* |
||||
* PTA is calculated from |
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
||||
* |
||||
* gclk CPU clock (not bus clock!) |
||||
* Trefresh Refresh cycle * 4 (four word bursts used) |
||||
* |
||||
* 4096 Rows from SDRAM example configuration |
||||
* 1000 factor s -> ms |
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
||||
* 4 Number of refresh cycles per period |
||||
* 64 Refresh cycle in ms per number of rows |
||||
* -------------------------------------------- |
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
||||
* |
||||
* 50 MHz => 50.000.000 / Divider = 98 |
||||
* 66 Mhz => 66.000.000 / Divider = 129 |
||||
* 80 Mhz => 80.000.000 / Divider = 156 |
||||
*/ |
||||
#define CONFIG_SYS_MAMR_PTA 129 |
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us |
||||
* (= 64 ms / 2K = 125 / quad bursts). |
||||
* For a simpler initialization, 15.6 us is used instead. |
||||
* |
||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
||||
*/ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
@ -1,89 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _VIDEO_AD7176_H_ |
||||
#define _VIDEO_AD7176_H_ |
||||
|
||||
#define VIDEO_ENCODER_NAME "Analog Devices AD7176" |
||||
|
||||
#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */ |
||||
#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ |
||||
|
||||
#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ |
||||
#undef VIDEO_MODE_RGB |
||||
#define VIDEO_MODE_BPP 16 |
||||
|
||||
#ifdef VIDEO_MODE_PAL |
||||
#define VIDEO_ACTIVE_COLS 720 |
||||
#define VIDEO_ACTIVE_ROWS 576 |
||||
#define VIDEO_VISIBLE_COLS 640 |
||||
#define VIDEO_VISIBLE_ROWS 480 |
||||
#endif |
||||
|
||||
#ifdef VIDEO_MODE_NTSC |
||||
#define VIDEO_ACTIVE_COLS 720 |
||||
#define VIDEO_ACTIVE_ROWS 525 |
||||
#define VIDEO_VISIBLE_COLS 640 |
||||
#define VIDEO_VISIBLE_ROWS 400 |
||||
#endif |
||||
|
||||
static unsigned char video_encoder_data[] = { |
||||
#ifdef VIDEO_MODE_NTSC |
||||
0x04, /* Mode Register 0 */ |
||||
#ifdef VIDEO_DEBUG_COLORBARS |
||||
0x82, |
||||
#else |
||||
0x02, /* Mode Register 1 */ |
||||
#endif /* VIDEO_DEBUG_COLORBARS */ |
||||
0x16, /* Subcarrier Freq 0 */ |
||||
0x7c, /* Subcarrier Freq 1 */ |
||||
0xf0, /* Subcarrier Freq 2 */ |
||||
0x21, /* Subcarrier Freq 3 */ |
||||
0x00, /* Subcarrier phase */ |
||||
0x02, /* Timing Register 0 */ |
||||
0x00, /* Extended Captioning 0 */ |
||||
0x00, /* Extended Captioning 1 */ |
||||
0x00, /* Closed Captioning 0 */ |
||||
0x00, /* Closed Captioning 1 */ |
||||
0x00, /* Timing Register 1 */ |
||||
0x08, /* Mode Register 2 */ |
||||
0x00, /* Pedestal Register 0 */ |
||||
0x00, /* Pedestal Register 1 */ |
||||
0x00, /* Pedestal Register 2 */ |
||||
0x00, /* Pedestal Register 3 */ |
||||
0x00 /* Mode Register 3 */ |
||||
|
||||
#endif /* VIDEO_MODE_NTSC */ |
||||
|
||||
#ifdef VIDEO_MODE_PAL |
||||
0x05, /* Mode Register 0 */ |
||||
#ifdef VIDEO_DEBUG_COLORBARS |
||||
0x82, |
||||
#else |
||||
0x02, /* Mode Register 1 (2) */ |
||||
#endif /* VIDEO_DEBUG_COLORBARS */ |
||||
0xcb, /* Subcarrier Freq 0 */ |
||||
0x8a, /* Subcarrier Freq 1 */ |
||||
0x09, /* Subcarrier Freq 2 */ |
||||
0x2a, /* Subcarrier Freq 3 */ |
||||
0x00, /* Subcarrier phase */ |
||||
0x0a, /* Timing Register 0 (a) */ |
||||
0x00, /* Extended Captioning 0 */ |
||||
0x00, /* Extended Captioning 1 */ |
||||
0x00, /* Closed Captioning 0 */ |
||||
0x00, /* Closed Captioning 1 */ |
||||
0x00, /* Timing Register 1 */ |
||||
0x08, /* Mode Register 2 (8) */ |
||||
0x00, /* Pedestal Register 0 */ |
||||
0x00, /* Pedestal Register 1 */ |
||||
0x00, /* Pedestal Register 2 */ |
||||
0x00, /* Pedestal Register 3 */ |
||||
0x00 /* Mode Register 3 */ |
||||
#endif /* VIDEO_MODE_PAL */ |
||||
} ; |
||||
|
||||
#endif /* _VIDEO_AD7176_H_ */ |
@ -1,133 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _VIDEO_AD7177_H_ |
||||
#define _VIDEO_AD7177_H_ |
||||
|
||||
/* #define VIDEO_DEBUG_DISABLE_COLORS 0 */ |
||||
|
||||
#define VIDEO_ENCODER_NAME "Analog Devices AD7177" |
||||
|
||||
#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */ |
||||
#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ |
||||
|
||||
#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ |
||||
#undef VIDEO_MODE_RGB |
||||
#define VIDEO_MODE_BPP 16 |
||||
|
||||
#ifdef VIDEO_MODE_PAL |
||||
#define VIDEO_ACTIVE_COLS 720 |
||||
#define VIDEO_ACTIVE_ROWS 576 |
||||
#define VIDEO_VISIBLE_COLS 640 |
||||
#define VIDEO_VISIBLE_ROWS 480 |
||||
#endif |
||||
|
||||
#ifdef VIDEO_MODE_NTSC |
||||
#define VIDEO_ACTIVE_COLS 720 |
||||
#define VIDEO_ACTIVE_ROWS 525 |
||||
#define VIDEO_VISIBLE_COLS 640 |
||||
#define VIDEO_VISIBLE_ROWS 400 |
||||
#endif |
||||
|
||||
static unsigned char |
||||
video_encoder_data[] = { |
||||
#ifdef VIDEO_MODE_NTSC |
||||
0x04, /* Mode Register 0 */ |
||||
#ifdef VIDEO_DEBUG_COLORBARS |
||||
0xc2, |
||||
#else |
||||
0x42, /* Mode Register 1 */ |
||||
#endif /* VIDEO_DEBUG_COLORBARS */ |
||||
0x16, /* Subcarrier Freq 0 */ |
||||
0x7c, /* Subcarrier Freq 1 */ |
||||
0xf0, /* Subcarrier Freq 2 */ |
||||
0x21, /* Subcarrier Freq 3 */ |
||||
0x00, /* Subcarrier phase */ |
||||
0x02, /* Timing Register 0 */ |
||||
0x00, /* Extended Captioning 0 */ |
||||
0x00, /* Extended Captioning 1 */ |
||||
0x00, /* Closed Captioning 0 */ |
||||
0x00, /* Closed Captioning 1 */ |
||||
0x00, /* Timing Register 1 */ |
||||
0x08, /* Mode Register 2 */ |
||||
0x00, /* Pedestal Register 0 */ |
||||
0x00, /* Pedestal Register 1 */ |
||||
0x00, /* Pedestal Register 2 */ |
||||
0x00, /* Pedestal Register 3 */ |
||||
0x08, /* Mode Register 3 */ |
||||
|
||||
#endif /* VIDEO_MODE_NTSC */ |
||||
|
||||
#ifdef VIDEO_MODE_PAL |
||||
#ifdef VIDEO_MODE_RGB_OUT |
||||
|
||||
0x69, /* Mode Register 0 */ |
||||
#ifdef VIDEO_DEBUG_COLORBARS |
||||
0xc0, /* Mode Register 1 (c0) */ |
||||
#else |
||||
0x40, /* Mode Register 1 (c0) */ |
||||
#endif /* VIDEO_DEBUG_COLORBARS */ |
||||
0xcb, /* Subcarrier Freq 0 */ |
||||
0x8a, /* Subcarrier Freq 1 */ |
||||
0x09, /* Subcarrier Freq 2 */ |
||||
0x2a, /* Subcarrier Freq 3 */ |
||||
0x00, /* Subcarrier phase */ |
||||
0x02, /* Timing Register 0 */ |
||||
0x00, /* Extended Captioning 0 */ |
||||
0x00, /* Extended Captioning 1 */ |
||||
0x00, /* Closed Captioning 0 */ |
||||
0x00, /* Closed Captioning 1 */ |
||||
0x00, /* Timing Register 1 */ |
||||
0x28, /* Mode Register 2 */ |
||||
0x00, /* Pedestal Register 0 */ |
||||
0x00, /* Pedestal Register 1 */ |
||||
0x00, /* Pedestal Register 2 */ |
||||
0x00, /* Pedestal Register 3 */ |
||||
0x08, /* Mode Register 3 */ |
||||
|
||||
#else /* ! VIDEO_MODE_RGB_OUT */ |
||||
|
||||
0x09, /* Mode Register 0 (was 01) */ |
||||
#ifdef VIDEO_DEBUG_COLORBARS |
||||
0xd8, /* */ |
||||
#else |
||||
0x59, /* Mode Register 1 (was 58) */ |
||||
#endif /* VIDEO_DEBUG_COLORBARS */ |
||||
0xcb, /* Subcarrier Freq 0 */ |
||||
0x8a, /* Subcarrier Freq 1 */ |
||||
0x09, /* Subcarrier Freq 2 */ |
||||
0x2a, /* Subcarrier Freq 3 */ |
||||
0x00, /* Subcarrier phase */ |
||||
0x02, /* Timing Register 0 (was a) */ |
||||
0x00, /* Extended Captioning 0 */ |
||||
0x00, /* Extended Captioning 1 */ |
||||
0x00, /* Closed Captioning 0 */ |
||||
0x00, /* Closed Captioning 1 */ |
||||
0x00, /* Timing Register 1 */ |
||||
#ifdef VIDEO_DEBUG_LOWPOWER |
||||
#ifdef VIDEO_DEBUG_DISABLE_COLORS |
||||
0x98, /* Mode Register 2 */ |
||||
#else |
||||
0x88, /* Mode Register 2 */ |
||||
#endif /* VIDEO_DEBUG_DISABLE_COLORS */ |
||||
#else /* ! VIDEO_DEBUG_LOWPOWER */ |
||||
#ifdef VIDEO_DEBUG_DISABLE_COLORS |
||||
0x18, /* Mode Register 2 */ |
||||
#else |
||||
0x08, /* Mode Register 2 */ |
||||
#endif /* VIDEO_DEBUG_DISABLE_COLORS */ |
||||
#endif /* VIDEO_DEBUG_LOWPOWER */ |
||||
0x00, /* Pedestal Register 0 */ |
||||
0x00, /* Pedestal Register 1 */ |
||||
0x00, /* Pedestal Register 2 */ |
||||
0x00, /* Pedestal Register 3 */ |
||||
0x08 /* Mode Register 3 */ |
||||
#endif /* VIDEO_MODE_RGB_OUT */ |
||||
#endif /* VIDEO_MODE_PAL */ |
||||
} ; |
||||
|
||||
#endif /* _VIDEO_AD7177_H_ */ |
@ -1,20 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _VIDEO_AD7179_H_ |
||||
#define _VIDEO_AD7179_H_ |
||||
|
||||
/*
|
||||
* The video encoder data are board specific now! |
||||
*/ |
||||
|
||||
#if defined(CONFIG_RRVISION) |
||||
#include "../board/RRvision/video_ad7179.h" |
||||
#else |
||||
#error "Please provide a board-specific video_ad7179.h" |
||||
#endif |
||||
|
||||
#endif /* _VIDEO_AD7179_H_ */ |
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Reference in new issue