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@ -266,7 +266,7 @@ int serial_tstc () |
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/*****************************************************************************/ |
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) |
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP) |
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#if defined(CONFIG_440) |
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#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 |
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@ -274,13 +274,34 @@ int serial_tstc () |
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#define CR0_MASK 0x3fff0000 |
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#define CR0_EXTCLK_ENA 0x00600000 |
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#define CR0_UDIV_POS 16 |
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#else |
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#define UART_BASE_PTR 0xF800FFFC; /* pointer to uart base */ |
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#elif defined(CONFIG_405EP) |
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#define UART0_BASE 0xef600300 |
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#define UART1_BASE 0xef600400 |
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#define UCR0_MASK 0x0000007f |
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#define UCR1_MASK 0x00007f00 |
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#define UCR0_UDIV_POS 0 |
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#define UCR1_UDIV_POS 8 |
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#define UDIV_MAX 127 |
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#else /* CONFIG_405GP || CONFIG_405CR */ |
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#define UART0_BASE 0xef600300 |
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#define UART1_BASE 0xef600400 |
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#define CR0_MASK 0x00001fff |
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#define CR0_EXTCLK_ENA 0x000000c0 |
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#define CR0_UDIV_POS 1 |
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#define UDIV_MAX 32 |
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#endif |
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/* using serial port 0 or 1 as U-Boot console ? */ |
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#if defined(CONFIG_UART1_CONSOLE) |
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#define ACTING_UART0_BASE UART1_BASE |
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#define ACTING_UART1_BASE UART0_BASE |
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#else |
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#define ACTING_UART0_BASE UART0_BASE |
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#define ACTING_UART1_BASE UART1_BASE |
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#endif |
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#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) |
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#error "External serial clock not supported on IBM PPC405EP!" |
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#endif |
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#define UART_RBR 0x00 |
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@ -299,7 +320,7 @@ int serial_tstc () |
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/*-----------------------------------------------------------------------------+
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| Line Status Register. |
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+-----------------------------------------------------------------------------*/ |
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/*#define asyncLSRport1 UART0_BASE+0x05 */ |
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/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */ |
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#define asyncLSRDataReady1 0x01 |
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#define asyncLSROverrunError1 0x02 |
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#define asyncLSRParityError1 0x04 |
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@ -312,8 +333,8 @@ int serial_tstc () |
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/*-----------------------------------------------------------------------------+
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| Miscellanies defines. |
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+-----------------------------------------------------------------------------*/ |
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/*#define asyncTxBufferport1 UART0_BASE+0x00 */ |
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/*#define asyncRxBufferport1 UART0_BASE+0x00 */ |
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/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ |
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/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ |
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#if CONFIG_SERIAL_SOFTWARE_FIFO |
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@ -412,16 +433,16 @@ int serial_init (void) |
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reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ |
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mtdcr (cntrl0, reg); |
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out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ |
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out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ |
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out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ |
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out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ |
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out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ |
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out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ |
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val = in8 (UART0_BASE + UART_LSR); /* clear line status */ |
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val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */ |
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out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ |
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out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ |
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out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ |
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out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ |
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out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ |
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out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ |
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out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ |
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out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ |
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val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ |
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val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ |
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out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ |
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out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ |
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return (0); |
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} |
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@ -439,6 +460,17 @@ int serial_init (void) |
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unsigned short bdiv; |
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volatile char val; |
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#ifdef CONFIG_405EP |
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reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); |
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clk = gd->cpu_clk; |
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tmp = CFG_BASE_BAUD * 16; |
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udiv = (clk + tmp / 2) / tmp; |
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if (udiv > UDIV_MAX) /* max. n bits for udiv */ |
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udiv = UDIV_MAX; |
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reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ |
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reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ |
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mtdcr (cpc0_ucr, reg); |
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#else /* CONFIG_405EP */ |
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reg = mfdcr(cntrl0) & ~CR0_MASK; |
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#ifdef CFG_EXT_SERIAL_CLOCK |
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clk = CFG_EXT_SERIAL_CLOCK; |
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@ -451,27 +483,27 @@ int serial_init (void) |
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#else |
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tmp = CFG_BASE_BAUD * 16; |
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udiv = (clk + tmp / 2) / tmp; |
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if (udiv > 32) /* max. 5 bits for udiv */ |
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udiv = 32; |
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if (udiv > UDIV_MAX) /* max. n bits for udiv */ |
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udiv = UDIV_MAX; |
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#endif |
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#endif |
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reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ |
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mtdcr (cntrl0, reg); |
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#endif /* CONFIG_405EP */ |
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tmp = gd->baudrate * udiv * 16; |
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bdiv = (clk + tmp / 2) / tmp; |
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out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ |
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out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ |
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out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ |
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out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ |
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out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ |
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out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ |
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val = in8 (UART0_BASE + UART_LSR); /* clear line status */ |
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val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */ |
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out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ |
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out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ |
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out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ |
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out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ |
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out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ |
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out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ |
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out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ |
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out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ |
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val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ |
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val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ |
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out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ |
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out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ |
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return (0); |
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} |
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@ -492,14 +524,19 @@ void serial_setbrg (void) |
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#else |
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clk = gd->cpu_clk; |
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#endif |
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#ifdef CONFIG_405EP |
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udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS); |
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#else |
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udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1; |
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#endif /* CONFIG_405EP */ |
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tmp = gd->baudrate * udiv * 16; |
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bdiv = (clk + tmp / 2) / tmp; |
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out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ |
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out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ |
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out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ |
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out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ |
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out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ |
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out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ |
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out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ |
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out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ |
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} |
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@ -512,11 +549,11 @@ void serial_putc (const char c) |
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/* check THRE bit, wait for transmiter available */ |
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for (i = 1; i < 3500; i++) { |
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if ((in8 (UART0_BASE + UART_LSR) & 0x20) == 0x20) |
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if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20) |
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break; |
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udelay (100); |
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} |
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out8 (UART0_BASE + UART_THR, c); /* put character out */ |
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out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */ |
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} |
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@ -536,7 +573,7 @@ int serial_getc () |
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#if defined(CONFIG_HW_WATCHDOG) |
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WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ |
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#endif /* CONFIG_HW_WATCHDOG */ |
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status = in8 (UART0_BASE + UART_LSR); |
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status = in8 (ACTING_UART0_BASE + UART_LSR); |
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if ((status & asyncLSRDataReady1) != 0x0) { |
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break; |
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} |
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@ -544,14 +581,14 @@ int serial_getc () |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1 )) != 0) { |
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out8 (UART0_BASE + UART_LSR, |
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out8 (ACTING_UART0_BASE + UART_LSR, |
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asyncLSRFramingError1 | |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1); |
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} |
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} |
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return (0x000000ff & (int) in8 (UART0_BASE)); |
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return (0x000000ff & (int) in8 (ACTING_UART0_BASE)); |
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} |
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@ -559,7 +596,7 @@ int serial_tstc () |
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{ |
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unsigned char status; |
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status = in8 (UART0_BASE + UART_LSR); |
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status = in8 (ACTING_UART0_BASE + UART_LSR); |
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if ((status & asyncLSRDataReady1) != 0x0) { |
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return (1); |
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} |
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@ -567,7 +604,7 @@ int serial_tstc () |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1 )) != 0) { |
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out8 (UART0_BASE + UART_LSR, |
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out8 (ACTING_UART0_BASE + UART_LSR, |
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asyncLSRFramingError1 | |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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@ -601,8 +638,8 @@ void serial_isr (void *arg) |
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rx_put = 0; |
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if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { |
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/* Stop flow by setting RTS inactive */ |
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out8 (UART0_BASE + UART_MCR, |
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in8 (UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); |
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out8 (ACTING_UART0_BASE + UART_MCR, |
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in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); |
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} |
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} |
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buf_info.rx_put = rx_put; |
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@ -615,7 +652,7 @@ void serial_buffered_init (void) |
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buf_info.rx_put = 0; |
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buf_info.rx_get = 0; |
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if (in8 (UART0_BASE + UART_MSR) & 0x10) { |
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if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) { |
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serial_puts ("Check CTS signal present on serial port: OK.\n"); |
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} else { |
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serial_puts ("WARNING: CTS signal not present on serial port.\n"); |
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@ -626,24 +663,24 @@ void serial_buffered_init (void) |
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(void *) &buf_info /*void *arg */ ); |
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/* Enable "RX Data Available" Interrupt on UART */ |
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/* out8(UART0_BASE + UART_IER, in8(UART0_BASE + UART_IER) |0x01); */ |
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out8 (UART0_BASE + UART_IER, 0x01); |
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/* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */ |
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out8 (ACTING_UART0_BASE + UART_IER, 0x01); |
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/* Set DTR active */ |
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out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x01); |
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out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01); |
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/* Start flow by setting RTS active */ |
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out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02); |
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out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); |
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/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ |
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out8 (UART0_BASE + UART_FCR, (1 << 6) | 1); |
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out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); |
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} |
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void serial_buffered_putc (const char c) |
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{ |
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/* Wait for CTS */ |
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#if defined(CONFIG_HW_WATCHDOG) |
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while (!(in8 (UART0_BASE + UART_MSR) & 0x10)) |
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while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) |
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WATCHDOG_RESET (); |
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#else |
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while (!(in8 (UART0_BASE + UART_MSR) & 0x10)); |
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while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); |
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#endif |
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serial_putc (c); |
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} |
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@ -679,7 +716,7 @@ int serial_buffered_getc (void) |
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} |
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if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { |
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/* Start flow by setting RTS active */ |
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out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02); |
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out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); |
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} |
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return c; |
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@ -716,16 +753,16 @@ void kgdb_serial_init (void) |
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/*
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* Init onboard 16550 UART |
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*/ |
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out8 (UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ |
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out8 (UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ |
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out8 (UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ |
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out8 (UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ |
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out8 (UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ |
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out8 (UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ |
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val = in8 (UART1_BASE + UART_LSR); /* clear line status */ |
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val = in8 (UART1_BASE + UART_RBR); /* read receive buffer */ |
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out8 (UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ |
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out8 (UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ |
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out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ |
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out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ |
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out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ |
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out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ |
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out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ |
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out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ |
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val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */ |
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val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ |
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out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ |
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out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ |
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} |
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@ -734,10 +771,10 @@ void putDebugChar (const char c) |
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if (c == '\n') |
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serial_putc ('\r'); |
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out8 (UART1_BASE + UART_THR, c); /* put character out */ |
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out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */ |
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/* check THRE bit, wait for transfer done */ |
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while ((in8 (UART1_BASE + UART_LSR) & 0x20) != 0x20); |
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while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); |
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} |
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@ -754,7 +791,7 @@ int getDebugChar (void) |
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unsigned char status = 0; |
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while (1) { |
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status = in8 (UART1_BASE + UART_LSR); |
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status = in8 (ACTING_UART1_BASE + UART_LSR); |
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if ((status & asyncLSRDataReady1) != 0x0) { |
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break; |
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} |
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@ -762,14 +799,14 @@ int getDebugChar (void) |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1 )) != 0) { |
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out8 (UART1_BASE + UART_LSR, |
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out8 (ACTING_UART1_BASE + UART_LSR, |
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asyncLSRFramingError1 | |
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asyncLSROverrunError1 | |
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asyncLSRParityError1 | |
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asyncLSRBreakInterrupt1); |
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} |
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} |
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return (0x000000ff & (int) in8 (UART1_BASE)); |
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return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); |
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} |
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