TI:am33xx: Create common config files for TI ARMv7 platforms, and AM33xx

We create two new files, include/configs/ti_armv7_common.h for all of
the common IP blocks and related features / commands we share in
virtually all of our platforms.  We then create
include/configs/ti_am335x_common.h for everything common to the am335x
SoC leaving just the board specific parts to
include/configs/ti_am335x_common.h.

Signed-off-by: Tom Rini <trini@ti.com>
master
Tom Rini 12 years ago
parent bc6fff9ac7
commit 8769455861
  1. 236
      include/configs/am335x_evm.h
  2. 60
      include/configs/ti_am335x_common.h
  3. 248
      include/configs/ti_armv7_common.h

@ -16,44 +16,20 @@
#ifndef __CONFIG_AM335X_EVM_H
#define __CONFIG_AM335X_EVM_H
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
#include <configs/ti_am335x_common.h>
#include <asm/arch/omap.h>
#define CONFIG_DMA_COHERENT
#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_NO_FLASH
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE (128 * 1024)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
/* Custom script for NOR */
#define CONFIG_SYS_LDSCRIPT "board/ti/am335x/u-boot.lds"
#define CONFIG_SYS_CACHELINE_SIZE 64
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_VERSION_VARIABLE
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
#ifdef CONFIG_NAND
#define NANDARGS \
@ -76,10 +52,8 @@
#define NANDARGS ""
#endif
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 1
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
@ -197,60 +171,11 @@
"run mmcboot;" \
"run nandboot;"
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_CMD_ECHO
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 64
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 512
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* memtest works on 8 MB in DRAM after skipping 32MB from
* start addr of ram disk
*/
#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ (8 * 1024 * 1024))
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_SPI
#define CONFIG_OMAP3_SPI
#define CONFIG_MTD_DEVICE
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED (24000000)
/* USB Composite download gadget - g_dnl */
#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
/* USB TI's IDs */
#define CONFIG_USBD_HS
#define CONFIG_G_DNL_VENDOR_NUM 0x0403
#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
@ -284,109 +209,24 @@
"rootfs part 0 9"
#endif
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000 /* 1ms clock */
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#define CONFIG_BAUDRATE 115200
/* I2C Configuration */
#define CONFIG_I2C
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_DRIVER_OMAP24XX_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_OMAP_GPIO
#define CONFIG_BAUDRATE 115200
/* CPU */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SPL */
#ifndef CONFIG_NOR_BOOT
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
/*
* Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
* rest of the space for stack.
*/
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_OS_BOOT
#define CONFIG_SPL_BSS_START_ADDR 0x80a00000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#ifdef CONFIG_SPL_OS_BOOT
/* fat */
#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_DRAM_1 + 0x100)
/* raw mmc */
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
/* nand */
#ifdef CONFIG_NAND
#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
#endif
/* spl export command */
#define CONFIG_CMD_SPL
#endif
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
@ -401,14 +241,7 @@
#define CONFIG_SPL_MUSB_NEW_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
@ -428,30 +261,16 @@
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif
#endif
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
* header. That is 0x800FFFC0--0x80100000 should not be used for any
* other needs.
* For NOR boot, we must set this to the start of where NOR is mapped
* in memory.
*/
#ifdef CONFIG_NOR_BOOT
#define CONFIG_SYS_TEXT_BASE 0x08000000
#else
#define CONFIG_SYS_TEXT_BASE 0x80800000
#endif
#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
/* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/*
@ -506,7 +325,6 @@
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nor0=m25p80-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \
"512k(u-boot),128k(u-boot-env1)," \
@ -519,22 +337,13 @@
#define CONFIG_SYS_MMC_ENV_PART 2
#endif
/* Unsupported features */
#undef CONFIG_USE_IRQ
/* SPI flash. */
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_NET_MULTI
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
@ -543,14 +352,7 @@
/* NAND support */
#ifdef CONFIG_NAND
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
devices */
#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
@ -579,6 +381,7 @@
*/
#if defined(CONFIG_NOR)
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_FLASH
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_CFI
@ -594,7 +397,6 @@
#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
"512k(u-boot)," \
@ -602,8 +404,6 @@
"128k(u-boot-env2)," \
"4m(kernel),-(rootfs)"
#endif
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_FLASH
#endif /* NOR support */
#endif /* ! __CONFIG_AM335X_EVM_H */

@ -0,0 +1,60 @@
/*
* ti_am335x_common.h
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*
* For more details, please see the technical documents listed at
* http://www.ti.com/product/am3359#technicaldocuments
*/
#ifndef __CONFIG_TI_AM335X_COMMON_H__
#define __CONFIG_TI_AM335X_COMMON_H__
#define CONFIG_AM33XX
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000
/* Network defines. */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_YMODEM_SUPPORT
/*
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/* Now bring in the rest of the common code. */
#include <configs/ti_armv7_common.h>
#endif /* __CONFIG_TI_AM335X_COMMON_H__ */

@ -0,0 +1,248 @@
/*
* ti_armv7_common.h
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*
* The various ARMv7 SoCs from TI all share a number of IP blocks when
* implementing a given feature. Rather than define these in every
* board or even SoC common file, we define a common file to be re-used
* in all cases. While technically true that some of these details are
* configurable at the board design, they are common throughout SoC
* reference platforms as well as custom designs and become de facto
* standards.
*/
#ifndef __CONFIG_TI_ARMV7_COMMON_H__
#define __CONFIG_TI_ARMV7_COMMON_H__
/* Common define for many platforms. */
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
/*
* We typically do not contain NOR flash. In the cases where we do, we
* undefine this later.
*/
#define CONFIG_SYS_NO_FLASH
/* Support both device trees and ATAGs. */
#define CONFIG_OF_LIBFDT
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*
* Our DDR memory always starts at 0x80000000 and U-Boot shall have
* relocated itself to higher in memory by the time this value is used.
*/
#define CONFIG_SYS_LOAD_ADDR 0x80000000
/*
* Default to a quick boot delay.
*/
#define CONFIG_BOOTDELAY 1
/*
* DDR information. We say (for simplicity) that we have 1 bank,
* always, even when we have more. We always start at 0x80000000,
* and we place the initial stack pointer in our SRAM.
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
/* Timer information. */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000 /* 1ms clock */
/* I2C IP block */
#define CONFIG_I2C
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_DRIVER_OMAP24XX_I2C
/* MMC/SD IP block */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_CMD_MMC
/* McSPI IP block */
#define CONFIG_SPI
#define CONFIG_OMAP3_SPI
/* GPIO block */
#define CONFIG_OMAP_GPIO
/*
* GPMC NAND block. We support 1 device and the physical address to
* access CS0 at is 0x8000000.
*/
#ifdef CONFIG_NAND
#define CONFIG_CMD_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_BASE 0x8000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
/*
* The following are general good-enough settings for U-Boot. We set a
* large malloc pool as we generally have a lot of DDR, and we opt for
* function over binary size in the main portion of U-Boot as this is
* generally easily constrained later if needed. We enable the config
* options that give us information in the environment about what board
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_VERSION_VARIABLE
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_BAUDRATE 115200
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 64
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 512
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/*
* When we have SPI, NOR or NAND flash we expect to be making use of
* mtdparts, both for ease of use in U-Boot and for passing information
* on to the Linux kernel.
*/
#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND)
#define CONFIG_MTD_DEVICE /* Required for mtdparts */
#define CONFIG_CMD_MTDPARTS
#endif
/*
* For commands to use, we take the default list and add a few other
* useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
* prior to this include, in order to skip a few commands. When we do
* have flash, if we expect these commands they must be enabled in that
* config.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_BOOTZ
/*
* Common filesystems support. When we have removable storage we
* enabled a number of useful commands and support.
*/
#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FS_GENERIC
#endif
/*
* Our platforms make use of SPL to initalize the hardware (primarily
* memory) enough for full U-Boot to be loaded. We also support Falcon
* Mode so that the Linux kernel can be booted directly from SPL
* instead, if desired. We make use of the general SPL framework found
* under common/spl/. Given our generally common memory map, we set a
* number of related defaults and sizes here.
*/
#ifndef CONFIG_NOR_BOOT
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_OS_BOOT
/*
* Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
* rest of the space for stack. We load U-Boot itself into memory at
* 0x80800000 for legacy reasons (to not conflict with older SPLs). We
* have our BSS be placed 1MiB after this, to allow for the default
* Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
* We have the SPL malloc pool at the end of the BSS area.
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_SPL_BSS_START_ADDR 0x80a00000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
/* FAT sd card locations. */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
/* FAT */
#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
/* RAW SD card / eMMC */
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
/* NAND */
#ifdef CONFIG_NAND
#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
#endif
/* spl export command */
#define CONFIG_CMD_SPL
#endif
#ifdef CONFIG_MMC
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#endif
/* General parts of the framework. */
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif
#endif /* !CONFIG_NOR_BOOT */
#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */
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