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@ -16,7 +16,7 @@ |
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#define CONFIG_SYS_CLK_FREQ 750000000 |
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#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ |
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/* dwgmac doesn't work with D$ enabled now */ |
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/* NAND controller DMA doesn't work correctly with D$ enabled */ |
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#define CONFIG_SYS_DCACHE_OFF |
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/*
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@ -40,7 +40,7 @@ |
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 |
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ |
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */ |
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#define CONFIG_SYS_INIT_SP_ADDR \ |
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) |
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@ -103,7 +103,7 @@ |
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64 |
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/*
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* SD/MMC configuration |
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