- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006master
Stefan Roese
19 years ago
parent
0dab03ba8f
commit
887e2ec9ec
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#
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# (C) Copyright 2002-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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include $(TOPDIR)/include/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o sdram.o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,41 @@ |
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#
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# (C) Copyright 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# AMCC 440EPx Reference Platform (Sequoia) board
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#
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sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp |
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ifndef TEXT_BASE |
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TEXT_BASE = 0xFFFA0000
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endif |
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
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endif |
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@ -0,0 +1,157 @@ |
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/* |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <ppc_asm.tmpl> |
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#include <config.h> |
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/* General */ |
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#define TLB_VALID 0x00000200 |
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#define _256M 0x10000000 |
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/* Supported page sizes */ |
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#define SZ_1K 0x00000000 |
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#define SZ_4K 0x00000010 |
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#define SZ_16K 0x00000020 |
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#define SZ_64K 0x00000030 |
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#define SZ_256K 0x00000040 |
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#define SZ_1M 0x00000050 |
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#define SZ_8M 0x00000060 |
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#define SZ_16M 0x00000070 |
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#define SZ_256M 0x00000090 |
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/* Storage attributes */ |
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#define SA_W 0x00000800 /* Write-through */ |
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#define SA_I 0x00000400 /* Caching inhibited */ |
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#define SA_M 0x00000200 /* Memory coherence */ |
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#define SA_G 0x00000100 /* Guarded */ |
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#define SA_E 0x00000080 /* Endian */ |
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/* Access control */ |
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#define AC_X 0x00000024 /* Execute */ |
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#define AC_W 0x00000012 /* Write */ |
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#define AC_R 0x00000009 /* Read */ |
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/* Some handy macros */ |
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#define EPN(e) ((e) & 0xfffffc00) |
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#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) |
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#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) |
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#define TLB2(a) ( (a)&0x00000fbf ) |
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#define tlbtab_start\ |
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mflr r1 ;\
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bl 0f ;
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#define tlbtab_end\ |
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.long 0, 0, 0 ; \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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#define tlbentry(epn,sz,rpn,erpn,attr)\ |
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.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) |
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/************************************************************************** |
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* TLB TABLE |
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* |
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* This table is used by the cpu boot code to setup the initial tlb |
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* entries. Rather than make broad assumptions in the cpu source tree, |
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* this table lets each board set things up however they like. |
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* |
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* Pointer to the table is returned in r1 |
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* |
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*************************************************************************/ |
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.section .bootpg,"ax" |
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.globl tlbtab
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tlbtab: |
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tlbtab_start |
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/* |
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the |
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* speed up boot process. It is patched after relocation to enable SA_I |
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*/ |
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#ifndef CONFIG_NAND_SPL |
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tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) |
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#else |
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tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) |
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#endif |
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/* TLB-entry for DDR SDRAM (Up to 2GB) */ |
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tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
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#ifdef CFG_INIT_RAM_DCACHE |
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
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tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) |
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#endif |
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/* TLB-entry for PCI Memory */ |
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tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) |
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tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) |
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tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) |
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tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) |
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/* TLB-entry for EBC */ |
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tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
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/* TLB-entry for NAND */ |
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tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
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/* TLB-entry for Internal Registers & OCM */ |
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tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) |
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/*TLB-entry PCI registers*/ |
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tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
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/* TLB-entry for peripherals */ |
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tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) |
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tlbtab_end |
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#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
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/* |
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* For NAND booting the first TLB has to be reconfigured to full size |
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* and with caching disabled after running from RAM! |
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*/ |
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#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) |
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#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) |
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#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) |
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.globl reconfig_tlb0
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reconfig_tlb0: |
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sync |
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isync |
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addi r4,r0,0x0000 /* TLB entry #0 */ |
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lis r5,TLB00@h
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ori r5,r5,TLB00@l
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tlbwe r5,r4,0x0000 /* Save it out */ |
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lis r5,TLB01@h
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ori r5,r5,TLB01@l
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tlbwe r5,r4,0x0001 /* Save it out */ |
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lis r5,TLB02@h
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ori r5,r5,TLB02@l
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tlbwe r5,r4,0x0002 /* Save it out */ |
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sync |
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isync |
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blr |
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#endif |
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@ -0,0 +1,83 @@ |
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/*
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* (C) Copyright 2006 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#include <ppc440.h> |
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/*************************************************************************
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* |
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* initdram -- 440EPx's DDR controller is a DENALI Core |
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* |
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************************************************************************/ |
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long int initdram (int board_type) |
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{ |
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
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volatile ulong val; |
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mtsdram(DDR0_02, 0x00000000); |
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/*
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* Soft-reset SDRAM controller |
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*/ |
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mtsdr(sdr_srst, SDR0_SRST0_DMC); |
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mtsdr(sdr_srst, 0x00000000); |
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mtsdram(DDR0_00, 0x0000190A); |
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mtsdram(DDR0_01, 0x01000000); |
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mtsdram(DDR0_03, 0x02030602); |
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mtsdram(DDR0_04, 0x13030300); |
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mtsdram(DDR0_05, 0x0202050E); |
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mtsdram(DDR0_06, 0x0104C823); |
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mtsdram(DDR0_07, 0x000D0100); |
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mtsdram(DDR0_08, 0x02360001); |
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mtsdram(DDR0_09, 0x00011D5F); |
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mtsdram(DDR0_10, 0x00000300); |
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mtsdram(DDR0_11, 0x0027C800); |
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mtsdram(DDR0_12, 0x00000003); |
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mtsdram(DDR0_14, 0x00000000); |
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mtsdram(DDR0_17, 0x19000000); |
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mtsdram(DDR0_18, 0x19191919); |
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mtsdram(DDR0_19, 0x19191919); |
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mtsdram(DDR0_20, 0x0B0B0B0B); |
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mtsdram(DDR0_21, 0x0B0B0B0B); |
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mtsdram(DDR0_22, 0x00267F0B); |
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mtsdram(DDR0_23, 0x00000000); |
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mtsdram(DDR0_24, 0x01010002); |
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mtsdram(DDR0_26, 0x5B260181); |
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mtsdram(DDR0_27, 0x0000682B); |
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mtsdram(DDR0_28, 0x00000000); |
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mtsdram(DDR0_31, 0x00000000); |
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mtsdram(DDR0_42, 0x01000006); |
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mtsdram(DDR0_43, 0x050A0200); |
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mtsdram(DDR0_44, 0x00000005); |
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mtsdram(DDR0_02, 0x00000001); |
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/*
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* Wait for DCC master delay line to finish calibration |
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*/ |
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mfsdram(DDR0_17, val); |
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while (((val >> 8) & 0x000007f) == 0) { |
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mfsdram(DDR0_17, val); |
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} |
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#endif /* #ifndef CONFIG_NAND_U_BOOT */ |
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return (CFG_MBYTES_SDRAM << 20); |
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} |
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@ -0,0 +1,552 @@ |
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/*
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* (C) Copyright 2006 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* (C) Copyright 2006 |
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com |
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#include <ppc440.h> |
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#include "sequoia.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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int board_early_init_f(void) |
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{ |
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unsigned long sdr0_cust0; |
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unsigned long sdr0_pfc1, sdr0_pfc2; |
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register uint reg; |
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mtdcr(ebccfga, xbcfg); |
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mtdcr(ebccfgd, 0xb8400000); |
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/*--------------------------------------------------------------------
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* Setup the GPIO pins |
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*-------------------------------------------------------------------*/ |
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/* test-only: take GPIO init from pcs440ep ???? in config file */ |
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out32(GPIO0_OR, 0x00000000); |
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out32(GPIO0_TCR, 0x0000000f); |
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out32(GPIO0_OSRL, 0x50015400); |
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out32(GPIO0_OSRH, 0x550050aa); |
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out32(GPIO0_TSRL, 0x50015400); |
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out32(GPIO0_TSRH, 0x55005000); |
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out32(GPIO0_ISR1L, 0x50000000); |
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out32(GPIO0_ISR1H, 0x00000000); |
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out32(GPIO0_ISR2L, 0x00000000); |
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out32(GPIO0_ISR2H, 0x00000100); |
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out32(GPIO0_ISR3L, 0x00000000); |
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out32(GPIO0_ISR3H, 0x00000000); |
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out32(GPIO1_OR, 0x00000000); |
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out32(GPIO1_TCR, 0xc2000000); |
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out32(GPIO1_OSRL, 0x5c280000); |
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out32(GPIO1_OSRH, 0x00000000); |
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out32(GPIO1_TSRL, 0x0c000000); |
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out32(GPIO1_TSRH, 0x00000000); |
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out32(GPIO1_ISR1L, 0x00005550); |
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out32(GPIO1_ISR1H, 0x00000000); |
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out32(GPIO1_ISR2L, 0x00050000); |
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out32(GPIO1_ISR2H, 0x00000000); |
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out32(GPIO1_ISR3L, 0x01400000); |
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out32(GPIO1_ISR3H, 0x00000000); |
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc. |
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*-------------------------------------------------------------------*/ |
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mtdcr(uic0sr, 0xffffffff); /* clear all */ |
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mtdcr(uic0er, 0x00000000); /* disable all */ |
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mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ |
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mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ |
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mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ |
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mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ |
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mtdcr(uic0sr, 0xffffffff); /* clear all */ |
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mtdcr(uic1sr, 0xffffffff); /* clear all */ |
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mtdcr(uic1er, 0x00000000); /* disable all */ |
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mtdcr(uic1cr, 0x00000000); /* all non-critical */ |
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mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ |
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mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ |
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mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ |
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mtdcr(uic1sr, 0xffffffff); /* clear all */ |
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mtdcr(uic2sr, 0xffffffff); /* clear all */ |
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mtdcr(uic2er, 0x00000000); /* disable all */ |
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mtdcr(uic2cr, 0x00000000); /* all non-critical */ |
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mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ |
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mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ |
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mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ |
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mtdcr(uic2sr, 0xffffffff); /* clear all */ |
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/* 50MHz tmrclk */ |
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*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; |
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/* clear write protects */ |
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*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; |
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/* enable Ethernet */ |
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*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00; |
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/* enable USB device */ |
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*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20; |
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/* select Ethernet pins */ |
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mfsdr(SDR0_PFC1, sdr0_pfc1); |
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; |
||||
mfsdr(SDR0_PFC2, sdr0_pfc2); |
||||
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; |
||||
mtsdr(SDR0_PFC2, sdr0_pfc2); |
||||
mtsdr(SDR0_PFC1, sdr0_pfc1); |
||||
|
||||
/* PCI arbiter enabled */ |
||||
mfsdr(sdr_pci0, reg); |
||||
mtsdr(sdr_pci0, 0x80000000 | reg); |
||||
|
||||
/* setup NAND FLASH */ |
||||
mfsdr(SDR0_CUST0, sdr0_cust0); |
||||
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | |
||||
SDR0_CUST0_NDFC_ENABLE | |
||||
SDR0_CUST0_NDFC_BW_8_BIT | |
||||
SDR0_CUST0_NDFC_ARE_MASK | |
||||
(0x80000000 >> (28 + CFG_NAND_CS)); |
||||
mtsdr(SDR0_CUST0, sdr0_cust0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
| misc_init_r. |
||||
+---------------------------------------------------------------------------*/ |
||||
int misc_init_r(void) |
||||
{ |
||||
uint pbcr; |
||||
int size_val = 0; |
||||
unsigned long usb2d0cr = 0; |
||||
unsigned long usb2phy0cr, usb2h0cr = 0; |
||||
unsigned long sdr0_pfc1; |
||||
char *act = getenv("usbact"); |
||||
|
||||
/*
|
||||
* FLASH stuff... |
||||
*/ |
||||
|
||||
/* Re-do sizing to get full correct info */ |
||||
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
||||
mtdcr(ebccfga, pb3cr); |
||||
#else |
||||
mtdcr(ebccfga, pb0cr); |
||||
#endif |
||||
pbcr = mfdcr(ebccfgd); |
||||
switch (gd->bd->bi_flashsize) { |
||||
case 1 << 20: |
||||
size_val = 0; |
||||
break; |
||||
case 2 << 20: |
||||
size_val = 1; |
||||
break; |
||||
case 4 << 20: |
||||
size_val = 2; |
||||
break; |
||||
case 8 << 20: |
||||
size_val = 3; |
||||
break; |
||||
case 16 << 20: |
||||
size_val = 4; |
||||
break; |
||||
case 32 << 20: |
||||
size_val = 5; |
||||
break; |
||||
case 64 << 20: |
||||
size_val = 6; |
||||
break; |
||||
case 128 << 20: |
||||
size_val = 7; |
||||
break; |
||||
} |
||||
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
||||
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
||||
mtdcr(ebccfga, pb3cr); |
||||
#else |
||||
mtdcr(ebccfga, pb0cr); |
||||
#endif |
||||
mtdcr(ebccfgd, pbcr); |
||||
|
||||
/* adjust flash start and offset */ |
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
||||
gd->bd->bi_flashoffset = 0; |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* Monitor protection ON by default */ |
||||
(void)flash_protect(FLAG_PROTECT_SET, |
||||
-CFG_MONITOR_LEN, |
||||
0xffffffff, |
||||
&flash_info[0]); |
||||
|
||||
/* Env protection ON by default */ |
||||
(void)flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR_REDUND, |
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
/*
|
||||
* USB suff... |
||||
*/ |
||||
if (act == NULL || strcmp(act, "hostdev") == 0) { |
||||
/* SDR Setting */ |
||||
mfsdr(SDR0_PFC1, sdr0_pfc1); |
||||
mfsdr(SDR0_USB0, usb2d0cr); |
||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
||||
mfsdr(SDR0_USB2H0CR, usb2h0cr); |
||||
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ |
||||
|
||||
/* An 8-bit/60MHz interface is the only possible alternative
|
||||
when connecting the Device to the PHY */ |
||||
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
||||
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ |
||||
|
||||
/* To enable the USB 2.0 Device function through the UTMI interface */ |
||||
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
||||
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ |
||||
|
||||
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
||||
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ |
||||
|
||||
mtsdr(SDR0_PFC1, sdr0_pfc1); |
||||
mtsdr(SDR0_USB0, usb2d0cr); |
||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
||||
mtsdr(SDR0_USB2H0CR, usb2h0cr); |
||||
|
||||
/*clear resets*/ |
||||
udelay (1000); |
||||
mtsdr(SDR0_SRST1, 0x00000000); |
||||
udelay (1000); |
||||
mtsdr(SDR0_SRST0, 0x00000000); |
||||
|
||||
printf("USB: Host(int phy) Device(ext phy)\n"); |
||||
|
||||
} else if (strcmp(act, "dev") == 0) { |
||||
/*-------------------PATCH-------------------------------*/ |
||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
||||
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ |
||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
||||
|
||||
udelay (1000); |
||||
mtsdr(SDR0_SRST1, 0x672c6000); |
||||
|
||||
udelay (1000); |
||||
mtsdr(SDR0_SRST0, 0x00000080); |
||||
|
||||
udelay (1000); |
||||
mtsdr(SDR0_SRST1, 0x60206000); |
||||
|
||||
*(unsigned int *)(0xe0000350) = 0x00000001; |
||||
|
||||
udelay (1000); |
||||
mtsdr(SDR0_SRST1, 0x60306000); |
||||
/*-------------------PATCH-------------------------------*/ |
||||
|
||||
/* SDR Setting */ |
||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
||||
mfsdr(SDR0_USB2H0CR, usb2h0cr); |
||||
mfsdr(SDR0_USB0, usb2d0cr); |
||||
mfsdr(SDR0_PFC1, sdr0_pfc1); |
||||
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ |
||||
|
||||
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
||||
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ |
||||
|
||||
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
||||
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/ |
||||
|
||||
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
||||
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ |
||||
|
||||
mtsdr(SDR0_USB2H0CR, usb2h0cr); |
||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
||||
mtsdr(SDR0_USB0, usb2d0cr); |
||||
mtsdr(SDR0_PFC1, sdr0_pfc1); |
||||
|
||||
/*clear resets*/ |
||||
udelay (1000); |
||||
mtsdr(SDR0_SRST1, 0x00000000); |
||||
udelay (1000); |
||||
mtsdr(SDR0_SRST0, 0x00000000); |
||||
|
||||
printf("USB: Device(int phy)\n"); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
char *s = getenv("serial#"); |
||||
|
||||
printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); |
||||
if (s != NULL) { |
||||
puts(", serial# "); |
||||
puts(s); |
||||
} |
||||
putc('\n'); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram(void) |
||||
{ |
||||
unsigned long *mem = (unsigned long *)0; |
||||
const unsigned long kend = (1024 / sizeof(unsigned long)); |
||||
unsigned long k, n; |
||||
|
||||
mtmsr(0); |
||||
|
||||
for (k = 0; k < CFG_MBYTES_SDRAM; |
||||
++k, mem += (1024 / sizeof(unsigned long))) { |
||||
if ((k & 1023) == 0) { |
||||
printf("%3d MB\r", k / 1024); |
||||
} |
||||
|
||||
memset(mem, 0xaaaaaaaa, 1024); |
||||
for (n = 0; n < kend; ++n) { |
||||
if (mem[n] != 0xaaaaaaaa) { |
||||
printf("SDRAM test fails at: %08x\n", |
||||
(uint) & mem[n]); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
memset(mem, 0x55555555, 1024); |
||||
for (n = 0; n < kend; ++n) { |
||||
if (mem[n] != 0x55555555) { |
||||
printf("SDRAM test fails at: %08x\n", |
||||
(uint) & mem[n]); |
||||
return 1; |
||||
} |
||||
} |
||||
} |
||||
printf("SDRAM test passes\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init |
||||
* |
||||
* This routine is called just prior to registering the hose and gives |
||||
* the board the opportunity to check things. Returning a value of zero |
||||
* indicates that things are bad & PCI initialization should be aborted. |
||||
* |
||||
* Different boards may wish to customize the pci controller structure |
||||
* (add regions, override default access routines, etc) or perform |
||||
* certain pre-initialization actions. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) |
||||
int pci_pre_init(struct pci_controller *hose) |
||||
{ |
||||
unsigned long addr; |
||||
#if 0 |
||||
/*--------------------------------------------------------------------------+
|
||||
* Cactus is always configured as the host & requires the |
||||
* PCI arbiter to be enabled ??? |
||||
*--------------------------------------------------------------------------*/ |
||||
unsigned long strap; |
||||
mfsdr(sdr_sdstp1, strap); |
||||
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { |
||||
printf("PCI: SDR0_STRP1[PAE] not set.\n"); |
||||
printf("PCI: Configuration aborted.\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB3 devices to 0. |
||||
| Set PLB3 arbiter to fair mode. |
||||
+-------------------------------------------------------------------------*/ |
||||
mfsdr(sdr_amp1, addr); |
||||
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); |
||||
addr = mfdcr(plb3_acr); |
||||
mtdcr(plb3_acr, addr | 0x80000000); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB4 devices to 0. |
||||
+-------------------------------------------------------------------------*/ |
||||
mfsdr(sdr_amp0, addr); |
||||
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); |
||||
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ |
||||
mtdcr(plb4_acr, addr); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set Nebula PLB4 arbiter to fair mode. |
||||
+-------------------------------------------------------------------------*/ |
||||
/* Segment0 */ |
||||
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; |
||||
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; |
||||
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; |
||||
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; |
||||
mtdcr(plb0_acr, addr); |
||||
|
||||
/* Segment1 */ |
||||
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; |
||||
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; |
||||
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; |
||||
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; |
||||
mtdcr(plb1_acr, addr); |
||||
|
||||
return 1; |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init |
||||
* |
||||
* The bootstrap configuration provides default settings for the pci |
||||
* inbound map (PIM). But the bootstrap config choices are limited and |
||||
* may not be sufficient for a given board. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
||||
void pci_target_init(struct pci_controller *hose) |
||||
{ |
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Direct MMIO registers |
||||
*--------------------------------------------------------------------------*/ |
||||
/*--------------------------------------------------------------------------+
|
||||
| PowerPC440EPX PCI Master configuration. |
||||
| Map one 1Gig range of PLB/processor addresses to PCI memory space. |
||||
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF |
||||
| Use byte reversed out routines to handle endianess. |
||||
| Make this region non-prefetchable. |
||||
+--------------------------------------------------------------------------*/ |
||||
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
||||
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ |
||||
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ |
||||
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
||||
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
||||
|
||||
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
||||
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ |
||||
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ |
||||
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
||||
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
||||
|
||||
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ |
||||
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ |
||||
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ |
||||
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Configuration registers |
||||
*--------------------------------------------------------------------------*/ |
||||
|
||||
/* Program the board's subsystem id/vendor id */ |
||||
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, |
||||
CFG_PCI_SUBSYS_VENDORID); |
||||
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); |
||||
|
||||
/* Configure command register as bus master */ |
||||
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); |
||||
|
||||
/* 240nS PCI clock */ |
||||
pci_write_config_word(0, PCI_LATENCY_TIMER, 1); |
||||
|
||||
/* No error reporting */ |
||||
pci_write_config_word(0, PCI_ERREN, 0); |
||||
|
||||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); |
||||
|
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_master_init |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) |
||||
void pci_master_init(struct pci_controller *hose) |
||||
{ |
||||
unsigned short temp_short; |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
| Write the PowerPC440 EP PCI Configuration regs. |
||||
| Enable PowerPC440 EP to be a master on the PCI bus (PMM). |
||||
| Enable PowerPC440 EP to act as a PCI memory target (PTM). |
||||
+--------------------------------------------------------------------------*/ |
||||
pci_read_config_word(0, PCI_COMMAND, &temp_short); |
||||
pci_write_config_word(0, PCI_COMMAND, |
||||
temp_short | PCI_COMMAND_MASTER | |
||||
PCI_COMMAND_MEMORY); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host |
||||
* |
||||
* This routine is called to determine if a pci scan should be |
||||
* performed. With various hardware environments (especially cPCI and |
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable |
||||
* bit in the strap register, or generic host/adapter assumptions. |
||||
* |
||||
* Rather than hard-code a bad assumption in the general 440 code, the |
||||
* 440 pci code requires the board to decide at runtime. |
||||
* |
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode. |
||||
* |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) |
||||
int is_pci_host(struct pci_controller *hose) |
||||
{ |
||||
/* Cactus is always configured as host. */ |
||||
return (1); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
@ -0,0 +1,67 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* (C) Copyright 2006 |
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com |
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| EBC Configuration Register - EBC0_CFG |
||||
+----------------------------------------------------------------------------*/ |
||||
/* External Bus Three-State Control */ |
||||
#define EBC0_CFG_EBTC_DRIVEN 0x80000000 |
||||
/* Device-Paced Time-out Disable */ |
||||
#define EBC0_CFG_PTD_ENABLED 0x00000000 |
||||
/* Ready Timeout Count */ |
||||
#define EBC0_CFG_RTC_MASK 0x38000000 |
||||
#define EBC0_CFG_RTC_16PERCLK 0x00000000 |
||||
#define EBC0_CFG_RTC_32PERCLK 0x08000000 |
||||
#define EBC0_CFG_RTC_64PERCLK 0x10000000 |
||||
#define EBC0_CFG_RTC_128PERCLK 0x18000000 |
||||
#define EBC0_CFG_RTC_256PERCLK 0x20000000 |
||||
#define EBC0_CFG_RTC_512PERCLK 0x28000000 |
||||
#define EBC0_CFG_RTC_1024PERCLK 0x30000000 |
||||
#define EBC0_CFG_RTC_2048PERCLK 0x38000000 |
||||
/* External Master Priority Low */ |
||||
#define EBC0_CFG_EMPL_LOW 0x00000000 |
||||
#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000 |
||||
#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000 |
||||
#define EBC0_CFG_EMPL_HIGH 0x06000000 |
||||
/* External Master Priority High */ |
||||
#define EBC0_CFG_EMPH_LOW 0x00000000 |
||||
#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000 |
||||
#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000 |
||||
#define EBC0_CFG_EMPH_HIGH 0x01800000 |
||||
/* Chip Select Three-State Control */ |
||||
#define EBC0_CFG_CSTC_DRIVEN 0x00400000 |
||||
/* Burst Prefetch */ |
||||
#define EBC0_CFG_BPF_ONEDW 0x00000000 |
||||
#define EBC0_CFG_BPF_TWODW 0x00100000 |
||||
#define EBC0_CFG_BPF_FOURDW 0x00200000 |
||||
/* External Master Size */ |
||||
#define EBC0_CFG_EMS_8BIT 0x00000000 |
||||
/* Power Management Enable */ |
||||
#define EBC0_CFG_PME_DISABLED 0x00000000 |
||||
#define EBC0_CFG_PME_ENABLED 0x00020000 |
||||
/* Power Management Timer */ |
||||
#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) |
||||
|
||||
#define SDR0_USB0 0x0320 /* USB Control Register */ |
||||
@ -0,0 +1,131 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
|
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,145 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/ppc4xx/start.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
|
||||
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); |
||||
|
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,173 @@ |
||||
/*
|
||||
* Overview: |
||||
* Platform independend driver for NDFC (NanD Flash Controller) |
||||
* integrated into EP440 cores |
||||
* |
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* Based on original work by |
||||
* Thomas Gleixner |
||||
* Copyright 2006 IBM |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) |
||||
|
||||
#include <nand.h> |
||||
#include <linux/mtd/ndfc.h> |
||||
#include <asm/processor.h> |
||||
#include <ppc440.h> |
||||
|
||||
static u8 hwctl = 0; |
||||
|
||||
static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) |
||||
{ |
||||
switch (cmd) { |
||||
case NAND_CTL_SETCLE: |
||||
hwctl |= 0x1; |
||||
break; |
||||
|
||||
case NAND_CTL_CLRCLE: |
||||
hwctl &= ~0x1; |
||||
break; |
||||
|
||||
case NAND_CTL_SETALE: |
||||
hwctl |= 0x2; |
||||
break; |
||||
|
||||
case NAND_CTL_CLRALE: |
||||
hwctl &= ~0x2; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) |
||||
{ |
||||
struct nand_chip *this = mtdinfo->priv; |
||||
ulong base = (ulong) this->IO_ADDR_W; |
||||
|
||||
if (hwctl & 0x1) |
||||
out8(base + NDFC_CMD, byte); |
||||
else if (hwctl & 0x2) |
||||
out8(base + NDFC_ALE, byte); |
||||
else |
||||
out8(base + NDFC_DATA, byte); |
||||
} |
||||
|
||||
static u_char ndfc_read_byte(struct mtd_info *mtdinfo) |
||||
{ |
||||
struct nand_chip *this = mtdinfo->priv; |
||||
ulong base = (ulong) this->IO_ADDR_W; |
||||
|
||||
return (in8(base + NDFC_DATA)); |
||||
} |
||||
|
||||
static int ndfc_dev_ready(struct mtd_info *mtdinfo) |
||||
{ |
||||
struct nand_chip *this = mtdinfo->priv; |
||||
ulong base = (ulong) this->IO_ADDR_W; |
||||
|
||||
while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) |
||||
; |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
#ifndef CONFIG_NAND_SPL |
||||
/*
|
||||
* Don't use these speedup functions in NAND boot image, since the image |
||||
* has to fit into 4kByte. |
||||
*/ |
||||
|
||||
/*
|
||||
* Speedups for buffer read/write/verify |
||||
* |
||||
* NDFC allows 32bit read/write of data. So we can speed up the buffer |
||||
* functions. No further checking, as nand_base will always read/write |
||||
* page aligned. |
||||
*/ |
||||
static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) |
||||
{ |
||||
struct nand_chip *this = mtdinfo->priv; |
||||
ulong base = (ulong) this->IO_ADDR_W; |
||||
uint32_t *p = (uint32_t *) buf; |
||||
|
||||
for(;len > 0; len -= 4) |
||||
*p++ = in32(base + NDFC_DATA); |
||||
} |
||||
|
||||
static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) |
||||
{ |
||||
struct nand_chip *this = mtdinfo->priv; |
||||
ulong base = (ulong) this->IO_ADDR_W; |
||||
uint32_t *p = (uint32_t *) buf; |
||||
|
||||
for(; len > 0; len -= 4) |
||||
out32(base + NDFC_DATA, *p++); |
||||
} |
||||
|
||||
static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) |
||||
{ |
||||
struct nand_chip *this = mtdinfo->priv; |
||||
ulong base = (ulong) this->IO_ADDR_W; |
||||
uint32_t *p = (uint32_t *) buf; |
||||
|
||||
for(; len > 0; len -= 4) |
||||
if (*p++ != in32(base + NDFC_DATA)) |
||||
return -1; |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* #ifndef CONFIG_NAND_SPL */ |
||||
|
||||
void board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
nand->eccmode = NAND_ECC_SOFT; |
||||
|
||||
nand->hwcontrol = ndfc_hwcontrol; |
||||
nand->read_byte = ndfc_read_byte; |
||||
nand->write_byte = ndfc_write_byte; |
||||
nand->dev_ready = ndfc_dev_ready; |
||||
|
||||
#ifndef CONFIG_NAND_SPL |
||||
nand->write_buf = ndfc_write_buf; |
||||
nand->read_buf = ndfc_read_buf; |
||||
nand->verify_buf = ndfc_verify_buf; |
||||
#else |
||||
/*
|
||||
* Setup EBC (CS0 only right now) |
||||
*/ |
||||
mtdcr(ebccfga, xbcfg); |
||||
mtdcr(ebccfgd, 0xb8400000); |
||||
|
||||
mtebc(pb0cr, CFG_EBC_PB0CR); |
||||
mtebc(pb0ap, CFG_EBC_PB0AP); |
||||
#endif |
||||
|
||||
/* Set NandFlash Core Configuration Register */ |
||||
/* Chip select 3, 1col x 2 rows */ |
||||
out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24)); |
||||
out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222); |
||||
} |
||||
|
||||
#endif |
||||
@ -0,0 +1,36 @@ |
||||
----------------------------- |
||||
NAND boot on PPC440 platforms |
||||
----------------------------- |
||||
|
||||
This document describes the U-Boot NAND boot feature as it |
||||
is implemented for the AMCC Sequoia (PPC440EPx) board. |
||||
|
||||
The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH, |
||||
completely without NOR FLASH. This can be done by using the NAND |
||||
boot feature of the 440 NAND flash controller (NDFC). |
||||
|
||||
Here a short desciption of the different boot stages: |
||||
|
||||
a) IPL (Initial Program Loader, integrated inside CPU) |
||||
------------------------------------------------------ |
||||
Will load first 4k from NAND (SPL) into cache and execute it from there. |
||||
|
||||
b) SPL (Secondary Program Loader) |
||||
--------------------------------- |
||||
Will load special U-Boot version (NUB) from NAND and execute it. This SPL |
||||
has to fit into 4kByte. It sets up the CPU and configures the SDRAM |
||||
controller and the NAND controller so that the special U-Boot image can be |
||||
loaded from NAND to SDRAM. |
||||
This special image is build in the directory "nand_spl". |
||||
|
||||
c) NUB (NAND U-Boot) |
||||
-------------------- |
||||
This NAND U-Boot (NUB) is a special U-Boot version which can be started |
||||
from RAM. Therefore it mustn't (re-)configure the SDRAM controller. |
||||
|
||||
On 440EPx the SPL is copied to internal SRAM before the NAND controller |
||||
is set up. While still running from cache, I experienced problems accessing |
||||
the NAND controller. |
||||
|
||||
|
||||
September 07 2006, Stefan Roese <sr@denx.de> |
||||
@ -0,0 +1,431 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* (C) Copyright 2006 |
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com |
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* sequoia.h - configuration for Sequoia board (PowerPC440EPx) |
||||
***********************************************************************/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SEQUOIA 1 /* Board is Sequoia */ |
||||
#define CONFIG_440EPX 1 /* Specific PPC440EPx */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ |
||||
|
||||
#define CFG_BOOT_BASE_ADDR 0xf0000000 |
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ |
||||
#define CFG_OCM_BASE 0xe0010000 /* ocm */ |
||||
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ |
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
||||
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 |
||||
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 |
||||
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 |
||||
|
||||
/* Don't change either of these */ |
||||
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ |
||||
|
||||
#define CFG_USB2D0_BASE 0xe0000100 |
||||
#define CFG_USB_DEVICE 0xe0000000 |
||||
#define CFG_USB_HOST 0xe0000400 |
||||
#define CFG_BCSR_BASE 0xc0000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer |
||||
*----------------------------------------------------------------------*/ |
||||
#if 0 |
||||
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ |
||||
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
||||
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ |
||||
#else |
||||
#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ |
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ |
||||
#endif |
||||
|
||||
#define CFG_INIT_RAM_END (4 << 10) |
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SERIAL_MULTI 1 |
||||
/* define this if you want console on UART1 */ |
||||
#undef CONFIG_UART1_CONSOLE |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
/*
|
||||
* Define here the location of the environment variables (FLASH or EEPROM). |
||||
* Note: DENX encourages to use redundant environment in FLASH. |
||||
*/ |
||||
#if 1 /* test-only */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
#else |
||||
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
||||
#endif |
||||
#if 0 |
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */ |
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ |
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND FLASH |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_NAND_BASE CFG_NAND_ADDR |
||||
|
||||
/*
|
||||
* IPL (Initial Program Loader, integrated inside CPU) |
||||
* Will load first 4k from NAND (SPL) into cache and execute it from there. |
||||
* |
||||
* SPL (Secondary Program Loader) |
||||
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL |
||||
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM |
||||
* controller and the NAND controller so that the special U-Boot image can be |
||||
* loaded from NAND to SDRAM. |
||||
* |
||||
* NUB (NAND U-Boot) |
||||
* This NAND U-Boot (NUB) is a special U-Boot version which can be started |
||||
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller. |
||||
* |
||||
* On 440EPx the SPL is copied to SDRAM before the NAND controller is |
||||
* set up. While still running from cache, I experienced problems accessing |
||||
* the NAND controller. sr - 2006-08-25 |
||||
*/ |
||||
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
||||
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ |
||||
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ |
||||
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ |
||||
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ |
||||
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) |
||||
|
||||
/*
|
||||
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here) |
||||
*/ |
||||
#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
||||
#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ |
||||
|
||||
/*
|
||||
* Now the NAND chip has to be defined (no autodetection used!) |
||||
*/ |
||||
#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ |
||||
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ |
||||
#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ |
||||
#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ |
||||
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_NAND |
||||
#define CFG_ENV_SIZE 0x4000 |
||||
#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE) |
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MBYTES_SDRAM (256) /* 256MB */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_MULTI_EEPROMS |
||||
#define CFG_I2C_EEPROM_ADDR (0xa8>>1) |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
#ifdef CFG_ENV_IS_IN_EEPROM |
||||
#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ |
||||
#define CFG_ENV_OFFSET 0x0 |
||||
#endif /* CFG_ENV_IS_IN_EEPROM */ |
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
||||
#define CONFIG_DTT_AD7414 1 /* use AD7414 */ |
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ |
||||
#define CFG_DTT_MAX_TEMP 70 |
||||
#define CFG_DTT_LOW_TEMP -30 |
||||
#define CFG_DTT_HYSTERESIS 3 |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"hostname=sequoia\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=/tftpboot/sequoia/uImage\0" \
|
||||
"kernel_addr=FE000000\0" \
|
||||
"ramdisk_addr=FE180000\0" \
|
||||
"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \
|
||||
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
|
||||
"cp.b 100000 FFFA0000 60000\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_M88E1111_PHY 1 |
||||
#define CONFIG_IBM_EMAC4_V4 1 |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
||||
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
|
||||
#define CONFIG_HAS_ETH0 |
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
||||
#define CONFIG_PHY1_ADDR 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_OHCI |
||||
#define CONFIG_USB_STORAGE |
||||
|
||||
/* Comment this out to enable USB 1.1 device */ |
||||
#define USB_2_0_DEVICE |
||||
|
||||
/* Partitions */ |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_ISO_PARTITION |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SDRAM | \
|
||||
CFG_CMD_USB ) |
||||
|
||||
#define CONFIG_SUPPORT_VFAT |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ |
||||
#define CFG_PCI_TARGET_INIT |
||||
#define CFG_PCI_MASTER_INIT |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
||||
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_FLASH CFG_FLASH_BASE |
||||
#define CFG_NAND 0xD0000000 |
||||
#define CFG_CPLD 0xC0000000 |
||||
|
||||
/*
|
||||
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting |
||||
*/ |
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
||||
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */ |
||||
/* Memory Bank 0 (NOR-FLASH) initialization */ |
||||
#define CFG_EBC_PB0AP 0x03017300 |
||||
#define CFG_EBC_PB0CR (CFG_FLASH | 0xba000) |
||||
|
||||
/* Memory Bank 3 (NAND-FLASH) initialization */ |
||||
#define CFG_EBC_PB3AP 0x018003c0 |
||||
#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) |
||||
#else |
||||
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ |
||||
/* Memory Bank 3 (NOR-FLASH) initialization */ |
||||
#define CFG_EBC_PB3AP 0x03017300 |
||||
#define CFG_EBC_PB3CR (CFG_FLASH | 0xba000) |
||||
|
||||
/* Memory Bank 0 (NAND-FLASH) initialization */ |
||||
#define CFG_EBC_PB0AP 0x018003c0 |
||||
#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) |
||||
#endif |
||||
|
||||
/* Memory Bank 2 (CPLD) initialization */ |
||||
#define CFG_EBC_PB2AP 0x24814580 |
||||
#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,67 @@ |
||||
/*
|
||||
* linux/include/linux/mtd/ndfc.h |
||||
* |
||||
* Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* Info: |
||||
* Contains defines, datastructures for ndfc nand controller |
||||
* |
||||
*/ |
||||
#ifndef __LINUX_MTD_NDFC_H |
||||
#define __LINUX_MTD_NDFC_H |
||||
|
||||
/* NDFC Register definitions */ |
||||
#define NDFC_CMD 0x00 |
||||
#define NDFC_ALE 0x04 |
||||
#define NDFC_DATA 0x08 |
||||
#define NDFC_ECC 0x10 |
||||
#define NDFC_BCFG0 0x30 |
||||
#define NDFC_BCFG1 0x34 |
||||
#define NDFC_BCFG2 0x38 |
||||
#define NDFC_BCFG3 0x3c |
||||
#define NDFC_CCR 0x40 |
||||
#define NDFC_STAT 0x44 |
||||
#define NDFC_HWCTL 0x48 |
||||
#define NDFC_REVID 0x50 |
||||
|
||||
#define NDFC_STAT_IS_READY 0x01000000 |
||||
|
||||
#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ |
||||
#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */ |
||||
#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */ |
||||
#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */ |
||||
#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */ |
||||
#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */ |
||||
#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */ |
||||
#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */ |
||||
#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */ |
||||
#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */ |
||||
#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */ |
||||
#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */ |
||||
#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */ |
||||
#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */ |
||||
#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */ |
||||
#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */ |
||||
|
||||
#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */ |
||||
#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */ |
||||
#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */ |
||||
#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */ |
||||
#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */ |
||||
|
||||
#define NDFC_MAX_BANKS 4 |
||||
|
||||
struct ndfc_controller_settings { |
||||
uint32_t ccr_settings; |
||||
uint64_t ndfc_erpn; |
||||
}; |
||||
|
||||
struct ndfc_chip_settings { |
||||
uint32_t bank_settings; |
||||
}; |
||||
|
||||
#endif |
||||
@ -0,0 +1,83 @@ |
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
include board/$(BOARDDIR)/config.mk |
||||
|
||||
LDSCRIPT= board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o init.o resetvec.o
|
||||
COBJS = nand_boot.o ndfc.o sdram.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
ALL = u-boot-spl u-boot-spl.bin u-boot-spl-4k.bin
|
||||
|
||||
all: $(obj).depend $(ALL) |
||||
|
||||
u-boot-spl-4k.bin: u-boot-spl |
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
u-boot-spl.bin: u-boot-spl |
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
u-boot-spl: $(OBJS) |
||||
$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
|
||||
-Map u-boot-spl.map -o u-boot-spl
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
ndfc.c: |
||||
@rm -f ndfc.c
|
||||
ln -s ../cpu/ppc4xx/ndfc.c ndfc.c
|
||||
|
||||
resetvec.S: |
||||
@rm -f resetvec.S
|
||||
ln -s ../cpu/ppc4xx/resetvec.S resetvec.S
|
||||
|
||||
start.S: |
||||
@rm -f start.S
|
||||
ln -s ../cpu/ppc4xx/start.S start.S
|
||||
|
||||
# from board directory
|
||||
init.S: |
||||
@rm -f init.S
|
||||
ln -s ../board/amcc/sequoia/init.S init.S
|
||||
|
||||
sdram.c: |
||||
@rm -f sdram.c
|
||||
ln -s ../board/amcc/sequoia/sdram.c sdram.c
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,49 @@ |
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#
|
||||
# AMCC 440EPx Reference Platform (Sequoia) board
|
||||
#
|
||||
|
||||
#
|
||||
# TEXT_BASE for SPL:
|
||||
#
|
||||
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
|
||||
# in the last 4kBytes of memory space in cache.
|
||||
# We will copy this SPL into internal SRAM in start.S. So we set
|
||||
# TEXT_BASE to starting address in internal SRAM here.
|
||||
#
|
||||
TEXT_BASE = 0xE0013000
|
||||
|
||||
# PAD_TO used to generate a 16kByte binary needed for the combined image
|
||||
# -> PAD_TO = TEXT_BASE + 0x4000
|
||||
PAD_TO = 0xE0017000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1) |
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif |
||||
|
||||
ifeq ($(dbcr),1) |
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif |
||||
@ -0,0 +1,65 @@ |
||||
/* |
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc:common) |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xE0013FFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.text : |
||||
{ |
||||
start.o (.text) |
||||
init.o (.text) |
||||
nand_boot.o (.text) |
||||
sdram.o (.text) |
||||
ndfc.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
} |
||||
_etext = .; |
||||
|
||||
.data : |
||||
{ |
||||
*(.rodata*) |
||||
*(.data*) |
||||
*(.sdata*) |
||||
__got2_start = .; |
||||
*(.got2) |
||||
__got2_end = .; |
||||
} |
||||
|
||||
_edata = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) |
||||
*(.bss) |
||||
} |
||||
|
||||
_end = . ; |
||||
} |
||||
@ -0,0 +1,178 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <nand.h> |
||||
|
||||
#define CFG_NAND_READ_DELAY \ |
||||
{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; } |
||||
|
||||
extern void board_nand_init(struct nand_chip *nand); |
||||
extern void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd); |
||||
extern void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte); |
||||
extern u_char ndfc_read_byte(struct mtd_info *mtdinfo); |
||||
extern int ndfc_dev_ready(struct mtd_info *mtdinfo); |
||||
extern int jump_to_ram(ulong delta); |
||||
extern int jump_to_uboot(ulong addr); |
||||
|
||||
static int nand_is_bad_block(struct mtd_info *mtd, int block) |
||||
{ |
||||
struct nand_chip *this = mtd->priv; |
||||
int page_addr = block * CFG_NAND_PAGE_COUNT; |
||||
|
||||
/* Begin command latch cycle */ |
||||
this->hwcontrol(mtd, NAND_CTL_SETCLE); |
||||
this->write_byte(mtd, NAND_CMD_READOOB); |
||||
/* Set ALE and clear CLE to start address cycle */ |
||||
this->hwcontrol(mtd, NAND_CTL_CLRCLE); |
||||
this->hwcontrol(mtd, NAND_CTL_SETALE); |
||||
/* Column address */ |
||||
this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS); /* A[7:0] */ |
||||
this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ |
||||
this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ |
||||
#ifdef CFG_NAND_4_ADDR_CYCLE |
||||
/* One more address cycle for devices > 32MiB */ |
||||
this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */ |
||||
#endif |
||||
/* Latch in address */ |
||||
this->hwcontrol(mtd, NAND_CTL_CLRALE); |
||||
|
||||
/*
|
||||
* Wait a while for the data to be ready |
||||
*/ |
||||
if (this->dev_ready) |
||||
this->dev_ready(mtd); |
||||
else |
||||
CFG_NAND_READ_DELAY; |
||||
|
||||
/*
|
||||
* Read on byte |
||||
*/ |
||||
if (this->read_byte(mtd) != 0xff) |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) |
||||
{ |
||||
struct nand_chip *this = mtd->priv; |
||||
int page_addr = page + block * CFG_NAND_PAGE_COUNT; |
||||
int i; |
||||
|
||||
/* Begin command latch cycle */ |
||||
this->hwcontrol(mtd, NAND_CTL_SETCLE); |
||||
this->write_byte(mtd, NAND_CMD_READ0); |
||||
/* Set ALE and clear CLE to start address cycle */ |
||||
this->hwcontrol(mtd, NAND_CTL_CLRCLE); |
||||
this->hwcontrol(mtd, NAND_CTL_SETALE); |
||||
/* Column address */ |
||||
this->write_byte(mtd, 0); /* A[7:0] */ |
||||
this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ |
||||
this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ |
||||
#ifdef CFG_NAND_4_ADDR_CYCLE |
||||
/* One more address cycle for devices > 32MiB */ |
||||
this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */ |
||||
#endif |
||||
/* Latch in address */ |
||||
this->hwcontrol(mtd, NAND_CTL_CLRALE); |
||||
|
||||
/*
|
||||
* Wait a while for the data to be ready |
||||
*/ |
||||
if (this->dev_ready) |
||||
this->dev_ready(mtd); |
||||
else |
||||
CFG_NAND_READ_DELAY; |
||||
|
||||
/*
|
||||
* Read page into buffer |
||||
*/ |
||||
for (i=0; i<CFG_NAND_PAGE_SIZE; i++) |
||||
*dst++ = this->read_byte(mtd); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst) |
||||
{ |
||||
int block; |
||||
int blockcopy_count; |
||||
int page; |
||||
|
||||
/*
|
||||
* offs has to be aligned to a block address! |
||||
*/ |
||||
block = offs / CFG_NAND_BLOCK_SIZE; |
||||
blockcopy_count = 0; |
||||
|
||||
while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) { |
||||
if (!nand_is_bad_block(mtd, block)) { |
||||
/*
|
||||
* Skip bad blocks |
||||
*/ |
||||
for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) { |
||||
nand_read_page(mtd, block, page, dst); |
||||
dst += CFG_NAND_PAGE_SIZE; |
||||
} |
||||
|
||||
blockcopy_count++; |
||||
} |
||||
|
||||
block++; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void nand_boot(void) |
||||
{ |
||||
ulong mem_size; |
||||
struct nand_chip nand_chip; |
||||
nand_info_t nand_info; |
||||
int ret; |
||||
void (*uboot)(void); |
||||
|
||||
/*
|
||||
* Init sdram, so we have access to memory |
||||
*/ |
||||
mem_size = initdram(0); |
||||
|
||||
/*
|
||||
* Init board specific nand support |
||||
*/ |
||||
nand_info.priv = &nand_chip; |
||||
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE; |
||||
nand_chip.dev_ready = NULL; /* preset to NULL */ |
||||
board_nand_init(&nand_chip); |
||||
|
||||
/*
|
||||
* Load U-Boot image from NAND into RAM |
||||
*/ |
||||
ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, |
||||
CFG_NAND_U_BOOT_SIZE, |
||||
(uchar *)CFG_NAND_U_BOOT_DST); |
||||
|
||||
/*
|
||||
* Jump to U-Boot image |
||||
*/ |
||||
uboot = (void (*)(void))CFG_NAND_U_BOOT_START; |
||||
(*uboot)(); |
||||
} |
||||
Loading…
Reference in new issue