driver/ddr/fsl: Fix timing_cfg_2

Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>

drivers/ddr/fsl/ctrl_regs.c

@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
 		| ((add_lat_mclk & 0xf) << 28)
 		| ((cpo & 0x1f) << 23)
 		| ((wr_lat & 0xf) << 19)
-		| ((wr_lat & 0x10) << 18)
+		| (((wr_lat & 0x10) >> 4) << 18)
 		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 		| ((cke_pls & 0x7) << 6)