Add support for loading U-Boot on the Broadcom 7445 SoC. This port assumes Broadcom's BOLT bootloader is acting as the second stage bootloader, and U-Boot is acting as the third stage bootloader, loaded as an ELF program by BOLT. Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Florian Fainelli <f.fainelli@gmail.com>lime2-spi
Thomas Fitzsimmons
7 years ago
committed by
Tom Rini
parent
d154ca6003
commit
894c3ad27f
@ -0,0 +1,36 @@ |
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if ARCH_BCMSTB |
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config TARGET_BCM7445 |
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bool "Broadcom 7445 TSBL" |
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depends on ARCH_BCMSTB |
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help |
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Support for the Broadcom 7445 SoC. This port assumes BOLT |
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is acting as the second stage bootloader, and U-Boot is |
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acting as the third stage bootloader (TSBL), loaded by BOLT. |
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This port may work on other BCM7xxx boards with |
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configuration changes. |
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config SYS_CPU |
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default "armv7" |
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config SYS_BOARD |
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default "bcmstb" |
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config SYS_VENDOR |
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default "broadcom" |
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config SYS_SOC |
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default "bcmstb" |
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config SYS_CONFIG_NAME |
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default "bcm7445" |
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config SYS_FDT_SAVE_ADDRESS |
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hex "Address to which the prior stage provided DTB will be copied" |
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default 0x1f00000 |
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config BCMSTB_SDHCI_INDEX |
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int "Index of preferred BCMSTB SDHCI alias in DTB" |
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default 1 |
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endif |
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@ -0,0 +1,8 @@ |
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2018 Cisco Systems, Inc.
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#
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# Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
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#
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obj-y := lowlevel_init.o
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@ -0,0 +1,11 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* (C) Copyright 2018 Cisco Systems, Inc. |
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* |
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
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*/ |
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|
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#ifndef _BCMSTB_GPIO_H |
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#define _BCMSTB_GPIO_H |
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#endif /* _BCMSTB_GPIO_H */ |
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@ -0,0 +1,11 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* (C) Copyright 2018 Cisco Systems, Inc. |
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* |
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
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*/ |
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#ifndef _BCMSTB_HARDWARE_H |
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#define _BCMSTB_HARDWARE_H |
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#endif /* _BCMSTB_HARDWARE_H */ |
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@ -0,0 +1,30 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* (C) Copyright 2018 Cisco Systems, Inc. |
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* |
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
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*/ |
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#ifndef _BCMSTB_PRIOR_STAGE_H |
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#define _BCMSTB_PRIOR_STAGE_H |
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#ifndef __ASSEMBLY__ |
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#include <linux/types.h> |
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struct bcmstb_boot_parameters { |
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u32 r0; |
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u32 r1; |
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u32 r2; |
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u32 r3; |
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u32 sp; |
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u32 lr; |
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}; |
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extern struct bcmstb_boot_parameters bcmstb_boot_parameters; |
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extern phys_addr_t prior_stage_fdt_address; |
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#endif /* __ASSEMBLY__ */ |
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#endif /* _BCMSTB_PRIOR_STAGE_H */ |
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@ -0,0 +1,15 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* (C) Copyright 2018 Cisco Systems, Inc. |
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* |
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
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*/ |
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#ifndef _BCMSTB_SDHCI_H |
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#define _BCMSTB_SDHCI_H |
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#include <linux/types.h> |
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int bcmstb_sdhci_init(phys_addr_t regbase); |
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#endif /* _BCMSTB_SDHCI_H */ |
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@ -0,0 +1,13 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* (C) Copyright 2018 Cisco Systems, Inc. |
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* |
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
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*/ |
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#ifndef _BCMSTB_TIMER_H |
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#define _BCMSTB_TIMER_H |
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unsigned long timer_read_counter(void); |
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#endif /* _BCMSTB_TIMER_H */ |
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@ -0,0 +1,21 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* (C) Copyright 2018 Cisco Systems, Inc. |
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* |
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
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*/ |
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#include <linux/linkage.h> |
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ENTRY(save_boot_params) |
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ldr r6, =bcmstb_boot_parameters |
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str r0, [r6, #0] |
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str r1, [r6, #4] |
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str r2, [r6, #8] |
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str r3, [r6, #12] |
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str sp, [r6, #16] |
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str lr, [r6, #20] |
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ldr r6, =prior_stage_fdt_address |
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str r2, [r6] |
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b save_boot_params_ret |
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ENDPROC(save_boot_params) |
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@ -0,0 +1,7 @@ |
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BCM7445 BOARD |
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M: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
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S: Maintained |
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F: board/broadcom/bcmstb/ |
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F: include/configs/bcmstb.h |
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F: include/configs/bcm7445.h |
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F: configs/bcm7445_defconfig |
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@ -0,0 +1,8 @@ |
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2018 Cisco Systems, Inc.
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#
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# Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
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#
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obj-y := bcmstb.o
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@ -0,0 +1,194 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 Cisco Systems, Inc. |
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* |
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
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*/ |
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#include <linux/types.h> |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/bootm.h> |
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#include <mach/sdhci.h> |
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#include <mach/timer.h> |
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#include <mmc.h> |
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#include <fdtdec.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define BCMSTB_DATA_SECTION __attribute__((section(".data"))) |
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struct bcmstb_boot_parameters bcmstb_boot_parameters BCMSTB_DATA_SECTION; |
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phys_addr_t prior_stage_fdt_address BCMSTB_DATA_SECTION; |
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union reg_value_union { |
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const char *data; |
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const phys_addr_t *address; |
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}; |
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int board_init(void) |
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{ |
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return 0; |
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} |
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u32 get_board_rev(void) |
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{ |
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return 0; |
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} |
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void reset_cpu(ulong ignored) |
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{ |
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} |
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int print_cpuinfo(void) |
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{ |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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if (fdtdec_setup_memory_size() != 0) |
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return -EINVAL; |
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return 0; |
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} |
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int dram_init_banksize(void) |
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{ |
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fdtdec_setup_memory_banksize(); |
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/*
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* On this SoC, U-Boot is running as an ELF file. Change the |
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* relocation address to CONFIG_SYS_TEXT_BASE, so that in |
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* setup_reloc, gd->reloc_off works out to 0, effectively |
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* disabling relocation. Otherwise U-Boot hangs in the setup |
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* instructions just before relocate_code in |
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* arch/arm/lib/crt0.S. |
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*/ |
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gd->relocaddr = CONFIG_SYS_TEXT_BASE; |
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return 0; |
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} |
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void enable_caches(void) |
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{ |
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/*
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* This port assumes that the prior stage bootloader has |
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* enabled I-cache and D-cache already. Implementing this |
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* function silences the warning in the default function. |
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*/ |
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} |
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static const phys_addr_t bcmstb_sdhci_address(u32 alias_index) |
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{ |
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int node = 0; |
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int ret = 0; |
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char sdhci[16] = { 0 }; |
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const void *fdt = gd->fdt_blob; |
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const char *path = NULL; |
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struct fdt_resource resource = { 0 }; |
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if (!fdt) { |
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printf("%s: Invalid gd->fdt_blob\n", __func__); |
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return 0; |
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} |
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node = fdt_path_offset(fdt, "/aliases"); |
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if (node < 0) { |
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printf("%s: Failed to find /aliases node\n", __func__); |
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return 0; |
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} |
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sprintf(sdhci, "sdhci%d", alias_index); |
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path = fdt_getprop(fdt, node, sdhci, NULL); |
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if (!path) { |
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printf("%s: Failed to find alias for %s\n", __func__, sdhci); |
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return 0; |
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} |
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node = fdt_path_offset(fdt, path); |
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if (node < 0) { |
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printf("%s: Failed to resolve BCMSTB SDHCI alias\n", __func__); |
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return 0; |
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} |
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", |
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"host", &resource); |
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if (ret) { |
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printf("%s: Failed to read BCMSTB SDHCI host resource\n", |
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__func__); |
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return 0; |
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} |
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return resource.start; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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phys_addr_t sdhci_base_address = 0; |
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sdhci_base_address = bcmstb_sdhci_address(CONFIG_BCMSTB_SDHCI_INDEX); |
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if (!sdhci_base_address) { |
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sdhci_base_address = BCMSTB_SDHCI_BASE; |
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printf("%s: Assuming BCMSTB SDHCI address: 0x%p\n", |
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__func__, (void *)sdhci_base_address); |
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} |
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debug("BCMSTB SDHCI base address: 0x%p\n", (void *)sdhci_base_address); |
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bcmstb_sdhci_init(sdhci_base_address); |
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return 0; |
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} |
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int timer_init(void) |
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{ |
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gd->arch.timer_rate_hz = readl(BCMSTB_TIMER_FREQUENCY); |
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return 0; |
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} |
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ulong get_tbclk(void) |
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{ |
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return gd->arch.timer_rate_hz; |
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} |
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uint64_t get_ticks(void) |
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{ |
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gd->timebase_h = readl(BCMSTB_TIMER_HIGH); |
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gd->timebase_l = readl(BCMSTB_TIMER_LOW); |
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return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l; |
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} |
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int board_late_init(void) |
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{ |
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debug("Arguments from prior stage bootloader:\n"); |
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debug("General Purpose Register 0: 0x%x\n", bcmstb_boot_parameters.r0); |
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debug("General Purpose Register 1: 0x%x\n", bcmstb_boot_parameters.r1); |
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debug("General Purpose Register 2: 0x%x\n", bcmstb_boot_parameters.r2); |
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debug("General Purpose Register 3: 0x%x\n", bcmstb_boot_parameters.r3); |
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debug("Stack Pointer Register: 0x%x\n", bcmstb_boot_parameters.sp); |
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debug("Link Register: 0x%x\n", bcmstb_boot_parameters.lr); |
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debug("Assuming timer frequency register at: 0x%p\n", |
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(void *)BCMSTB_TIMER_FREQUENCY); |
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debug("Read timer frequency (in Hz): %ld\n", gd->arch.timer_rate_hz); |
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debug("Prior stage provided DTB at: 0x%p\n", |
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(void *)prior_stage_fdt_address); |
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/*
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* Set fdtcontroladdr in the environment so that scripts can |
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* refer to it, for example, to reuse it for fdtaddr. |
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*/ |
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env_set_hex("fdtcontroladdr", prior_stage_fdt_address); |
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/*
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* Do not set machid to the machine identifier value provided |
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* by the prior stage bootloader (bcmstb_boot_parameters.r1) |
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* because we're using a device tree to boot Linux. |
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*/ |
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return 0; |
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} |
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@ -0,0 +1,27 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_BCMSTB=y |
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CONFIG_TARGET_BCM7445=y |
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CONFIG_USE_PRIVATE_LIBGCC=y |
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CONFIG_OF_CONTROL=y |
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CONFIG_OF_PRIOR_STAGE=y |
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CONFIG_DM=y |
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CONFIG_DM_SPI=y |
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CONFIG_DM_SPI_FLASH=y |
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CONFIG_SPI=y |
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CONFIG_SPI_FLASH=y |
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CONFIG_ENV_IS_IN_SPI_FLASH=y |
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CONFIG_BCMSTB_SPI=y |
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CONFIG_FIT=y |
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CONFIG_FIT_SIGNATURE=y |
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CONFIG_RSA=y |
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CONFIG_BLK=n |
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CONFIG_SDHCI=y |
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CONFIG_MMC_SDHCI=y |
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CONFIG_MMC_SDHCI_BCMSTB=y |
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CONFIG_CONS_INDEX=3 |
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CONFIG_BOOTDELAY=1 |
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CONFIG_SYS_PROMPT="U-Boot>" |
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CONFIG_HUSH_PARSER=y |
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CONFIG_SYS_TEXT_BASE=0x80100000 |
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CONFIG_SYS_NS16550_COM3=0xf040ab00 |
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CONFIG_EFI_LOADER=n |
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@ -0,0 +1,150 @@ |
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Summary |
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======= |
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This document describes how to use U-Boot on the Broadcom 7445 SoC, as |
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a third stage bootloader loaded by Broadcom's BOLT bootloader. |
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BOLT loads U-Boot as a generic ELF binary. Some U-Boot features such |
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as networking are not yet available but other important features are, |
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including: |
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- ext4 file system traversal |
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- support for loading FIT images |
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- advanced scripting |
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- support for FIT-provided DTBs instead of relying on the |
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BOLT-provided DTB |
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A customized version of this port has been used in production. The |
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same approach may work on other BCM7xxx boards, with some |
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configuration adjustments and memory layout experimentation. |
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Build |
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===== |
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make bcm7445_defconfig |
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make |
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${CROSS_COMPILE}strip u-boot |
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Run |
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=== |
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Flash the u-boot binary into board storage, then invoke it from BOLT. |
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For example: |
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BOLT> boot -bsu -elf flash0.u-boot1 |
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This port assumes that I-cache and D-cache are already enabled when |
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U-Boot is entered. |
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Flattened Image Tree Support |
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============================ |
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What follows is an example FIT image source file. Build it with: |
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mkimage -f image.its image.itb |
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Booting the resulting image.itb was tested on BOLT v1.20, with the |
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following kernels: |
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https://github.com/Broadcom/stblinux-3.14 |
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https://github.com/Broadcom/stblinux-4.1 |
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https://github.com/Broadcom/stblinux-4.9 |
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and with a generic ARMv7 root file system. |
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image.its: |
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/dts-v1/; |
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/ { |
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description = "BCM7445 FIT"; |
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images { |
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kernel@1 { |
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description = "Linux kernel"; |
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/* |
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* This kernel image output format can be |
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* generated with: |
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* |
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* make vmlinux |
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* ${CROSS_COMPILE}objcopy -O binary -S vmlinux vmlinux.bin |
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* gzip -9 vmlinux.bin |
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* |
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* For stblinux-3.14, the specific Broadcom |
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* board type should be configured in the |
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* kernel, for example CONFIG_BCM7445D0=y. |
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*/ |
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data = /incbin/("<vmlinux.bin.gz>"); |
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type = "kernel"; |
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arch = "arm"; |
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os = "linux"; |
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compression = "gzip"; |
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load = <0x8000>; |
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entry = <0x8000>; |
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hash@1 { |
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algo = "sha256"; |
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}; |
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}; |
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ramdisk@1 { |
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description = "Initramfs root file system"; |
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data = /incbin/("<initramfs.cpio.gz>"); |
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type = "ramdisk"; |
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arch = "arm"; |
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os = "linux"; |
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compression = "gzip"; |
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/* |
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* Set the environment variable initrd_high to |
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* 0xffffffff, and set "load" and "entry" here |
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* to 0x0 to keep initramfs in-place and to |
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* accommodate stblinux bmem/CMA reservations. |
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*/ |
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load = <0x0>; |
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entry = <0x0>; |
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hash@1 { |
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algo = "sha256"; |
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}; |
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}; |
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fdt@1 { |
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description = "Device tree dumped from BOLT"; |
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/* |
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* This DTB should be similar to the |
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* BOLT-generated device tree, after BOLT has |
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* done its runtime modifications to it. For |
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* example, it can be dumped from within |
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* U-Boot (at ${fdtcontroladdr}), after BOLT |
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* has loaded U-Boot. The result can be added |
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* to the Linux source tree as a .dts file. |
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* |
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* To support modifications to the device tree |
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* in-place in U-Boot, add to Linux's |
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* arch/arm/boot/dts/Makefile: |
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* |
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* DTC_FLAGS ?= -p 4096 |
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* |
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* This will leave some padding in the DTB and |
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* thus reserve room for node additions. |
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* |
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* Also, set the environment variable fdt_high |
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* to 0xffffffff to keep the DTB in-place and |
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* to accommodate stblinux bmem/CMA |
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* reservations. |
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*/ |
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data = /incbin/("<bolt-<version>.dtb"); |
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type = "flat_dt"; |
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arch = "arm"; |
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compression = "none"; |
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hash@1 { |
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algo = "sha256"; |
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}; |
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}; |
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}; |
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configurations { |
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default = "conf@bcm7445"; |
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conf@bcm7445 { |
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description = "BCM7445 configuration"; |
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kernel = "kernel@1"; |
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ramdisk = "ramdisk@1"; |
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fdt = "fdt@1"; |
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}; |
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}; |
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}; |
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@ -0,0 +1,67 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 Cisco Systems, Inc. |
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* |
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
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*/ |
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|
||||
#include <common.h> |
||||
#include <mach/sdhci.h> |
||||
#include <malloc.h> |
||||
#include <sdhci.h> |
||||
|
||||
/*
|
||||
* The BCMSTB SDHCI has a quirk in that its actual maximum frequency |
||||
* capability is 100 MHz. The divisor that is eventually written to |
||||
* SDHCI_CLOCK_CONTROL is calculated based on what the MMC device |
||||
* reports, and relative to this maximum frequency. |
||||
* |
||||
* This define used to be set to 52000000 (52 MHz), the desired |
||||
* maximum frequency, but that would result in the communication |
||||
* actually running at 100 MHz (seemingly without issue), which is |
||||
* out-of-spec. |
||||
* |
||||
* Now, by setting this to 0 (auto-detect), 100 MHz will be read from |
||||
* the capabilities register, and the resulting divisor will be |
||||
* doubled, meaning that the clock control register will be set to the |
||||
* in-spec 52 MHz value. |
||||
*/ |
||||
#define BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY 0 |
||||
/*
|
||||
* When the minimum clock frequency is set to 0 (auto-detect), U-Boot |
||||
* sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz, |
||||
* which results in the controller timing out when trying to |
||||
* communicate with the MMC device. Hard-code this value to 400000 |
||||
* (400 kHz) to prevent this. |
||||
*/ |
||||
#define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000 |
||||
|
||||
static char *BCMSTB_SDHCI_NAME = "bcmstb-sdhci"; |
||||
|
||||
/*
|
||||
* This driver has only been tested with eMMC devices; SD devices may |
||||
* not work. |
||||
*/ |
||||
int bcmstb_sdhci_init(phys_addr_t regbase) |
||||
{ |
||||
struct sdhci_host *host = NULL; |
||||
|
||||
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); |
||||
if (!host) { |
||||
printf("%s: Failed to allocate memory\n", __func__); |
||||
return 1; |
||||
} |
||||
memset(host, 0, sizeof(*host)); |
||||
|
||||
host->name = BCMSTB_SDHCI_NAME; |
||||
host->ioaddr = (void *)regbase; |
||||
host->quirks = 0; |
||||
|
||||
host->cfg.part_type = PART_TYPE_DOS; |
||||
|
||||
host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
||||
|
||||
return add_sdhci(host, |
||||
BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY, |
||||
BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY); |
||||
} |
||||
@ -0,0 +1,439 @@ |
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2018 Cisco Systems, Inc. |
||||
* |
||||
* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
||||
*/ |
||||
|
||||
#include <asm/io.h> |
||||
#include <command.h> |
||||
#include <config.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <fdtdec.h> |
||||
#include <linux/bitops.h> |
||||
#include <linux/delay.h> |
||||
#include <log.h> |
||||
#include <malloc.h> |
||||
#include <spi.h> |
||||
#include <time.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define SPBR_MIN 8 |
||||
#define BITS_PER_WORD 8 |
||||
|
||||
#define NUM_TXRAM 32 |
||||
#define NUM_RXRAM 32 |
||||
#define NUM_CDRAM 16 |
||||
|
||||
/* hif_mspi register structure. */ |
||||
struct bcmstb_hif_mspi_regs { |
||||
u32 spcr0_lsb; /* 0x000 */ |
||||
u32 spcr0_msb; /* 0x004 */ |
||||
u32 spcr1_lsb; /* 0x008 */ |
||||
u32 spcr1_msb; /* 0x00c */ |
||||
u32 newqp; /* 0x010 */ |
||||
u32 endqp; /* 0x014 */ |
||||
u32 spcr2; /* 0x018 */ |
||||
u32 reserved0; /* 0x01c */ |
||||
u32 mspi_status; /* 0x020 */ |
||||
u32 cptqp; /* 0x024 */ |
||||
u32 spcr3; /* 0x028 */ |
||||
u32 revision; /* 0x02c */ |
||||
u32 reserved1[4]; /* 0x030 */ |
||||
u32 txram[NUM_TXRAM]; /* 0x040 */ |
||||
u32 rxram[NUM_RXRAM]; /* 0x0c0 */ |
||||
u32 cdram[NUM_CDRAM]; /* 0x140 */ |
||||
u32 write_lock; /* 0x180 */ |
||||
}; |
||||
|
||||
/* hif_mspi masks. */ |
||||
#define HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK 0x00000080 |
||||
#define HIF_MSPI_SPCR2_SPE_MASK 0x00000040 |
||||
#define HIF_MSPI_SPCR2_SPIFIE_MASK 0x00000020 |
||||
#define HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK 0x00000001 |
||||
|
||||
/* bspi offsets. */ |
||||
#define BSPI_MAST_N_BOOT_CTRL 0x008 |
||||
|
||||
/* bspi_raf is not used in this driver. */ |
||||
|
||||
/* hif_spi_intr2 offsets and masks. */ |
||||
#define HIF_SPI_INTR2_CPU_CLEAR 0x08 |
||||
#define HIF_SPI_INTR2_CPU_MASK_SET 0x10 |
||||
#define HIF_SPI_INTR2_CPU_MASK_CLEAR 0x14 |
||||
#define HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK 0x00000020 |
||||
|
||||
/* SPI transfer timeout in milliseconds. */ |
||||
#define HIF_MSPI_WAIT 10 |
||||
|
||||
enum bcmstb_base_type { |
||||
HIF_MSPI, |
||||
BSPI, |
||||
HIF_SPI_INTR2, |
||||
CS_REG, |
||||
BASE_LAST, |
||||
}; |
||||
|
||||
struct bcmstb_spi_platdata { |
||||
void *base[4]; |
||||
}; |
||||
|
||||
struct bcmstb_spi_priv { |
||||
struct bcmstb_hif_mspi_regs *regs; |
||||
void *bspi; |
||||
void *hif_spi_intr2; |
||||
void *cs_reg; |
||||
int default_cs; |
||||
int curr_cs; |
||||
uint tx_slot; |
||||
uint rx_slot; |
||||
u8 saved_cmd[NUM_CDRAM]; |
||||
uint saved_cmd_len; |
||||
void *saved_din_addr; |
||||
}; |
||||
|
||||
static int bcmstb_spi_ofdata_to_platdata(struct udevice *bus) |
||||
{ |
||||
struct bcmstb_spi_platdata *plat = dev_get_platdata(bus); |
||||
const void *fdt = gd->fdt_blob; |
||||
int node = dev_of_offset(bus); |
||||
int ret = 0; |
||||
int i = 0; |
||||
struct fdt_resource resource = { 0 }; |
||||
char *names[BASE_LAST] = { "hif_mspi", "bspi", "hif_spi_intr2", |
||||
"cs_reg" }; |
||||
const phys_addr_t defaults[BASE_LAST] = { BCMSTB_HIF_MSPI_BASE, |
||||
BCMSTB_BSPI_BASE, |
||||
BCMSTB_HIF_SPI_INTR2, |
||||
BCMSTB_CS_REG }; |
||||
|
||||
for (i = 0; i < BASE_LAST; i++) { |
||||
plat->base[i] = (void *)defaults[i]; |
||||
|
||||
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", |
||||
names[i], &resource); |
||||
if (ret) { |
||||
printf("%s: Assuming BCMSTB SPI %s address 0x0x%p\n", |
||||
__func__, names[i], (void *)defaults[i]); |
||||
} else { |
||||
plat->base[i] = (void *)resource.start; |
||||
debug("BCMSTB SPI %s address: 0x0x%p\n", |
||||
names[i], (void *)plat->base[i]); |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void bcmstb_spi_hw_set_parms(struct bcmstb_spi_priv *priv) |
||||
{ |
||||
writel(SPBR_MIN, &priv->regs->spcr0_lsb); |
||||
writel(BITS_PER_WORD << 2 | SPI_MODE_3, &priv->regs->spcr0_msb); |
||||
} |
||||
|
||||
static void bcmstb_spi_enable_interrupt(void *base, u32 mask) |
||||
{ |
||||
void *reg = base + HIF_SPI_INTR2_CPU_MASK_CLEAR; |
||||
|
||||
writel(readl(reg) | mask, reg); |
||||
readl(reg); |
||||
} |
||||
|
||||
static void bcmstb_spi_disable_interrupt(void *base, u32 mask) |
||||
{ |
||||
void *reg = base + HIF_SPI_INTR2_CPU_MASK_SET; |
||||
|
||||
writel(readl(reg) | mask, reg); |
||||
readl(reg); |
||||
} |
||||
|
||||
static void bcmstb_spi_clear_interrupt(void *base, u32 mask) |
||||
{ |
||||
void *reg = base + HIF_SPI_INTR2_CPU_CLEAR; |
||||
|
||||
writel(readl(reg) | mask, reg); |
||||
readl(reg); |
||||
} |
||||
|
||||
static int bcmstb_spi_probe(struct udevice *bus) |
||||
{ |
||||
struct bcmstb_spi_platdata *plat = dev_get_platdata(bus); |
||||
struct bcmstb_spi_priv *priv = dev_get_priv(bus); |
||||
|
||||
priv->regs = plat->base[HIF_MSPI]; |
||||
priv->bspi = plat->base[BSPI]; |
||||
priv->hif_spi_intr2 = plat->base[HIF_SPI_INTR2]; |
||||
priv->cs_reg = plat->base[CS_REG]; |
||||
priv->default_cs = 0; |
||||
priv->curr_cs = -1; |
||||
priv->tx_slot = 0; |
||||
priv->rx_slot = 0; |
||||
memset(priv->saved_cmd, 0, NUM_CDRAM); |
||||
priv->saved_cmd_len = 0; |
||||
priv->saved_din_addr = NULL; |
||||
|
||||
debug("spi_xfer: tx regs: 0x%p\n", &priv->regs->txram[0]); |
||||
debug("spi_xfer: rx regs: 0x%p\n", &priv->regs->rxram[0]); |
||||
|
||||
/* Disable BSPI. */ |
||||
writel(1, priv->bspi + BSPI_MAST_N_BOOT_CTRL); |
||||
readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL); |
||||
|
||||
/* Set up interrupts. */ |
||||
bcmstb_spi_disable_interrupt(priv->hif_spi_intr2, 0xffffffff); |
||||
bcmstb_spi_clear_interrupt(priv->hif_spi_intr2, 0xffffffff); |
||||
bcmstb_spi_enable_interrupt(priv->hif_spi_intr2, |
||||
HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK); |
||||
|
||||
/* Set up control registers. */ |
||||
writel(0, &priv->regs->spcr1_lsb); |
||||
writel(0, &priv->regs->spcr1_msb); |
||||
writel(0, &priv->regs->newqp); |
||||
writel(0, &priv->regs->endqp); |
||||
writel(HIF_MSPI_SPCR2_SPIFIE_MASK, &priv->regs->spcr2); |
||||
writel(0, &priv->regs->spcr3); |
||||
|
||||
bcmstb_spi_hw_set_parms(priv); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void bcmstb_spi_submit(struct bcmstb_spi_priv *priv, bool done) |
||||
{ |
||||
debug("WR NEWQP: %d\n", 0); |
||||
writel(0, &priv->regs->newqp); |
||||
|
||||
debug("WR ENDQP: %d\n", priv->tx_slot - 1); |
||||
writel(priv->tx_slot - 1, &priv->regs->endqp); |
||||
|
||||
if (done) { |
||||
debug("WR CDRAM[%d]: %02x\n", priv->tx_slot - 1, |
||||
readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80); |
||||
writel(readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80, |
||||
&priv->regs->cdram[priv->tx_slot - 1]); |
||||
} |
||||
|
||||
/* Force chip select first time. */ |
||||
if (priv->curr_cs != priv->default_cs) { |
||||
debug("spi_xfer: switching chip select to %d\n", |
||||
priv->default_cs); |
||||
writel((readl(priv->cs_reg) & ~0xff) | (1 << priv->default_cs), |
||||
priv->cs_reg); |
||||
readl(priv->cs_reg); |
||||
udelay(10); |
||||
priv->curr_cs = priv->default_cs; |
||||
} |
||||
|
||||
debug("WR WRITE_LOCK: %02x\n", 1); |
||||
writel((readl(&priv->regs->write_lock) & |
||||
~HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK) | 1, |
||||
&priv->regs->write_lock); |
||||
readl(&priv->regs->write_lock); |
||||
|
||||
debug("WR SPCR2: %02x\n", |
||||
HIF_MSPI_SPCR2_SPIFIE_MASK | |
||||
HIF_MSPI_SPCR2_SPE_MASK | |
||||
HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK); |
||||
writel(HIF_MSPI_SPCR2_SPIFIE_MASK | |
||||
HIF_MSPI_SPCR2_SPE_MASK | |
||||
HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK, |
||||
&priv->regs->spcr2); |
||||
} |
||||
|
||||
static int bcmstb_spi_wait(struct bcmstb_spi_priv *priv) |
||||
{ |
||||
u32 start_time = get_timer(0); |
||||
u32 status = readl(&priv->regs->mspi_status); |
||||
|
||||
while (!(status & 1)) { |
||||
if (get_timer(start_time) > HIF_MSPI_WAIT) |
||||
return -ETIMEDOUT; |
||||
status = readl(&priv->regs->mspi_status); |
||||
} |
||||
|
||||
writel(readl(&priv->regs->mspi_status) & ~1, &priv->regs->mspi_status); |
||||
bcmstb_spi_clear_interrupt(priv->hif_spi_intr2, |
||||
HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int bcmstb_spi_xfer(struct udevice *dev, unsigned int bitlen, |
||||
const void *dout, void *din, unsigned long flags) |
||||
{ |
||||
uint len = bitlen / 8; |
||||
uint tx_len = len; |
||||
uint rx_len = len; |
||||
const u8 *out_bytes = (u8 *)dout; |
||||
u8 *in_bytes = (u8 *)din; |
||||
struct udevice *bus = dev_get_parent(dev); |
||||
struct bcmstb_spi_priv *priv = dev_get_priv(bus); |
||||
struct bcmstb_hif_mspi_regs *regs = priv->regs; |
||||
|
||||
debug("spi_xfer: %d, t: 0x%p, r: 0x%p, f: %lx\n", |
||||
len, dout, din, flags); |
||||
debug("spi_xfer: chip select: %x\n", readl(priv->cs_reg) & 0xff); |
||||
debug("spi_xfer: tx addr: 0x%p\n", ®s->txram[0]); |
||||
debug("spi_xfer: rx addr: 0x%p\n", ®s->rxram[0]); |
||||
debug("spi_xfer: cd addr: 0x%p\n", ®s->cdram[0]); |
||||
|
||||
if (flags & SPI_XFER_END) { |
||||
debug("spi_xfer: clearing saved din address: 0x%p\n", |
||||
priv->saved_din_addr); |
||||
priv->saved_din_addr = NULL; |
||||
priv->saved_cmd_len = 0; |
||||
memset(priv->saved_cmd, 0, NUM_CDRAM); |
||||
} |
||||
|
||||
if (bitlen == 0) |
||||
return 0; |
||||
|
||||
if (bitlen % 8) { |
||||
printf("%s: Non-byte-aligned transfer\n", __func__); |
||||
return -EOPNOTSUPP; |
||||
} |
||||
|
||||
if (flags & ~(SPI_XFER_BEGIN | SPI_XFER_END)) { |
||||
printf("%s: Unsupported flags: %lx\n", __func__, flags); |
||||
return -EOPNOTSUPP; |
||||
} |
||||
|
||||
if (flags & SPI_XFER_BEGIN) { |
||||
priv->tx_slot = 0; |
||||
priv->rx_slot = 0; |
||||
|
||||
if (out_bytes && len > NUM_CDRAM) { |
||||
printf("%s: Unable to save transfer\n", __func__); |
||||
return -EOPNOTSUPP; |
||||
} |
||||
|
||||
if (out_bytes && !(flags & SPI_XFER_END)) { |
||||
/*
|
||||
* This is the start of a transmit operation |
||||
* that will need repeating if the calling |
||||
* code polls for the result. Save it for |
||||
* subsequent transmission. |
||||
*/ |
||||
debug("spi_xfer: saving command: %x, %d\n", |
||||
out_bytes[0], len); |
||||
priv->saved_cmd_len = len; |
||||
memcpy(priv->saved_cmd, out_bytes, priv->saved_cmd_len); |
||||
} |
||||
} |
||||
|
||||
if (!(flags & (SPI_XFER_BEGIN | SPI_XFER_END))) { |
||||
if (priv->saved_din_addr == din) { |
||||
/*
|
||||
* The caller is polling for status. Repeat |
||||
* the last transmission. |
||||
*/ |
||||
int ret = 0; |
||||
|
||||
debug("spi_xfer: Making recursive call\n"); |
||||
ret = bcmstb_spi_xfer(dev, priv->saved_cmd_len * 8, |
||||
priv->saved_cmd, NULL, |
||||
SPI_XFER_BEGIN); |
||||
if (ret) { |
||||
printf("%s: Recursive call failed\n", __func__); |
||||
return ret; |
||||
} |
||||
} else { |
||||
debug("spi_xfer: saving din address: 0x%p\n", din); |
||||
priv->saved_din_addr = din; |
||||
} |
||||
} |
||||
|
||||
while (rx_len > 0) { |
||||
priv->rx_slot = priv->tx_slot; |
||||
|
||||
while (priv->tx_slot < NUM_CDRAM && tx_len > 0) { |
||||
bcmstb_spi_hw_set_parms(priv); |
||||
debug("WR TXRAM[%d]: %02x\n", priv->tx_slot, |
||||
out_bytes ? out_bytes[len - tx_len] : 0xff); |
||||
writel(out_bytes ? out_bytes[len - tx_len] : 0xff, |
||||
®s->txram[priv->tx_slot << 1]); |
||||
debug("WR CDRAM[%d]: %02x\n", priv->tx_slot, 0x8e); |
||||
writel(0x8e, ®s->cdram[priv->tx_slot]); |
||||
priv->tx_slot++; |
||||
tx_len--; |
||||
if (!in_bytes) |
||||
rx_len--; |
||||
} |
||||
|
||||
debug("spi_xfer: early return clauses: %d, %d, %d\n", |
||||
len <= NUM_CDRAM, |
||||
!in_bytes, |
||||
(flags & (SPI_XFER_BEGIN | |
||||
SPI_XFER_END)) == SPI_XFER_BEGIN); |
||||
if (len <= NUM_CDRAM && |
||||
!in_bytes && |
||||
(flags & (SPI_XFER_BEGIN | SPI_XFER_END)) == SPI_XFER_BEGIN) |
||||
return 0; |
||||
|
||||
bcmstb_spi_submit(priv, tx_len == 0); |
||||
|
||||
if (bcmstb_spi_wait(priv) == -ETIMEDOUT) { |
||||
printf("%s: Timed out\n", __func__); |
||||
return -ETIMEDOUT; |
||||
} |
||||
|
||||
priv->tx_slot %= NUM_CDRAM; |
||||
|
||||
if (in_bytes) { |
||||
while (priv->rx_slot < NUM_CDRAM && rx_len > 0) { |
||||
in_bytes[len - rx_len] = |
||||
readl(®s->rxram[(priv->rx_slot << 1) |
||||
+ 1]) |
||||
& 0xff; |
||||
debug("RD RXRAM[%d]: %02x\n", |
||||
priv->rx_slot, in_bytes[len - rx_len]); |
||||
priv->rx_slot++; |
||||
rx_len--; |
||||
} |
||||
} |
||||
} |
||||
|
||||
if (flags & SPI_XFER_END) { |
||||
debug("WR WRITE_LOCK: %02x\n", 0); |
||||
writel((readl(&priv->regs->write_lock) & |
||||
~HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK) | 0, |
||||
&priv->regs->write_lock); |
||||
readl(&priv->regs->write_lock); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int bcmstb_spi_set_speed(struct udevice *dev, uint speed) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
static int bcmstb_spi_set_mode(struct udevice *dev, uint mode) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
static const struct dm_spi_ops bcmstb_spi_ops = { |
||||
.xfer = bcmstb_spi_xfer, |
||||
.set_speed = bcmstb_spi_set_speed, |
||||
.set_mode = bcmstb_spi_set_mode, |
||||
}; |
||||
|
||||
static const struct udevice_id bcmstb_spi_id[] = { |
||||
{ .compatible = "brcm,spi-brcmstb" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(bcmstb_spi) = { |
||||
.name = "bcmstb_spi", |
||||
.id = UCLASS_SPI, |
||||
.of_match = bcmstb_spi_id, |
||||
.ops = &bcmstb_spi_ops, |
||||
.ofdata_to_platdata = bcmstb_spi_ofdata_to_platdata, |
||||
.probe = bcmstb_spi_probe, |
||||
.platdata_auto_alloc_size = sizeof(struct bcmstb_spi_platdata), |
||||
.priv_auto_alloc_size = sizeof(struct bcmstb_spi_priv), |
||||
}; |
||||
@ -0,0 +1,26 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/*
|
||||
* (C) Copyright 2018 Cisco Systems, Inc. |
||||
* |
||||
* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
||||
* |
||||
* Configuration settings for the Broadcom BCM7445 SoC family. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include "bcmstb.h" |
||||
|
||||
#define CONFIG_SYS_NS16550_COM3 0xf040ab00 |
||||
|
||||
#define BCMSTB_SDHCI_BASE 0xf03e0200 |
||||
#define BCMSTB_TIMER_LOW 0xf0412008 |
||||
#define BCMSTB_TIMER_HIGH 0xf041200c |
||||
#define BCMSTB_TIMER_FREQUENCY 0xf0412020 |
||||
#define BCMSTB_HIF_MSPI_BASE 0xf03e3400 |
||||
#define BCMSTB_BSPI_BASE 0xf03e3200 |
||||
#define BCMSTB_HIF_SPI_INTR2 0xf03e1a00 |
||||
#define BCMSTB_CS_REG 0xf03e0920 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,183 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/*
|
||||
* (C) Copyright 2018 Cisco Systems, Inc. |
||||
* |
||||
* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
||||
* |
||||
* Configuration settings for the Broadcom BCMSTB SoC family. |
||||
*/ |
||||
|
||||
#ifndef __BCMSTB_H |
||||
#define __BCMSTB_H |
||||
|
||||
#include "version.h" |
||||
#include <linux/sizes.h> |
||||
#include <asm/arch/prior_stage.h> |
||||
|
||||
/*
|
||||
* Generic board configuration. |
||||
*/ |
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
|
||||
/*
|
||||
* CPU configuration. |
||||
*/ |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
/*
|
||||
* Memory configuration. |
||||
* |
||||
* The prior stage BOLT bootloader sets up memory for us. |
||||
* |
||||
* An example boot memory layout after loading everything is: |
||||
* |
||||
* 0x0000 8000 vmlinux.bin.gz |
||||
* : [~31 MiB uncompressed max] |
||||
* 0x01ef f000 FIT containing signed public key |
||||
* : [~2 KiB in size] |
||||
* 0x01f0 0000 DTB copied from prior-stage-provided region |
||||
* : [~1 MiB max] |
||||
* 0x0200 0000 FIT containing ramdisk and device tree |
||||
* : initramfs.cpio.gz |
||||
* : [~208 MiB uncompressed max, to CMA/bmem low address] |
||||
* : [~80 MiB compressed max, to PSB low address] |
||||
* : device tree binary |
||||
* : [~60 KiB] |
||||
* 0x0700 0000 Prior stage bootloader (PSB) |
||||
* : |
||||
* 0x0761 7000 Prior-stage-provided device tree binary (DTB) |
||||
* : [~40 KiB in size] |
||||
* 0x0f00 0000 Contiguous memory allocator (CMA/bmem) low address |
||||
* : |
||||
* 0x8010 0000 U-Boot code at ELF load address |
||||
* : [~500 KiB in size, stripped] |
||||
* 0xc000 0000 Top of RAM |
||||
* |
||||
* Setting gd->relocaddr to CONFIG_SYS_TEXT_BASE in dram_init_banksize |
||||
* prevents U-Boot from relocating itself when it is run as an ELF |
||||
* program by the prior stage bootloader. |
||||
* |
||||
* We want to keep the ramdisk and FDT in the FIT image in-place, to |
||||
* accommodate stblinux's bmem and CMA regions. To accomplish this, |
||||
* we set initrd_high and fdt_high to 0xffffffff, and the load and |
||||
* entry addresses of the FIT ramdisk entry to 0x0. |
||||
* |
||||
* Overwriting the prior stage bootloader causes memory instability, |
||||
* so the compressed initramfs needs to fit between the load address |
||||
* and the PSB low address. In BOLT's default configuration this |
||||
* limits the compressed size of the initramfs to approximately 80 |
||||
* MiB. However, BOLT can be configured to allow loading larger |
||||
* initramfs images, in which case this limitation is eliminated. |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 3 |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x80100000 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_MALLOC_LEN ((10 * 1024) << 10) /* 10 MiB */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 |
||||
|
||||
/*
|
||||
* CONFIG_SYS_LOAD_ADDR - 1 MiB. |
||||
*/ |
||||
#define CONFIG_SYS_FDT_SAVE_ADDRESS 0x1f00000 |
||||
#define CONFIG_SYS_CBSIZE 512 |
||||
#define CONFIG_SYS_MAXARGS 32 |
||||
|
||||
/*
|
||||
* Large kernel image bootm configuration. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTM_LEN SZ_64M |
||||
|
||||
/*
|
||||
* NS16550 configuration. |
||||
*/ |
||||
#define V_NS16550_CLK 81000000 |
||||
|
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
||||
|
||||
/*
|
||||
* Serial console configuration. |
||||
*/ |
||||
#define CONFIG_SERIAL3 3 |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ |
||||
115200} |
||||
|
||||
/*
|
||||
* Informational display configuration. |
||||
*/ |
||||
#define CONFIG_REVISION_TAG |
||||
|
||||
/*
|
||||
* Command configuration. |
||||
*/ |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_CMD_SPI |
||||
#define CONFIG_CMD_SF_TEST |
||||
#define CONFIG_CMD_MMC |
||||
|
||||
/*
|
||||
* Flash configuration. |
||||
*/ |
||||
#define CONFIG_ST_SMI |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#define CONFIG_SPI_FLASH_MACRONIX |
||||
|
||||
/*
|
||||
* Filesystem configuration. |
||||
*/ |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_EXT4 |
||||
#define CONFIG_FS_EXT4 |
||||
#define CONFIG_CMD_FS_GENERIC |
||||
|
||||
/*
|
||||
* Environment configuration. |
||||
*/ |
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
||||
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH 1 |
||||
#define CONFIG_ENV_OFFSET 0x1e0000 |
||||
#define CONFIG_ENV_SIZE (64 << 10) /* 64 KiB */ |
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* Save the prior stage provided DTB. |
||||
*/ |
||||
#define CONFIG_PREBOOT \ |
||||
"fdt addr ${fdtcontroladdr};" \
|
||||
"fdt move ${fdtcontroladdr} ${fdtsaveaddr};" \
|
||||
"fdt addr ${fdtsaveaddr};" |
||||
/*
|
||||
* Enable in-place RFS with this initrd_high setting. |
||||
*/ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"fdtsaveaddr=" __stringify(CONFIG_SYS_FDT_SAVE_ADDRESS) "\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_high=0xffffffff\0" |
||||
|
||||
/*
|
||||
* Set fdtaddr to prior stage-provided DTB in board_late_init, when |
||||
* writeable environment is available. |
||||
*/ |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
|
||||
#define CONFIG_DM_SPI 1 |
||||
|
||||
#endif /* __BCMSTB_H */ |
||||
Loading…
Reference in new issue