- Fix mkimage recognition - Update all my fragments ZynqMP: - Use clk driver - Support loading elfs in el1 - Various DTS and defconfig changes - Enable newer pmufw versions - Support more clocks - Remove ep108 - Secure image support - Fix memtest setup Zynq: - Enabling watchdog driver - Support more clocks - defconfig changes fpga: - Simplify error path net: - GMII case update -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlq1D5kACgkQykllyylKDCHt5gCaA4AhhC+BPrFvD8cTFKPix7vq ctYAnA63Ye8IkvyOhgn3QwBL5+YXbsVP =7++x -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2018.05' of git://git.denx.de/u-boot-microblaze Xilinx changes for v2018.05 - Fix mkimage recognition - Update all my fragments ZynqMP: - Use clk driver - Support loading elfs in el1 - Various DTS and defconfig changes - Enable newer pmufw versions - Support more clocks - Remove ep108 - Secure image support - Fix memtest setup Zynq: - Enabling watchdog driver - Support more clocks - defconfig changes fpga: - Simplify error path net: - GMII case updatemaster
Tom Rini
6 years ago
commit
89a650e0ff
@ -0,0 +1,290 @@ |
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/* |
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* Clock specification for Xilinx ZynqMP |
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* |
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* (C) Copyright 2017, Xilinx, Inc. |
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* |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/ { |
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fclk0: fclk0 { |
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status = "disabled"; |
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compatible = "xlnx,fclk"; |
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clocks = <&clkc 71>; |
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}; |
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|
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fclk1: fclk1 { |
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status = "disabled"; |
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compatible = "xlnx,fclk"; |
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clocks = <&clkc 72>; |
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}; |
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|
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fclk2: fclk2 { |
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status = "disabled"; |
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compatible = "xlnx,fclk"; |
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clocks = <&clkc 73>; |
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}; |
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|
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fclk3: fclk3 { |
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status = "disabled"; |
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compatible = "xlnx,fclk"; |
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clocks = <&clkc 74>; |
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}; |
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|
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pss_ref_clk: pss_ref_clk { |
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u-boot,dm-pre-reloc; |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <33333333>; |
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}; |
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|
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video_clk: video_clk { |
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u-boot,dm-pre-reloc; |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <27000000>; |
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}; |
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pss_alt_ref_clk: pss_alt_ref_clk { |
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u-boot,dm-pre-reloc; |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <0>; |
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}; |
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|
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gt_crx_ref_clk: gt_crx_ref_clk { |
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u-boot,dm-pre-reloc; |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <108000000>; |
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}; |
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|
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aux_ref_clk: aux_ref_clk { |
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u-boot,dm-pre-reloc; |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <27000000>; |
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}; |
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|
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clkc: clkc { |
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u-boot,dm-pre-reloc; |
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#clock-cells = <1>; |
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compatible = "xlnx,zynqmp-clkc"; |
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clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; |
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clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; |
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clock-output-names = "iopll", "rpll", "apll", "dpll", |
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"vpll", "iopll_to_fpd", "rpll_to_fpd", |
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"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", |
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"acpu", "acpu_half", "dbf_fpd", "dbf_lpd", |
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"dbg_trace", "dbg_tstmp", "dp_video_ref", |
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"dp_audio_ref", "dp_stc_ref", "gdma_ref", |
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"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", |
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"gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", |
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"topsw_main", "topsw_lsbus", "gtgref0_ref", |
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"lpd_switch", "lpd_lsbus", "usb0_bus_ref", |
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"usb1_bus_ref", "usb3_dual_ref", "usb0", |
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"usb1", "cpu_r5", "cpu_r5_core", "csu_spb", |
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"csu_pll", "pcap", "iou_switch", "gem_tsu_ref", |
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"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", |
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"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", |
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"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", |
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"uart0_ref", "uart1_ref", "spi0_ref", |
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"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", |
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"can0_ref", "can1_ref", "can0", "can1", |
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"dll_ref", "adma_ref", "timestamp_ref", |
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"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; |
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}; |
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dp_aclk: dp_aclk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <100000000>; |
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clock-accuracy = <100>; |
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}; |
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}; |
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&can0 { |
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clocks = <&clkc 63>, <&clkc 31>; |
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}; |
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&can1 { |
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clocks = <&clkc 64>, <&clkc 31>; |
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}; |
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&cpu0 { |
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clocks = <&clkc 10>; |
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}; |
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&fpd_dma_chan1 { |
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clocks = <&clkc 19>, <&clkc 31>; |
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}; |
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&fpd_dma_chan2 { |
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clocks = <&clkc 19>, <&clkc 31>; |
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}; |
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&fpd_dma_chan3 { |
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clocks = <&clkc 19>, <&clkc 31>; |
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}; |
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|
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&fpd_dma_chan4 { |
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clocks = <&clkc 19>, <&clkc 31>; |
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}; |
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&fpd_dma_chan5 { |
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clocks = <&clkc 19>, <&clkc 31>; |
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}; |
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&fpd_dma_chan6 { |
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clocks = <&clkc 19>, <&clkc 31>; |
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}; |
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|
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&fpd_dma_chan7 { |
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clocks = <&clkc 19>, <&clkc 31>; |
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}; |
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|
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&fpd_dma_chan8 { |
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clocks = <&clkc 19>, <&clkc 31>; |
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}; |
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&gpu { |
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clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>; |
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}; |
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&lpd_dma_chan1 { |
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clocks = <&clkc 68>, <&clkc 31>; |
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}; |
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&lpd_dma_chan2 { |
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clocks = <&clkc 68>, <&clkc 31>; |
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}; |
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&lpd_dma_chan3 { |
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clocks = <&clkc 68>, <&clkc 31>; |
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}; |
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&lpd_dma_chan4 { |
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clocks = <&clkc 68>, <&clkc 31>; |
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}; |
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&lpd_dma_chan5 { |
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clocks = <&clkc 68>, <&clkc 31>; |
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}; |
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&lpd_dma_chan6 { |
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clocks = <&clkc 68>, <&clkc 31>; |
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}; |
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&lpd_dma_chan7 { |
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clocks = <&clkc 68>, <&clkc 31>; |
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}; |
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&lpd_dma_chan8 { |
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clocks = <&clkc 68>, <&clkc 31>; |
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}; |
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&nand0 { |
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clocks = <&clkc 60>, <&clkc 31>; |
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}; |
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&gem0 { |
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clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>; |
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; |
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}; |
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&gem1 { |
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clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>; |
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; |
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}; |
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|
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&gem2 { |
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clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>; |
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; |
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}; |
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|
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&gem3 { |
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clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>; |
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; |
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}; |
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|
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&gpio { |
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clocks = <&clkc 31>; |
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}; |
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&i2c0 { |
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clocks = <&clkc 61>; |
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}; |
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|
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&i2c1 { |
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clocks = <&clkc 62>; |
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}; |
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|
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&pcie { |
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clocks = <&clkc 23>; |
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}; |
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&qspi { |
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clocks = <&clkc 53>, <&clkc 31>; |
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}; |
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&sata { |
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clocks = <&clkc 22>; |
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}; |
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|
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&sdhci0 { |
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clocks = <&clkc 54>, <&clkc 31>; |
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}; |
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&sdhci1 { |
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clocks = <&clkc 55>, <&clkc 31>; |
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}; |
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&spi0 { |
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clocks = <&clkc 58>, <&clkc 31>; |
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}; |
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&spi1 { |
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clocks = <&clkc 59>, <&clkc 31>; |
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}; |
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|
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&uart0 { |
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clocks = <&clkc 56>, <&clkc 31>; |
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}; |
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&uart1 { |
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clocks = <&clkc 57>, <&clkc 31>; |
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}; |
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|
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&usb0 { |
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clocks = <&clkc 32>, <&clkc 34>; |
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}; |
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|
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&usb1 { |
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clocks = <&clkc 33>, <&clkc 34>; |
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}; |
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|
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&watchdog0 { |
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clocks = <&clkc 75>; |
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}; |
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&xilinx_ams { |
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clocks = <&clkc 70>; |
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}; |
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&xilinx_drm { |
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clocks = <&clkc 16>; |
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}; |
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|
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&xlnx_dp { |
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clocks = <&dp_aclk>, <&clkc 17>; |
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}; |
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&xlnx_dpdma { |
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clocks = <&clkc 20>; |
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}; |
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|
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&xlnx_dp_snd_codec0 { |
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clocks = <&clkc 17>; |
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}; |
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@ -1,172 +0,0 @@ |
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/* |
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* clock specification for Xilinx ZynqMP ep108 development board |
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* |
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* (C) Copyright 2015, Xilinx, Inc. |
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* |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/ { |
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misc_clk: misc_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <25000000>; |
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u-boot,dm-pre-reloc; |
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}; |
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i2c_clk: i2c_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0x0>; |
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clock-frequency = <111111111>; |
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}; |
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|
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sata_clk: sata_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <75000000>; |
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}; |
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|
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dp_aclk: clock0 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <50000000>; |
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clock-accuracy = <100>; |
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}; |
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clk100: clk100 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <100000000>; |
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}; |
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clk600: clk600 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <600000000>; |
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}; |
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dp_aud_clk: clock1 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <22579200>; |
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clock-accuracy = <100>; |
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}; |
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}; |
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|
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&can0 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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|
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&can1 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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|
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&fpd_dma_chan1 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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|
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&fpd_dma_chan2 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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|
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&fpd_dma_chan3 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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|
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&fpd_dma_chan4 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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|
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&fpd_dma_chan5 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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|
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&fpd_dma_chan6 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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|
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&fpd_dma_chan7 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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|
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&fpd_dma_chan8 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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|
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&gem0 { |
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clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; |
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}; |
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|
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&gpio { |
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clocks = <&misc_clk>; |
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}; |
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|
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&i2c0 { |
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clocks = <&i2c_clk>; |
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}; |
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|
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&i2c1 { |
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clocks = <&i2c_clk>; |
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}; |
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|
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&nand0 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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|
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&qspi { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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|
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&sata { |
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clocks = <&sata_clk>; |
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}; |
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|
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&sdhci0 { |
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clocks = <&misc_clk>, <&misc_clk>; |
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}; |
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|
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&sdhci1 { |
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clocks = <&misc_clk>, <&misc_clk>; |
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}; |
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|
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&spi0 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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|
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&spi1 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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|
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&uart0 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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|
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&usb0 { |
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clocks = <&misc_clk>, <&misc_clk>; |
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}; |
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|
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&usb1 { |
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clocks = <&misc_clk>, <&misc_clk>; |
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}; |
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|
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&watchdog0 { |
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clocks= <&misc_clk>; |
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}; |
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|
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&xilinx_drm { |
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clocks = <&misc_clk>; |
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}; |
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|
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&xlnx_dp { |
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clocks = <&dp_aclk>, <&dp_aud_clk>; |
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}; |
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|
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&xlnx_dp_snd_codec0 { |
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clocks = <&dp_aud_clk>; |
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}; |
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|
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&xlnx_dpdma { |
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clocks = <&misc_clk>; |
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}; |
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@ -1,235 +0,0 @@ |
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/* |
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* dts file for Xilinx ZynqMP ep108 development board |
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* |
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* (C) Copyright 2014 - 2015, Xilinx, Inc. |
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* |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/dts-v1/; |
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|
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#include "zynqmp.dtsi" |
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#include "zynqmp-ep108-clk.dtsi" |
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|
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/ { |
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model = "ZynqMP EP108"; |
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|
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aliases { |
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ethernet0 = &gem0; |
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mmc0 = &sdhci0; |
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mmc1 = &sdhci1; |
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serial0 = &uart0; |
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spi0 = &qspi; |
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spi1 = &spi0; |
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spi2 = &spi1; |
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usb0 = &usb0; |
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usb1 = &usb1; |
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}; |
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|
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chosen { |
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bootargs = "earlycon"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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memory@0 { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x40000000>; |
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}; |
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}; |
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|
||||
&can0 { |
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status = "okay"; |
||||
}; |
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|
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&can1 { |
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status = "okay"; |
||||
}; |
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|
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&gem0 { |
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status = "okay"; |
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phy-handle = <&phy0>; |
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phy-mode = "rgmii-id"; |
||||
phy0: phy@0 { |
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reg = <0>; |
||||
max-speed = <100>; |
||||
}; |
||||
}; |
||||
|
||||
&gpio { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&i2c0 { |
||||
status = "okay"; |
||||
clock-frequency = <400000>; |
||||
eeprom@54 { |
||||
compatible = "atmel,24c64"; |
||||
reg = <0x54>; |
||||
}; |
||||
}; |
||||
|
||||
&i2c1 { |
||||
status = "okay"; |
||||
clock-frequency = <400000>; |
||||
eeprom@55 { |
||||
compatible = "atmel,24c64"; |
||||
reg = <0x55>; |
||||
}; |
||||
}; |
||||
|
||||
&nand0 { |
||||
status = "okay"; |
||||
arasan,has-mdma; |
||||
num-cs = <1>; |
||||
|
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partition@0 { /* for testing purpose */ |
||||
label = "nand-fsbl-uboot"; |
||||
reg = <0x0 0x0 0x400000>; |
||||
}; |
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partition@1 { /* for testing purpose */ |
||||
label = "nand-linux"; |
||||
reg = <0x0 0x400000 0x1400000>; |
||||
}; |
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partition@2 { /* for testing purpose */ |
||||
label = "nand-device-tree"; |
||||
reg = <0x0 0x1800000 0x400000>; |
||||
}; |
||||
partition@3 { /* for testing purpose */ |
||||
label = "nand-rootfs"; |
||||
reg = <0x0 0x1C00000 0x1400000>; |
||||
}; |
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partition@4 { /* for testing purpose */ |
||||
label = "nand-bitstream"; |
||||
reg = <0x0 0x3000000 0x400000>; |
||||
}; |
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partition@5 { /* for testing purpose */ |
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label = "nand-misc"; |
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reg = <0x0 0x3400000 0xFCC00000>; |
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}; |
||||
}; |
||||
|
||||
&qspi { |
||||
status = "okay"; |
||||
flash@0 { |
||||
compatible = "m25p80"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
reg = <0x0>; |
||||
spi-tx-bus-width = <1>; |
||||
spi-rx-bus-width = <4>; |
||||
spi-max-frequency = <10000000>; |
||||
partition@qspi-fsbl-uboot { /* for testing purpose */ |
||||
label = "qspi-fsbl-uboot"; |
||||
reg = <0x0 0x100000>; |
||||
}; |
||||
partition@qspi-linux { /* for testing purpose */ |
||||
label = "qspi-linux"; |
||||
reg = <0x100000 0x500000>; |
||||
}; |
||||
partition@qspi-device-tree { /* for testing purpose */ |
||||
label = "qspi-device-tree"; |
||||
reg = <0x600000 0x20000>; |
||||
}; |
||||
partition@qspi-rootfs { /* for testing purpose */ |
||||
label = "qspi-rootfs"; |
||||
reg = <0x620000 0x5E0000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&sata { |
||||
status = "okay"; |
||||
ceva,broken-gen2; |
||||
/* SATA Phy OOB timing settings */ |
||||
ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; |
||||
ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; |
||||
ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; |
||||
ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; |
||||
ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; |
||||
ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; |
||||
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; |
||||
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; |
||||
}; |
||||
|
||||
&sdhci0 { |
||||
status = "okay"; |
||||
bus-width = <8>; |
||||
xlnx,mio_bank = <2>; |
||||
}; |
||||
|
||||
&sdhci1 { |
||||
status = "okay"; |
||||
xlnx,mio_bank = <1>; |
||||
}; |
||||
|
||||
&spi0 { |
||||
status = "okay"; |
||||
num-cs = <1>; |
||||
spi0_flash0: spi0_flash0@0 { |
||||
compatible = "m25p80"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
spi-max-frequency = <50000000>; |
||||
reg = <0>; |
||||
|
||||
spi0_flash0@0 { |
||||
label = "spi0_flash0"; |
||||
reg = <0x0 0x100000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&spi1 { |
||||
status = "okay"; |
||||
num-cs = <1>; |
||||
spi1_flash0: spi1_flash0@0 { |
||||
compatible = "m25p80"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
spi-max-frequency = <50000000>; |
||||
reg = <0>; |
||||
|
||||
spi1_flash0@0 { |
||||
label = "spi1_flash0"; |
||||
reg = <0x0 0x100000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&uart0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&dwc3_0 { |
||||
status = "okay"; |
||||
dr_mode = "peripheral"; |
||||
maximum-speed = "high-speed"; |
||||
}; |
||||
|
||||
&usb1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&dwc3_1 { |
||||
status = "okay"; |
||||
dr_mode = "host"; |
||||
maximum-speed = "high-speed"; |
||||
}; |
||||
|
||||
&watchdog0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&xlnx_dp { |
||||
xlnx,max-pclock-frequency = <200000>; |
||||
}; |
||||
|
||||
&xlnx_dpdma { |
||||
xlnx,axi-clock-freq = <200000000>; |
||||
}; |
||||
@ -1,6 +1,7 @@ |
||||
ZYNQ BOARD |
||||
M: Michal Simek <monstr@monstr.eu> |
||||
S: Maintained |
||||
F: arch/arm/dts/zynq-* |
||||
F: board/xilinx/zynq/ |
||||
F: include/configs/zynq*.h |
||||
F: configs/zynq_*_defconfig |
||||
|
||||
@ -0,0 +1,18 @@ |
||||
# Copyright (c) 2018, Xilinx, Inc. |
||||
# |
||||
# SPDX-License-Identifier: GPL-2.0 |
||||
|
||||
if ARCH_ZYNQMP |
||||
|
||||
config CMD_ZYNQMP |
||||
bool "Enable ZynqMP specific commands" |
||||
default y |
||||
help |
||||
Enable ZynqMP specific commands like "zynqmp secure" |
||||
which is used for zynqmp secure image verification. |
||||
The secure image is a xilinx specific BOOT.BIN with |
||||
either authentication or encryption or both encryption |
||||
and authentication feature enabled while generating |
||||
BOOT.BIN using Xilinx bootgen tool. |
||||
|
||||
endif |
||||
@ -1,6 +1,7 @@ |
||||
XILINX_ZYNQMP BOARDS |
||||
M: Michal Simek <michal.simek@xilinx.com> |
||||
S: Maintained |
||||
F: arch/arm/dts/zynqmp-* |
||||
F: board/xilinx/zynqmp/ |
||||
F: include/configs/xilinx_zynqmp* |
||||
F: configs/xilinx_zynqmp* |
||||
|
||||
@ -0,0 +1,105 @@ |
||||
/*
|
||||
* (C) Copyright 2018 Xilinx, Inc. |
||||
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/io.h> |
||||
|
||||
static int zynqmp_verify_secure(u8 *key_ptr, u8 *src_ptr, u32 len) |
||||
{ |
||||
int ret; |
||||
u32 src_lo, src_hi; |
||||
u32 key_lo = 0; |
||||
u32 key_hi = 0; |
||||
u32 ret_payload[PAYLOAD_ARG_CNT]; |
||||
u64 addr; |
||||
|
||||
if ((ulong)src_ptr != ALIGN((ulong)src_ptr, |
||||
CONFIG_SYS_CACHELINE_SIZE)) { |
||||
printf("Failed: source address not aligned:%p\n", src_ptr); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
src_lo = lower_32_bits((ulong)src_ptr); |
||||
src_hi = upper_32_bits((ulong)src_ptr); |
||||
flush_dcache_range((ulong)src_ptr, (ulong)(src_ptr + len)); |
||||
|
||||
if (key_ptr) { |
||||
key_lo = lower_32_bits((ulong)key_ptr); |
||||
key_hi = upper_32_bits((ulong)key_ptr); |
||||
flush_dcache_range((ulong)key_ptr, |
||||
(ulong)(key_ptr + KEY_PTR_LEN)); |
||||
} |
||||
|
||||
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD, src_lo, src_hi, |
||||
key_lo, key_hi, ret_payload); |
||||
if (ret) { |
||||
printf("Failed: secure op status:0x%x\n", ret); |
||||
} else { |
||||
addr = (u64)ret_payload[1] << 32 | ret_payload[2]; |
||||
printf("Verified image at 0x%llx\n", addr); |
||||
env_set_hex("zynqmp_verified_img_addr", addr); |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
/**
|
||||
* do_zynqmp - Handle the "zynqmp" command-line command |
||||
* @cmdtp: Command data struct pointer |
||||
* @flag: Command flag |
||||
* @argc: Command-line argument count |
||||
* @argv: Array of command-line arguments |
||||
* |
||||
* Processes the zynqmp specific commands |
||||
* |
||||
* Return: return 0 on success and CMD_RET_USAGE incase of misuse and error |
||||
*/ |
||||
static int do_zynqmp(cmd_tbl_t *cmdtp, int flag, int argc, |
||||
char *const argv[]) |
||||
{ |
||||
u64 src_addr; |
||||
u32 len; |
||||
u8 *key_ptr = NULL; |
||||
u8 *src_ptr; |
||||
int ret; |
||||
|
||||
if (argc > 5 || argc < 4 || strncmp(argv[1], "secure", 6)) |
||||
return CMD_RET_USAGE; |
||||
|
||||
src_addr = simple_strtoull(argv[2], NULL, 16); |
||||
|
||||
len = simple_strtoul(argv[3], NULL, 16); |
||||
|
||||
if (argc > 4) |
||||
key_ptr = (uint8_t *)(uintptr_t)simple_strtoull(argv[4], |
||||
NULL, 16); |
||||
|
||||
src_ptr = (uint8_t *)(uintptr_t)src_addr; |
||||
|
||||
ret = zynqmp_verify_secure(key_ptr, src_ptr, len); |
||||
if (ret) |
||||
return CMD_RET_FAILURE; |
||||
|
||||
return CMD_RET_SUCCESS; |
||||
} |
||||
|
||||
/***************************************************/ |
||||
#ifdef CONFIG_SYS_LONGHELP |
||||
static char zynqmp_help_text[] = |
||||
"secure src len [key_addr] - verifies secure images of $len bytes\n" |
||||
" long at address $src. Optional key_addr\n" |
||||
" can be specified if user key needs to\n" |
||||
" be used for decryption\n"; |
||||
#endif |
||||
|
||||
U_BOOT_CMD( |
||||
zynqmp, 5, 1, do_zynqmp, |
||||
"Verify and load secure images", |
||||
zynqmp_help_text |
||||
) |
||||
@ -1,102 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep" |
||||
CONFIG_ARCH_ZYNQMP=y |
||||
CONFIG_SYS_TEXT_BASE=0x8000000 |
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000 |
||||
CONFIG_ZYNQ_SDHCI_MAX_FREQ=52000000 |
||||
CONFIG_ZYNQMP_USB=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_AHCI=y |
||||
CONFIG_DISTRO_DEFAULTS=y |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SPL_LOAD_FIT=y |
||||
# CONFIG_DISPLAY_CPUINFO is not set |
||||
# CONFIG_DISPLAY_BOARDINFO is not set |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_OS_BOOT=y |
||||
CONFIG_SYS_PROMPT="ZynqMP> " |
||||
CONFIG_FASTBOOT=y |
||||
CONFIG_FASTBOOT_FLASH=y |
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
||||
# CONFIG_CMD_CONSOLE is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
CONFIG_CMD_THOR_DOWNLOAD=y |
||||
# CONFIG_CMD_EDITENV is not set |
||||
# CONFIG_CMD_ENV_EXISTS is not set |
||||
CONFIG_CMD_CLK=y |
||||
CONFIG_CMD_DFU=y |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_GPT=y |
||||
CONFIG_CMD_I2C=y |
||||
# CONFIG_CMD_LOADB is not set |
||||
# CONFIG_CMD_LOADS is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_NAND_LOCK_UNLOCK=y |
||||
CONFIG_CMD_USB=y |
||||
# CONFIG_CMD_ITEST is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_CMD_TFTPPUT=y |
||||
# CONFIG_CMD_NFS is not set |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_TIMER=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
# CONFIG_SPL_ISO_PARTITION is not set |
||||
CONFIG_SPL_OF_CONTROL=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_ENV_IS_IN_FAT=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_SPL_DM=y |
||||
CONFIG_SPL_DM_SEQ_ALIAS=y |
||||
CONFIG_SCSI_AHCI=y |
||||
CONFIG_SATA_CEVA=y |
||||
CONFIG_DFU_RAM=y |
||||
CONFIG_FPGA_XILINX=y |
||||
CONFIG_FPGA_ZYNQMPPL=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_SYS_I2C_CADENCE=y |
||||
CONFIG_MISC=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_MMC_SDHCI=y |
||||
CONFIG_MMC_SDHCI_ZYNQ=y |
||||
CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 |
||||
CONFIG_NAND=y |
||||
CONFIG_NAND_ARASAN=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_BAR=y |
||||
CONFIG_SPI_FLASH_SPANSION=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_SPI_FLASH_WINBOND=y |
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
||||
CONFIG_PHY_MARVELL=y |
||||
CONFIG_PHY_NATSEMI=y |
||||
CONFIG_PHY_REALTEK=y |
||||
CONFIG_PHY_TI=y |
||||
CONFIG_PHY_VITESSE=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_PHY_GIGE=y |
||||
CONFIG_ZYNQ_GEM=y |
||||
CONFIG_SCSI=y |
||||
CONFIG_DM_SCSI=y |
||||
CONFIG_DEBUG_UART_ZYNQ=y |
||||
CONFIG_DEBUG_UART_BASE=0xff000000 |
||||
CONFIG_DEBUG_UART_CLOCK=25000000 |
||||
CONFIG_DEBUG_UART_ANNOUNCE=y |
||||
CONFIG_ZYNQ_SERIAL=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_XHCI_HCD=y |
||||
CONFIG_USB_XHCI_DWC3=y |
||||
CONFIG_USB_XHCI_ZYNQMP=y |
||||
CONFIG_USB_DWC3=y |
||||
CONFIG_USB_DWC3_GADGET=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx" |
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03fd |
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 |
||||
CONFIG_USB_FUNCTION_THOR=y |
||||
# CONFIG_REGEX is not set |
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y |
||||
@ -0,0 +1,276 @@ |
||||
/*
|
||||
* Cadence WDT driver - Used by Xilinx Zynq |
||||
* Reference: Linux kernel Cadence watchdog driver. |
||||
* |
||||
* Author(s): Shreenidhi Shedi <yesshedi@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <wdt.h> |
||||
#include <clk.h> |
||||
#include <linux/io.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
struct cdns_regs { |
||||
u32 zmr; /* WD Zero mode register, offset - 0x0 */ |
||||
u32 ccr; /* Counter Control Register offset - 0x4 */ |
||||
u32 restart; /* Restart key register, offset - 0x8 */ |
||||
u32 status; /* Status Register, offset - 0xC */ |
||||
}; |
||||
|
||||
struct cdns_wdt_priv { |
||||
bool rst; |
||||
u32 timeout; |
||||
void __iomem *reg; |
||||
struct cdns_regs *regs; |
||||
}; |
||||
|
||||
#define CDNS_WDT_DEFAULT_TIMEOUT 10 |
||||
|
||||
/* Supports 1 - 516 sec */ |
||||
#define CDNS_WDT_MIN_TIMEOUT 1 |
||||
#define CDNS_WDT_MAX_TIMEOUT 516 |
||||
|
||||
/* Restart key */ |
||||
#define CDNS_WDT_RESTART_KEY 0x00001999 |
||||
|
||||
/* Counter register access key */ |
||||
#define CDNS_WDT_REGISTER_ACCESS_KEY 0x00920000 |
||||
|
||||
/* Counter value divisor */ |
||||
#define CDNS_WDT_COUNTER_VALUE_DIVISOR 0x1000 |
||||
|
||||
/* Clock prescaler value and selection */ |
||||
#define CDNS_WDT_PRESCALE_64 64 |
||||
#define CDNS_WDT_PRESCALE_512 512 |
||||
#define CDNS_WDT_PRESCALE_4096 4096 |
||||
#define CDNS_WDT_PRESCALE_SELECT_64 1 |
||||
#define CDNS_WDT_PRESCALE_SELECT_512 2 |
||||
#define CDNS_WDT_PRESCALE_SELECT_4096 3 |
||||
|
||||
/* Input clock frequency */ |
||||
#define CDNS_WDT_CLK_75MHZ 75000000 |
||||
|
||||
/* Counter maximum value */ |
||||
#define CDNS_WDT_COUNTER_MAX 0xFFF |
||||
|
||||
/********************* Register Map **********************************/ |
||||
|
||||
/*
|
||||
* Zero Mode Register - This register controls how the time out is indicated |
||||
* and also contains the access code to allow writes to the register (0xABC). |
||||
*/ |
||||
#define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */ |
||||
#define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */ |
||||
#define CDNS_WDT_ZMR_IRQEN_MASK 0x00000004 /* Enable IRQ output */ |
||||
#define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */ |
||||
#define CDNS_WDT_ZMR_ZKEY_VAL 0x00ABC000 /* Access key, 0xABC << 12 */ |
||||
|
||||
/*
|
||||
* Counter Control register - This register controls how fast the timer runs |
||||
* and the reset value and also contains the access code to allow writes to |
||||
* the register. |
||||
*/ |
||||
#define CDNS_WDT_CCR_CRV_MASK 0x00003FFC /* Counter reset value */ |
||||
|
||||
/* Write access to Registers */ |
||||
static inline void cdns_wdt_writereg(u32 *addr, u32 val) |
||||
{ |
||||
writel(val, addr); |
||||
} |
||||
|
||||
/**
|
||||
* cdns_wdt_reset - Reload the watchdog timer (i.e. pat the watchdog). |
||||
* |
||||
* @dev: Watchdog device |
||||
* |
||||
* Write the restart key value (0x00001999) to the restart register. |
||||
* |
||||
* Return: Always 0 |
||||
*/ |
||||
static int cdns_wdt_reset(struct udevice *dev) |
||||
{ |
||||
struct cdns_wdt_priv *priv = dev_get_priv(dev); |
||||
|
||||
debug("%s\n", __func__); |
||||
|
||||
cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/**
|
||||
* cdns_wdt_start - Enable and start the watchdog. |
||||
* |
||||
* @dev: Watchdog device |
||||
* @timeout: Timeout value |
||||
* @flags: Driver flags |
||||
* |
||||
* The counter value is calculated according to the formula: |
||||
* count = (timeout * clock) / prescaler + 1. |
||||
* |
||||
* The calculated count is divided by 0x1000 to obtain the field value |
||||
* to write to counter control register. |
||||
* |
||||
* Clears the contents of prescaler and counter reset value. Sets the |
||||
* prescaler to 4096 and the calculated count and access key |
||||
* to write to CCR Register. |
||||
* |
||||
* Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit) |
||||
* or Interrupt signal(IRQEN) with a specified cycles and the access |
||||
* key to write to ZMR Register. |
||||
* |
||||
* Return: Upon success 0, failure -1. |
||||
*/ |
||||
static int cdns_wdt_start(struct udevice *dev, u64 timeout, ulong flags) |
||||
{ |
||||
ulong clk_f; |
||||
u32 count, prescaler, ctrl_clksel, data = 0; |
||||
struct clk clock; |
||||
struct cdns_wdt_priv *priv = dev_get_priv(dev); |
||||
|
||||
if (clk_get_by_index(dev, 0, &clock) < 0) { |
||||
dev_err(dev, "failed to get clock\n"); |
||||
return -1; |
||||
} |
||||
|
||||
clk_f = clk_get_rate(&clock); |
||||
if (IS_ERR_VALUE(clk_f)) { |
||||
dev_err(dev, "failed to get rate\n"); |
||||
return -1; |
||||
} |
||||
|
||||
debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f, timeout); |
||||
|
||||
if ((timeout < CDNS_WDT_MIN_TIMEOUT) || |
||||
(timeout > CDNS_WDT_MAX_TIMEOUT)) { |
||||
timeout = priv->timeout; |
||||
} |
||||
|
||||
if (clk_f <= CDNS_WDT_CLK_75MHZ) { |
||||
prescaler = CDNS_WDT_PRESCALE_512; |
||||
ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512; |
||||
} else { |
||||
prescaler = CDNS_WDT_PRESCALE_4096; |
||||
ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096; |
||||
} |
||||
|
||||
/*
|
||||
* Counter value divisor to obtain the value of |
||||
* counter reset to be written to control register. |
||||
*/ |
||||
count = (timeout * (clk_f / prescaler)) / |
||||
CDNS_WDT_COUNTER_VALUE_DIVISOR + 1; |
||||
|
||||
if (count > CDNS_WDT_COUNTER_MAX) |
||||
count = CDNS_WDT_COUNTER_MAX; |
||||
|
||||
cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL); |
||||
|
||||
count = (count << 2) & CDNS_WDT_CCR_CRV_MASK; |
||||
|
||||
/* Write counter access key first to be able write to register */ |
||||
data = count | CDNS_WDT_REGISTER_ACCESS_KEY | ctrl_clksel; |
||||
cdns_wdt_writereg(&priv->regs->ccr, data); |
||||
|
||||
data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 | |
||||
CDNS_WDT_ZMR_ZKEY_VAL; |
||||
|
||||
/* Reset on timeout if specified in device tree. */ |
||||
if (priv->rst) { |
||||
data |= CDNS_WDT_ZMR_RSTEN_MASK; |
||||
data &= ~CDNS_WDT_ZMR_IRQEN_MASK; |
||||
} else { |
||||
data &= ~CDNS_WDT_ZMR_RSTEN_MASK; |
||||
data |= CDNS_WDT_ZMR_IRQEN_MASK; |
||||
} |
||||
|
||||
cdns_wdt_writereg(&priv->regs->zmr, data); |
||||
cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/**
|
||||
* cdns_wdt_stop - Stop the watchdog. |
||||
* |
||||
* @dev: Watchdog device |
||||
* |
||||
* Read the contents of the ZMR register, clear the WDEN bit in the register |
||||
* and set the access key for successful write. |
||||
* |
||||
* Return: Always 0 |
||||
*/ |
||||
static int cdns_wdt_stop(struct udevice *dev) |
||||
{ |
||||
struct cdns_wdt_priv *priv = dev_get_priv(dev); |
||||
|
||||
cdns_wdt_writereg(&priv->regs->zmr, |
||||
CDNS_WDT_ZMR_ZKEY_VAL & (~CDNS_WDT_ZMR_WDEN_MASK)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/**
|
||||
* cdns_wdt_probe - Probe call for the device. |
||||
* |
||||
* @dev: Handle to the udevice structure. |
||||
* |
||||
* Return: Always 0. |
||||
*/ |
||||
static int cdns_wdt_probe(struct udevice *dev) |
||||
{ |
||||
struct cdns_wdt_priv *priv = dev_get_priv(dev); |
||||
|
||||
debug("%s: Probing wdt%u\n", __func__, dev->seq); |
||||
|
||||
priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs)); |
||||
|
||||
cdns_wdt_stop(dev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int cdns_wdt_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
int node = dev_of_offset(dev); |
||||
struct cdns_wdt_priv *priv = dev_get_priv(dev); |
||||
|
||||
priv->regs = devfdt_get_addr_ptr(dev); |
||||
if (IS_ERR(priv->regs)) |
||||
return PTR_ERR(priv->regs); |
||||
|
||||
priv->timeout = fdtdec_get_int(gd->fdt_blob, node, "timeout-sec", |
||||
CDNS_WDT_DEFAULT_TIMEOUT); |
||||
|
||||
priv->rst = fdtdec_get_bool(gd->fdt_blob, node, "reset-on-timeout"); |
||||
|
||||
debug("%s: timeout %d, reset %d\n", __func__, priv->timeout, priv->rst); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct wdt_ops cdns_wdt_ops = { |
||||
.start = cdns_wdt_start, |
||||
.reset = cdns_wdt_reset, |
||||
.stop = cdns_wdt_stop, |
||||
}; |
||||
|
||||
static const struct udevice_id cdns_wdt_ids[] = { |
||||
{ .compatible = "cdns,wdt-r1p2" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(cdns_wdt) = { |
||||
.name = "cdns_wdt", |
||||
.id = UCLASS_WDT, |
||||
.of_match = cdns_wdt_ids, |
||||
.probe = cdns_wdt_probe, |
||||
.priv_auto_alloc_size = sizeof(struct cdns_wdt_priv), |
||||
.ofdata_to_platdata = cdns_wdt_ofdata_to_platdata, |
||||
.ops = &cdns_wdt_ops, |
||||
}; |
||||
@ -1,24 +0,0 @@ |
||||
/*
|
||||
* Configuration for Xilinx ZynqMP emulation platforms |
||||
* |
||||
* (C) Copyright 2014 - 2015 Xilinx, Inc. |
||||
* Michal Simek <michal.simek@xilinx.com> |
||||
* Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
||||
* |
||||
* Based on Configuration for Versatile Express |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_ZYNQMP_EP_H |
||||
#define __CONFIG_ZYNQMP_EP_H |
||||
|
||||
#define CONFIG_ZYNQ_EEPROM |
||||
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ |
||||
ZYNQMP_USB1_XHCI_BASEADDR} |
||||
|
||||
#define COUNTER_FREQUENCY 4000000 |
||||
|
||||
#include <configs/xilinx_zynqmp.h> |
||||
|
||||
#endif /* __CONFIG_ZYNQMP_EP_H */ |
||||
Loading…
Reference in new issue