Board support for the Guntermann & Drunck PowerPC 440 ETX module. Based on the AMCC Yosemite board support by Stefan Roese. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>master
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#
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# (C) Copyright 2002-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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#
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# (C) Copyright 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# G&D 440EP/GR ETX-Module
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#
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#TEXT_BASE = 0x00001000
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ifeq ($(ramsym),1) |
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TEXT_BASE = 0xFBD00000
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else |
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TEXT_BASE = 0xFFF80000
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endif |
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif |
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/*
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* (C) Copyright 2008 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* Based on board/amcc/yosemite/yosemite.c |
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* (C) Copyright 2006-2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <ppc4xx.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* info for FLASH chips */ |
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; |
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int board_early_init_f(void) |
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{ |
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register uint reg; |
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/*
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* Setup the external bus controller/chip selects |
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*/ |
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mfebc(xbcfg, reg); |
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mtebc(xbcfg, reg | 0x04000000); /* Set ATC */ |
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/*
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* Setup the GPIO pins |
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*/ |
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/* setup Address lines for flash size 64Meg. */ |
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000); |
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000); |
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000); |
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/* setup emac */ |
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); |
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); |
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); |
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); |
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out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); |
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/* UART0 and UART1*/ |
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000); |
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out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000); |
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out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000); |
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out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000); |
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/* disable boot-eeprom WP */ |
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000); |
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000); |
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000); |
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000); |
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out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000); |
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/* external interrupts IRQ0...3 */ |
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out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); |
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out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); |
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out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); |
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/*
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* Setup the interrupt controller polarities, triggers, etc. |
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*/ |
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mtdcr(uic0sr, 0xffffffff); /* clear all */ |
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mtdcr(uic0er, 0x00000000); /* disable all */ |
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mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ |
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ |
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ |
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ |
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mtdcr(uic0sr, 0xffffffff); /* clear all */ |
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mtdcr(uic1sr, 0xffffffff); /* clear all */ |
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mtdcr(uic1er, 0x00000000); /* disable all */ |
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mtdcr(uic1cr, 0x00000000); /* all non-critical */ |
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ |
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ |
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ |
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mtdcr(uic1sr, 0xffffffff); /* clear all */ |
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/*
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* Setup other serial configuration |
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*/ |
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mfsdr(sdr_pci0, reg); |
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mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ |
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mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ |
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mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ |
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return 0; |
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} |
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int misc_init_r(void) |
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{ |
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uint pbcr; |
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int size_val; |
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uint sz; |
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/* Re-do sizing to get full correct info */ |
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mfebc(pb0cr, pbcr); |
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if (gd->bd->bi_flashsize > 0x08000000) |
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panic("Max. flash banksize is 128 MB!\n"); |
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for (sz = gd->bd->bi_flashsize, size_val = 7; |
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((sz & 0x08000000) == 0) && (size_val > 0); --size_val) |
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sz <<= 1; |
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
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mtebc(pb0cr, pbcr); |
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/* adjust flash start and offset */ |
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
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gd->bd->bi_flashoffset = 0; |
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/* Monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, |
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-CONFIG_SYS_MONITOR_LEN, |
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0xffffffff, |
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&flash_info[0]); |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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char *s = getenv("serial#"); |
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u8 rev; |
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u8 val; |
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printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module"); |
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if (s != NULL) { |
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puts(", serial# "); |
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puts(s); |
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} |
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putc('\n'); |
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return 0; |
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} |
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/*
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* pci_pre_init |
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* |
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* This routine is called just prior to registering the hose and gives |
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* the board the opportunity to check things. Returning a value of zero |
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* indicates that things are bad & PCI initialization should be aborted. |
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* |
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* Different boards may wish to customize the pci controller structure |
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* (add regions, override default access routines, etc) or perform |
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* certain pre-initialization actions. |
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* |
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*/ |
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#if defined(CONFIG_PCI) |
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int pci_pre_init(struct pci_controller *hose) |
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{ |
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unsigned long addr; |
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/*
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* Set priority for all PLB3 devices to 0. |
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* Set PLB3 arbiter to fair mode. |
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*/ |
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mfsdr(sdr_amp1, addr); |
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mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); |
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addr = mfdcr(plb3_acr); |
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mtdcr(plb3_acr, addr | 0x80000000); |
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/*
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* Set priority for all PLB4 devices to 0. |
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*/ |
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mfsdr(sdr_amp0, addr); |
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mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); |
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addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ |
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mtdcr(plb4_acr, addr); |
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/*
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* Set Nebula PLB4 arbiter to fair mode. |
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*/ |
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/* Segment0 */ |
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addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; |
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addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; |
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addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; |
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addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; |
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mtdcr(plb0_acr, addr); |
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/* Segment1 */ |
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addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; |
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addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; |
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addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; |
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addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; |
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mtdcr(plb1_acr, addr); |
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/* enable 66 MHz ext. Clock */ |
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); |
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out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000); |
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return 1; |
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} |
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#endif /* defined(CONFIG_PCI) */ |
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/*
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* pci_target_init |
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* |
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* The bootstrap configuration provides default settings for the pci |
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* inbound map (PIM). But the bootstrap config choices are limited and |
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* may not be sufficient for a given board. |
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* |
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*/ |
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) |
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void pci_target_init(struct pci_controller *hose) |
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{ |
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/*
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* Set up Direct MMIO registers |
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*/ |
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/*
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* PowerPC440 EP PCI Master configuration. |
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* Map one 1Gig range of PLB/processor addresses to PCI memory space. |
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* PLB address 0xA0000000-0xDFFFFFFF |
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* ==> PCI address 0xA0000000-0xDFFFFFFF |
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* Use byte reversed out routines to handle endianess. |
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* Make this region non-prefetchable. |
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*/ |
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out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */ |
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out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); |
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out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); |
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out32r(PCIX0_PMM0PCIHA, 0x00000000); |
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out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ |
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out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */ |
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out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); |
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out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); |
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out32r(PCIX0_PMM1PCIHA, 0x00000000); |
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out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ |
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out32r(PCIX0_PTM1MS, 0x00000001); |
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out32r(PCIX0_PTM1LA, 0); |
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out32r(PCIX0_PTM2MS, 0); |
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out32r(PCIX0_PTM2LA, 0); |
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/*
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* Set up Configuration registers |
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*/ |
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/* Program the board's subsystem id/vendor id */ |
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pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, |
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CONFIG_SYS_PCI_SUBSYS_VENDORID); |
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pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); |
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/* Configure command register as bus master */ |
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pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); |
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/* 240nS PCI clock */ |
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pci_write_config_word(0, PCI_LATENCY_TIMER, 1); |
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/* No error reporting */ |
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pci_write_config_word(0, PCI_ERREN, 0); |
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pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); |
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} |
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ |
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/*
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* pci_master_init |
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* |
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*/ |
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) |
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void pci_master_init(struct pci_controller *hose) |
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{ |
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unsigned short temp_short; |
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/*
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* Write the PowerPC440 EP PCI Configuration regs. |
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* Enable PowerPC440 EP to be a master on the PCI bus (PMM). |
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* Enable PowerPC440 EP to act as a PCI memory target (PTM). |
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*/ |
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pci_read_config_word(0, PCI_COMMAND, &temp_short); |
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pci_write_config_word(0, PCI_COMMAND, |
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temp_short | PCI_COMMAND_MASTER | |
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PCI_COMMAND_MEMORY); |
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} |
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ |
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|
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/*
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* is_pci_host |
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* |
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* This routine is called to determine if a pci scan should be |
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* performed. With various hardware environments (especially cPCI and |
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* PPMC) it's insufficient to depend on the state of the arbiter enable |
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* bit in the strap register, or generic host/adapter assumptions. |
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* |
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* Rather than hard-code a bad assumption in the general 440 code, the |
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* 440 pci code requires the board to decide at runtime. |
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* |
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* Return 0 for adapter mode, non-zero for host (monarch) mode. |
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* |
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* |
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*/ |
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#if defined(CONFIG_PCI) |
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int is_pci_host(struct pci_controller *hose) |
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{ |
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return 1; |
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} |
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#endif /* defined(CONFIG_PCI) */ |
@ -0,0 +1,75 @@ |
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/* |
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* (C) Copyright 2008 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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* |
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* based on board/amcc/yosemite/init.S |
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* original Copyright not specified there |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <ppc_asm.tmpl> |
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#include <config.h> |
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#include <asm/mmu.h> |
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/************************************************************************** |
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* TLB TABLE |
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* |
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* This table is used by the cpu boot code to setup the initial tlb |
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* entries. Rather than make broad assumptions in the cpu source tree, |
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* this table lets each board set things up however they like. |
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* |
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* Pointer to the table is returned in r1 |
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* |
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*************************************************************************/ |
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.section .bootpg,"ax" |
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.globl tlbtab
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tlbtab: |
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tlbtab_start |
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/* |
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use |
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* the speed up boot process. It is patched after relocation to enable SA_I |
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*/ |
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tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, |
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0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) |
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|
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, |
||||
0, AC_R|AC_W|AC_X|SA_G ) |
||||
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, |
||||
0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, |
||||
0, AC_R|AC_W|SA_G|SA_I ) |
||||
|
||||
/* PCI */ |
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, |
||||
0, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, |
||||
0, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, |
||||
0, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, |
||||
0, AC_R|AC_W|SA_G|SA_I ) |
||||
|
||||
tlbtab_end |
@ -0,0 +1,144 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/ppc4xx/start.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/gdsys/gdppc440etx/init.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,194 @@ |
||||
/*
|
||||
* (C) Copyright 2008 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* Based on include/configs/yosemite.h |
||||
* (C) Copyright 2005-2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_440GR 1 /* Specific PPC440GR support */ |
||||
#define CONFIG_HOSTNAME gdppc440etx |
||||
#define CONFIG_440 1 /* ... PPC440 family */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
||||
|
||||
/*
|
||||
* Include common defines/options for all AMCC eval boards |
||||
*/ |
||||
#include "amcc-common.h" |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ |
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ |
||||
#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ |
||||
#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 |
||||
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 |
||||
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 |
||||
|
||||
/*Don't change either of these*/ |
||||
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripheral*/ |
||||
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ |
||||
/*Don't change either of these*/ |
||||
|
||||
#define CONFIG_SYS_USB_DEVICE 0x50000000 |
||||
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 |
||||
|
||||
/*
|
||||
* Initial RAM & stack pointer (placed in SDRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ |
||||
#define CONFIG_SYS_INIT_RAM_END (4 << 10) |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes init data*/ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ |
||||
- CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
||||
#define CONFIG_UART1_CONSOLE |
||||
|
||||
/*
|
||||
* Environment |
||||
* Define here the location of the environment variables (FLASH or EEPROM). |
||||
* Note: DENX encourages to use redundant environment in FLASH. |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ |
||||
|
||||
/*
|
||||
* FLASH related |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ |
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */ |
||||
|
||||
/*
|
||||
* DDR SDRAM |
||||
*/ |
||||
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ |
||||
#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ |
||||
#define CONFIG_SYS_SDRAM_BANKS (2) |
||||
|
||||
#define CONFIG_SDRAM_BANK0 |
||||
#define CONFIG_SDRAM_BANK1 |
||||
|
||||
#define CONFIG_SYS_SDRAM0_TR0 0x410a4012 |
||||
#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 |
||||
#define CONFIG_SYS_SDRAM0_RTR 0x04080000 |
||||
#define CONFIG_SYS_SDRAM0_CFG0 0x80000000 |
||||
|
||||
#undef CONFIG_SDRAM_ECC |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/ |
||||
|
||||
/*
|
||||
* Default environment variables |
||||
*/ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
CONFIG_AMCC_DEF_ENV \
|
||||
CONFIG_AMCC_DEF_ENV_POWERPC \
|
||||
CONFIG_AMCC_DEF_ENV_NOR_UPD \
|
||||
"kernel_addr=fc000000\0" \
|
||||
"ramdisk_addr=fc180000\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
||||
#define CONFIG_PHY_ADDR 1 |
||||
#define CONFIG_PHY1_ADDR 3 |
||||
|
||||
#ifdef DEBUG |
||||
#define CONFIG_PANIC_HANG |
||||
#endif |
||||
|
||||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h |
||||
*/ |
||||
#define CONFIG_CMD_PCI |
||||
#undef CONFIG_CMD_EEPROM |
||||
|
||||
/*
|
||||
* PCI stuff |
||||
*/ |
||||
|
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ |
||||
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ |
||||
CONFIG_SYS_PCI_MEMBASE*/ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CONFIG_SYS_PCI_TARGET_INIT |
||||
#define CONFIG_SYS_PCI_MASTER_INIT |
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ |
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE |
||||
|
||||
/* Memory Bank 0 (NOR-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB0AP 0x03017200 |
||||
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue