Wolfgang Denk
18 years ago
commit
8a92b7c60b
@ -0,0 +1,52 @@ |
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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SOBJS := init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(OBJS) $(SOBJS)
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.PHONY: distclean |
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude ($obj).depend |
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#########################################################################
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@ -0,0 +1,30 @@ |
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# Copyright 2004 Freescale Semiconductor.
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# Modified by Jeff Brown
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# sbc8641 board
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# default CCSRBAR is at 0xff700000
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#
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TEXT_BASE = 0xfff00000
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PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
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@ -0,0 +1,192 @@ |
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/* |
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* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> |
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* Copyright 2007 Embedded Specialties, Inc. |
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* Joe Hamman joe.hamman@embeddedspecialties.com
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* |
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* Copyright 2004 Freescale Semiconductor. |
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* Jeff Brown |
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <ppc_asm.tmpl> |
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#include <ppc_defs.h> |
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#include <asm/cache.h> |
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#include <asm/mmu.h> |
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#include <config.h> |
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#include <mpc86xx.h> |
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/* |
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* LAW(Local Access Window) configuration: |
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* |
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* 0x0000_0000 0x0fff_ffff DDR1 256M |
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* 0x1000_0000 0x1fff_ffff DDR2 256M |
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* 0xe000_0000 0xffff_ffff LBC 512M |
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* |
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* Notes: |
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* CCSRBAR doesn't need a configured Local Access Window. |
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* If flash is 8M at default position (last 8M), no LAW needed. |
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*/ |
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# DDR Bank 1 |
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# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) |
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# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
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# DDR Bank 2 |
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# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff) |
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# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
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# LBC |
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# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff) |
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# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))) |
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/* |
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* LAW (Local Access Window) configuration: |
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* |
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* 0x0000_0000 DDR 256M |
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* 0x1000_0000 DDR2 256M |
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* 0x8000_0000 PCI1 MEM 512M |
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* 0xa000_0000 PCI2 MEM 512M |
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* 0xc000_0000 RapidIO 512M |
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* 0xe200_0000 PCI1 IO 16M |
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* 0xe300_0000 PCI2 IO 16M |
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* 0xf800_0000 CCSRBAR 2M |
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* 0xfe00_0000 FLASH (boot bank) 32M |
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* |
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*/ |
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#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) |
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
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#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) |
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
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#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) |
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#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) |
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#define LAWBAR4 ((0xf8000000>>12) & 0xffffff) |
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) |
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#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff) |
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
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#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) |
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#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) |
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#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) |
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#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) |
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#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff) |
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#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
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#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) |
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#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
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.section .bootpg, "ax" |
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.globl law_entry
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law_entry: |
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lis r7,CFG_CCSRBAR@h
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ori r7,r7,CFG_CCSRBAR@l
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addi r4,r7,0 |
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addi r5,r7,0 |
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/* Skip LAWAR0, start at LAWAR1 */ |
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lis r6,LAWBAR1@h
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ori r6,r6,LAWBAR1@l
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stwu r6, 0xc28(r4) |
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lis r6,LAWAR1@h
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ori r6,r6,LAWAR1@l
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stwu r6, 0xc30(r5) |
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/* LAWBAR2, LAWAR2 */ |
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lis r6,LAWBAR2@h
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ori r6,r6,LAWBAR2@l
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stwu r6, 0x20(r4) |
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lis r6,LAWAR2@h
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ori r6,r6,LAWAR2@l
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stwu r6, 0x20(r5) |
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/* LAWBAR3, LAWAR3 */ |
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lis r6,LAWBAR3@h
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ori r6,r6,LAWBAR3@l
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stwu r6, 0x20(r4) |
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lis r6,LAWAR3@h
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ori r6,r6,LAWAR3@l
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stwu r6, 0x20(r5) |
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/* LAWBAR4, LAWAR4 */ |
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lis r6,LAWBAR4@h
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ori r6,r6,LAWBAR4@l
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stwu r6, 0x20(r4) |
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lis r6,LAWAR4@h
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ori r6,r6,LAWAR4@l
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stwu r6, 0x20(r5) |
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/* LAWBAR5, LAWAR5 */ |
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lis r6,LAWBAR5@h
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ori r6,r6,LAWBAR5@l
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stwu r6, 0x20(r4) |
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lis r6,LAWAR5@h
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ori r6,r6,LAWAR5@l
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stwu r6, 0x20(r5) |
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/* LAWBAR6, LAWAR6 */ |
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lis r6,LAWBAR6@h
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ori r6,r6,LAWBAR6@l
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stwu r6, 0x20(r4) |
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lis r6,LAWAR6@h
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ori r6,r6,LAWAR6@l
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stwu r6, 0x20(r5) |
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/* LAWBAR7, LAWAR7 */ |
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lis r6,LAWBAR7@h
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ori r6,r6,LAWBAR7@l
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stwu r6, 0x20(r4) |
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lis r6,LAWAR7@h
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ori r6,r6,LAWAR7@l
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stwu r6, 0x20(r5) |
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/* LAWBAR8, LAWAR8 */ |
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lis r6,LAWBAR8@h
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ori r6,r6,LAWBAR8@l
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stwu r6, 0x20(r4) |
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lis r6,LAWAR8@h
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ori r6,r6,LAWAR8@l
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stwu r6, 0x20(r5) |
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/* LAWBAR9, LAWAR9 */ |
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lis r6,LAWBAR9@h
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ori r6,r6,LAWBAR9@l
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stwu r6, 0x20(r4) |
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lis r6,LAWAR9@h
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ori r6,r6,LAWAR9@l
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stwu r6, 0x20(r5) |
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blr |
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@ -0,0 +1,406 @@ |
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/*
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* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> |
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* Copyright 2007 Embedded Specialties, Inc. |
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* Joe Hamman joe.hamman@embeddedspecialties.com |
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* |
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* Copyright 2004 Freescale Semiconductor. |
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* Jeff Brown |
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
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* |
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <pci.h> |
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#include <asm/processor.h> |
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#include <asm/immap_86xx.h> |
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#include <asm/immap_fsl_pci.h> |
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#include <spd.h> |
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#if defined(CONFIG_OF_FLAT_TREE) |
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#include <ft_build.h> |
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extern void ft_cpu_setup (void *blob, bd_t * bd); |
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#endif |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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extern void ddr_enable_ecc (unsigned int dram_size); |
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#endif |
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#if defined(CONFIG_SPD_EEPROM) |
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#include "spd_sdram.h" |
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#endif |
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void sdram_init (void); |
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long int fixed_sdram (void); |
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int board_early_init_f (void) |
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{ |
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return 0; |
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} |
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int checkboard (void) |
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{ |
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puts ("Board: Wind River SBC8641D\n"); |
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return 0; |
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} |
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long int initdram (int board_type) |
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{ |
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long dram_size = 0; |
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#if defined(CONFIG_SPD_EEPROM) |
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dram_size = spd_sdram (); |
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#else |
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dram_size = fixed_sdram (); |
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#endif |
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#if defined(CFG_RAMBOOT) |
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puts (" DDR: "); |
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return dram_size; |
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#endif |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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/*
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* Initialize and enable DDR ECC. |
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*/ |
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ddr_enable_ecc (dram_size); |
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#endif |
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puts (" DDR: "); |
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return dram_size; |
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} |
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#if defined(CFG_DRAM_TEST) |
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int testdram (void) |
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{ |
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uint *pstart = (uint *) CFG_MEMTEST_START; |
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uint *pend = (uint *) CFG_MEMTEST_END; |
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uint *p; |
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puts ("SDRAM test phase 1:\n"); |
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for (p = pstart; p < pend; p++) |
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*p = 0xaaaaaaaa; |
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for (p = pstart; p < pend; p++) { |
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if (*p != 0xaaaaaaaa) { |
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printf ("SDRAM test fails at: %08x\n", (uint) p); |
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return 1; |
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} |
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} |
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puts ("SDRAM test phase 2:\n"); |
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for (p = pstart; p < pend; p++) |
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*p = 0x55555555; |
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for (p = pstart; p < pend; p++) { |
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if (*p != 0x55555555) { |
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printf ("SDRAM test fails at: %08x\n", (uint) p); |
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return 1; |
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} |
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} |
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puts ("SDRAM test passed.\n"); |
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return 0; |
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} |
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#endif |
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#if !defined(CONFIG_SPD_EEPROM) |
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/*
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* Fixed sdram init -- doesn't use serial presence detect. |
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*/ |
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long int fixed_sdram (void) |
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{ |
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#if !defined(CFG_RAMBOOT) |
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volatile immap_t *immap = (immap_t *) CFG_IMMR; |
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volatile ccsr_ddr_t *ddr = &immap->im_ddr1; |
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ddr->cs0_bnds = CFG_DDR_CS0_BNDS; |
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ddr->cs1_bnds = CFG_DDR_CS1_BNDS; |
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ddr->cs2_bnds = CFG_DDR_CS2_BNDS; |
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ddr->cs3_bnds = CFG_DDR_CS3_BNDS; |
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ddr->cs0_config = CFG_DDR_CS0_CONFIG; |
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ddr->cs1_config = CFG_DDR_CS1_CONFIG; |
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ddr->cs2_config = CFG_DDR_CS2_CONFIG; |
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ddr->cs3_config = CFG_DDR_CS3_CONFIG; |
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ddr->ext_refrec = CFG_DDR_EXT_REFRESH; |
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ddr->timing_cfg_0 = CFG_DDR_TIMING_0; |
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ddr->timing_cfg_1 = CFG_DDR_TIMING_1; |
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ddr->timing_cfg_2 = CFG_DDR_TIMING_2; |
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ddr->sdram_cfg_1 = CFG_DDR_CFG_1A; |
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ddr->sdram_cfg_2 = CFG_DDR_CFG_2; |
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ddr->sdram_mode_1 = CFG_DDR_MODE_1; |
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ddr->sdram_mode_2 = CFG_DDR_MODE_2; |
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ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL; |
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ddr->sdram_interval = CFG_DDR_INTERVAL; |
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ddr->sdram_data_init = CFG_DDR_DATA_INIT; |
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ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; |
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|
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asm ("sync;isync"); |
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udelay (500); |
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|
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ddr->sdram_cfg_1 = CFG_DDR_CFG_1B; |
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asm ("sync; isync"); |
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|
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udelay (500); |
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ddr = &immap->im_ddr2; |
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|
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ddr->cs0_bnds = CFG_DDR2_CS0_BNDS; |
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ddr->cs1_bnds = CFG_DDR2_CS1_BNDS; |
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ddr->cs2_bnds = CFG_DDR2_CS2_BNDS; |
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ddr->cs3_bnds = CFG_DDR2_CS3_BNDS; |
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ddr->cs0_config = CFG_DDR2_CS0_CONFIG; |
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ddr->cs1_config = CFG_DDR2_CS1_CONFIG; |
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ddr->cs2_config = CFG_DDR2_CS2_CONFIG; |
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ddr->cs3_config = CFG_DDR2_CS3_CONFIG; |
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ddr->ext_refrec = CFG_DDR2_EXT_REFRESH; |
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ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; |
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ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; |
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ddr->timing_cfg_2 = CFG_DDR2_TIMING_2; |
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ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A; |
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ddr->sdram_cfg_2 = CFG_DDR2_CFG_2; |
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ddr->sdram_mode_1 = CFG_DDR2_MODE_1; |
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ddr->sdram_mode_2 = CFG_DDR2_MODE_2; |
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ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL; |
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ddr->sdram_interval = CFG_DDR2_INTERVAL; |
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ddr->sdram_data_init = CFG_DDR2_DATA_INIT; |
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ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL; |
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|
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asm ("sync;isync"); |
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|
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udelay (500); |
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|
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ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B; |
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asm ("sync; isync"); |
||||
|
||||
udelay (500); |
||||
#endif |
||||
return CFG_SDRAM_SIZE * 1024 * 1024; |
||||
} |
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
/*
|
||||
* Initialize PCI Devices, report devices found. |
||||
*/ |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_fsl86xxads_config_table[] = { |
||||
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, |
||||
{} |
||||
}; |
||||
#endif |
||||
|
||||
static struct pci_controller pci1_hose = { |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc86xxcts_config_table |
||||
#endif |
||||
}; |
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
#ifdef CONFIG_PCI2 |
||||
static struct pci_controller pci2_hose; |
||||
#endif /* CONFIG_PCI2 */ |
||||
|
||||
int first_free_busno = 0; |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; |
||||
volatile ccsr_gur_t *gur = &immap->im_gur; |
||||
uint devdisr = gur->devdisr; |
||||
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; |
||||
|
||||
#ifdef CONFIG_PCI1 |
||||
{ |
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; |
||||
extern void fsl_pci_init(struct pci_controller *hose); |
||||
struct pci_controller *hose = &pci1_hose; |
||||
#ifdef DEBUG |
||||
uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; |
||||
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); |
||||
#endif |
||||
if ((io_sel == 2 || io_sel == 3 || io_sel == 5 |
||||
|| io_sel == 6 || io_sel == 7 || io_sel == 0xF) |
||||
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { |
||||
debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); |
||||
debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); |
||||
if (pci->pme_msg_det) { |
||||
pci->pme_msg_det = 0xffffffff; |
||||
debug(" with errors. Clearing. Now 0x%08x", |
||||
pci->pme_msg_det); |
||||
} |
||||
debug("\n"); |
||||
|
||||
/* inbound */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI_MEMORY_BUS, |
||||
CFG_PCI_MEMORY_PHYS, |
||||
CFG_PCI_MEMORY_SIZE, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
/* outbound memory */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI1_MEM_BASE, |
||||
CFG_PCI1_MEM_PHYS, |
||||
CFG_PCI1_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* outbound io */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCI1_IO_BASE, |
||||
CFG_PCI1_IO_PHYS, |
||||
CFG_PCI1_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = 3; |
||||
|
||||
hose->first_busno=first_free_busno; |
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
||||
|
||||
fsl_pci_init(hose); |
||||
|
||||
first_free_busno=hose->last_busno+1; |
||||
printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", |
||||
hose->first_busno,hose->last_busno); |
||||
|
||||
} else { |
||||
puts("PCI-EXPRESS 1: Disabled\n"); |
||||
} |
||||
} |
||||
#else |
||||
puts("PCI-EXPRESS1: Disabled\n"); |
||||
#endif /* CONFIG_PCI1 */ |
||||
|
||||
#ifdef CONFIG_PCI2 |
||||
{ |
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; |
||||
extern void fsl_pci_init(struct pci_controller *hose); |
||||
struct pci_controller *hose = &pci2_hose; |
||||
|
||||
|
||||
/* inbound */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI_MEMORY_BUS, |
||||
CFG_PCI_MEMORY_PHYS, |
||||
CFG_PCI_MEMORY_SIZE, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
/* outbound memory */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI2_MEM_BASE, |
||||
CFG_PCI2_MEM_PHYS, |
||||
CFG_PCI2_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* outbound io */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCI2_IO_BASE, |
||||
CFG_PCI2_IO_PHYS, |
||||
CFG_PCI2_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = 3; |
||||
|
||||
hose->first_busno=first_free_busno; |
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
||||
|
||||
fsl_pci_init(hose); |
||||
|
||||
first_free_busno=hose->last_busno+1; |
||||
printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", |
||||
hose->first_busno,hose->last_busno); |
||||
} |
||||
#else |
||||
puts("PCI-EXPRESS 2: Disabled\n"); |
||||
#endif /* CONFIG_PCI2 */ |
||||
|
||||
} |
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) |
||||
void ft_board_setup (void *blob, bd_t * bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
ft_cpu_setup (blob, bd); |
||||
|
||||
p = ft_get_prop (blob, "/memory/reg", &len); |
||||
if (p != NULL) { |
||||
*p++ = cpu_to_be32 (bd->bi_memstart); |
||||
*p = cpu_to_be32 (bd->bi_memsize); |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
void sbc8641d_reset_board (void) |
||||
{ |
||||
puts ("Resetting board....\n"); |
||||
} |
||||
|
||||
/*
|
||||
* get_board_sys_clk |
||||
* Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ |
||||
*/ |
||||
|
||||
unsigned long get_board_sys_clk (ulong dummy) |
||||
{ |
||||
int i; |
||||
ulong val = 0; |
||||
|
||||
i = 5; |
||||
i &= 0x07; |
||||
|
||||
switch (i) { |
||||
case 0: |
||||
val = 33000000; |
||||
break; |
||||
case 1: |
||||
val = 40000000; |
||||
break; |
||||
case 2: |
||||
val = 50000000; |
||||
break; |
||||
case 3: |
||||
val = 66000000; |
||||
break; |
||||
case 4: |
||||
val = 83000000; |
||||
break; |
||||
case 5: |
||||
val = 100000000; |
||||
break; |
||||
case 6: |
||||
val = 134000000; |
||||
break; |
||||
case 7: |
||||
val = 166000000; |
||||
break; |
||||
} |
||||
|
||||
return val; |
||||
} |
||||
@ -0,0 +1,135 @@ |
||||
/* |
||||
* Copyright 2006, 2007 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
|
||||
SECTIONS |
||||
{ |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc86xx/start.o (.text) |
||||
board/sbc8641d/init.o (.bootpg) |
||||
cpu/mpc86xx/traps.o (.text) |
||||
cpu/mpc86xx/interrupts.o (.text) |
||||
cpu/mpc86xx/cpu_init.o (.text) |
||||
cpu/mpc86xx/cpu.o (.text) |
||||
cpu/mpc86xx/speed.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,28 @@ |
||||
Wind River SBC8641D reference board |
||||
=========================== |
||||
|
||||
Created 06/14/2007 Joe Hamman |
||||
Copyright 2007, Embedded Specialties, Inc. |
||||
Copyright 2007 Wind River Systemes, Inc. |
||||
----------------------------- |
||||
|
||||
1. Building U-Boot |
||||
------------------ |
||||
The SBC8641D code is known to build using ELDK 4.1. |
||||
|
||||
$ make sbc8641d_config |
||||
Configuring for sbc8641d board... |
||||
|
||||
$ make |
||||
|
||||
|
||||
2. Switch and Jumper Settings |
||||
----------------------------- |
||||
All Jumpers & Switches are in their default positions. Please refer to |
||||
the board documentation for details. Some settings control CPU voltages |
||||
and settings may change with board revisions. |
||||
|
||||
3. Known limitations |
||||
-------------------- |
||||
PCI: |
||||
The PCI command may hang if no boards are present in either slot. |
||||
@ -0,0 +1,604 @@ |
||||
/*
|
||||
* Copyright 2007 Wind River Systems <www.windriver.com> |
||||
* Copyright 2007 Embedded Specialties, Inc. |
||||
* Joe Hamman <joe.hamman@embeddedspecialties.com> |
||||
* |
||||
* Copyright 2006 Freescale Semiconductor. |
||||
* |
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* SBC8641D board configuration file |
||||
* |
||||
* Make sure you change the MAC address and other network params first, |
||||
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_MPC86xx 1 /* MPC86xx */ |
||||
#define CONFIG_MPC8641 1 /* MPC8641 specific */ |
||||
#define CONFIG_SBC8641D 1 /* SBC8641D board specific */ |
||||
#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ |
||||
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
||||
|
||||
#ifdef RUN_DIAG |
||||
#define CFG_DIAG_ADDR 0xff800000 |
||||
#endif |
||||
|
||||
#define CFG_RESET_ADDRESS 0xfff00100 |
||||
|
||||
#define CONFIG_PCI 1 /* Enable PCIE */ |
||||
#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ |
||||
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ |
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ |
||||
#undef CONFIG_DDR_DLL /* possible DLL fix needed */ |
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
||||
#define CONFIG_NUM_DDR_CONTROLLERS 2 |
||||
#define CACHE_LINE_INTERLEAVING 0x20000000 |
||||
#define PAGE_INTERLEAVING 0x21000000 |
||||
#define BANK_INTERLEAVING 0x22000000 |
||||
#define SUPER_BANK_INTERLEAVING 0x23000000 |
||||
|
||||
|
||||
#define CONFIG_ALTIVEC 1 |
||||
|
||||
/*
|
||||
* L2CR setup -- make sure this is right for your board! |
||||
*/ |
||||
#define CFG_L2 |
||||
#define L2_INIT 0 |
||||
#define L2_ENABLE (L2CR_L2E) |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
||||
#endif |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00400000 |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||
#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ |
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
||||
|
||||
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) |
||||
#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CFG_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ |
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
||||
#define CFG_SDRAM_BASE2 CFG_DDR_SDRAM_BASE2 |
||||
#define CONFIG_VERY_BIG_RAM |
||||
|
||||
#define MPC86xx_DDR_SDRAM_CLK_CNTL |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* Determine DDR configuration from I2C interface. |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ |
||||
#define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ |
||||
#define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ |
||||
#define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ |
||||
|
||||
#else |
||||
/*
|
||||
* Manually set up DDR1 & DDR2 parameters |
||||
*/ |
||||
|
||||
#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ |
||||
|
||||
#define CFG_DDR_CS0_BNDS 0x0000000F |
||||
#define CFG_DDR_CS1_BNDS 0x00000000 |
||||
#define CFG_DDR_CS2_BNDS 0x00000000 |
||||
#define CFG_DDR_CS3_BNDS 0x00000000 |
||||
#define CFG_DDR_CS0_CONFIG 0x80010102 |
||||
#define CFG_DDR_CS1_CONFIG 0x00000000 |
||||
#define CFG_DDR_CS2_CONFIG 0x00000000 |
||||
#define CFG_DDR_CS3_CONFIG 0x00000000 |
||||
#define CFG_DDR_EXT_REFRESH 0x00000000 |
||||
#define CFG_DDR_TIMING_0 0x00220802 |
||||
#define CFG_DDR_TIMING_1 0x38377322 |
||||
#define CFG_DDR_TIMING_2 0x002040c7 |
||||
#define CFG_DDR_CFG_1A 0x43008008 |
||||
#define CFG_DDR_CFG_2 0x24401000 |
||||
#define CFG_DDR_MODE_1 0x23c00542 |
||||
#define CFG_DDR_MODE_2 0x00000000 |
||||
#define CFG_DDR_MODE_CTL 0x00000000 |
||||
#define CFG_DDR_INTERVAL 0x05080100 |
||||
#define CFG_DDR_DATA_INIT 0x00000000 |
||||
#define CFG_DDR_CLK_CTRL 0x03800000 |
||||
#define CFG_DDR_CFG_1B 0xC3008008 |
||||
|
||||
#define CFG_DDR2_CS0_BNDS 0x0010001F |
||||
#define CFG_DDR2_CS1_BNDS 0x00000000 |
||||
#define CFG_DDR2_CS2_BNDS 0x00000000 |
||||
#define CFG_DDR2_CS3_BNDS 0x00000000 |
||||
#define CFG_DDR2_CS0_CONFIG 0x80010102 |
||||
#define CFG_DDR2_CS1_CONFIG 0x00000000 |
||||
#define CFG_DDR2_CS2_CONFIG 0x00000000 |
||||
#define CFG_DDR2_CS3_CONFIG 0x00000000 |
||||
#define CFG_DDR2_EXT_REFRESH 0x00000000 |
||||
#define CFG_DDR2_TIMING_0 0x00220802 |
||||
#define CFG_DDR2_TIMING_1 0x38377322 |
||||
#define CFG_DDR2_TIMING_2 0x002040c7 |
||||
#define CFG_DDR2_CFG_1A 0x43008008 |
||||
#define CFG_DDR2_CFG_2 0x24401000 |
||||
#define CFG_DDR2_MODE_1 0x23c00542 |
||||
#define CFG_DDR2_MODE_2 0x00000000 |
||||
#define CFG_DDR2_MODE_CTL 0x00000000 |
||||
#define CFG_DDR2_INTERVAL 0x05080100 |
||||
#define CFG_DDR2_DATA_INIT 0x00000000 |
||||
#define CFG_DDR2_CLK_CTRL 0x03800000 |
||||
#define CFG_DDR2_CFG_1B 0xC3008008 |
||||
|
||||
|
||||
#endif |
||||
|
||||
/* #define CFG_ID_EEPROM 1
|
||||
#define ID_EEPROM_ADDR 0x57 */ |
||||
|
||||
/*
|
||||
* The SBC8641D contains 16MB flash space at ff000000. |
||||
*/ |
||||
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
||||
|
||||
/* Flash */ |
||||
#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ |
||||
#define CFG_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ |
||||
|
||||
/* 64KB EEPROM */ |
||||
#define CFG_BR1_PRELIM 0xf0000801 /* port size 16bit */ |
||||
#define CFG_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ |
||||
|
||||
/* EPLD - User switches, board id, LEDs */ |
||||
#define CFG_BR2_PRELIM 0xf1000801 /* port size 16bit */ |
||||
#define CFG_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ |
||||
|
||||
/* Local bus SDRAM 128MB */ |
||||
#define CFG_BR3_PRELIM 0xe0001861 /* port size ?bit */ |
||||
#define CFG_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ |
||||
#define CFG_BR4_PRELIM 0xe4001861 /* port size ?bit */ |
||||
#define CFG_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ |
||||
|
||||
/* Disk on Chip (DOC) 128MB */ |
||||
#define CFG_BR5_PRELIM 0xe8001001 /* port size ?bit */ |
||||
#define CFG_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ |
||||
|
||||
/* LCD */ |
||||
#define CFG_BR6_PRELIM 0xf4000801 /* port size ?bit */ |
||||
#define CFG_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ |
||||
|
||||
/* Control logic & misc peripherals */ |
||||
#define CFG_BR7_PRELIM 0xf2000801 /* port size ?bit */ |
||||
#define CFG_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 131 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_WRITE_SWAPPED_DATA |
||||
#define CFG_FLASH_EMPTY_INFO |
||||
#define CFG_FLASH_PROTECTION |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#ifndef CFG_INIT_RAM_LOCK |
||||
#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ |
||||
#else |
||||
#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
||||
#endif |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/*
|
||||
* Pass open firmware flat tree to kernel |
||||
*/ |
||||
#define CONFIG_OF_FLAT_TREE 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
/* maximum size of the flat tree (8K) */ |
||||
#define OF_FLAT_TREE_MAX_SIZE 8192 |
||||
|
||||
#define OF_CPU "PowerPC,8641@0" |
||||
#define OF_SOC "soc@f8000000" |
||||
#define OF_TBCLK (bd->bi_busfreq / 4) |
||||
#define OF_STDOUT_PATH "/soc@f8000000/serial@4500" |
||||
|
||||
#define CFG_64BIT_VSPRINTF 1 |
||||
#define CFG_64BIT_STRTOUL 1 |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||
#define CFG_I2C_OFFSET 0x3100 |
||||
|
||||
/*
|
||||
* RapidIO MMU |
||||
*/ |
||||
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ |
||||
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE |
||||
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI1_IO_BASE 0xe2000000 |
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE |
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ |
||||
|
||||
/* PCI view of System Memory */ |
||||
#define CFG_PCI_MEMORY_BUS 0x00000000 |
||||
#define CFG_PCI_MEMORY_PHYS 0x00000000 |
||||
#define CFG_PCI_MEMORY_SIZE 0x80000000 |
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000 |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI2_IO_BASE 0xe3000000 |
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE |
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
|
||||
#undef CFG_SCSI_SCAN_BUS_REVERSE |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
|
||||
#if !defined(CONFIG_PCI_PNP) |
||||
#define PCI_ENET0_IOADDR 0xe0000000 |
||||
#define PCI_ENET0_MEMADDR 0xe0000000 |
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
||||
#endif |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
|
||||
#define CONFIG_DOS_PARTITION |
||||
#undef CONFIG_SCSI_AHCI |
||||
|
||||
#ifdef CONFIG_SCSI_AHCI |
||||
#define CONFIG_SATA_ULI5288 |
||||
#define CFG_SCSI_MAX_SCSI_ID 4 |
||||
#define CFG_SCSI_MAX_LUN 1 |
||||
#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) |
||||
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE |
||||
#endif |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
/* #define CONFIG_MII 1 */ /* MII PHY management */ |
||||
|
||||
#define CONFIG_TSEC1 1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC1" |
||||
#define CONFIG_TSEC2 1 |
||||
#define CONFIG_TSEC2_NAME "eTSEC2" |
||||
#define CONFIG_TSEC3 1 |
||||
#define CONFIG_TSEC3_NAME "eTSEC3" |
||||
#define CONFIG_TSEC4 1 |
||||
#define CONFIG_TSEC4_NAME "eTSEC4" |
||||
|
||||
#define TSEC1_PHY_ADDR 0x1F |
||||
#define TSEC2_PHY_ADDR 0x00 |
||||
#define TSEC3_PHY_ADDR 0x01 |
||||
#define TSEC4_PHY_ADDR 0x02 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define TSEC3_PHYIDX 0 |
||||
#define TSEC4_PHYIDX 0 |
||||
|
||||
#define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ |
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1" |
||||
|
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
/*
|
||||
* BAT0 2G Cacheable, non-guarded |
||||
* 0x0000_0000 2G DDR |
||||
*/ |
||||
#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) |
||||
#define CFG_IBAT0U CFG_DBAT0U |
||||
|
||||
/*
|
||||
* BAT1 1G Cache-inhibited, guarded |
||||
* 0x8000_0000 512M PCI-Express 1 Memory |
||||
* 0xa000_0000 512M PCI-Express 2 Memory |
||||
* Changed it for operating from 0xd0000000 |
||||
*/ |
||||
#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ |
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT1U CFG_DBAT1U |
||||
|
||||
/*
|
||||
* BAT2 512M Cache-inhibited, guarded |
||||
* 0xc000_0000 512M RapidIO Memory |
||||
*/ |
||||
#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ |
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT2U CFG_DBAT2U |
||||
|
||||
/*
|
||||
* BAT3 4M Cache-inhibited, guarded |
||||
* 0xf800_0000 4M CCSR |
||||
*/ |
||||
#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ |
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT3U CFG_DBAT3U |
||||
|
||||
/*
|
||||
* BAT4 32M Cache-inhibited, guarded |
||||
* 0xe200_0000 16M PCI-Express 1 I/O |
||||
* 0xe300_0000 16M PCI-Express 2 I/0 |
||||
* Note that this is at 0xe0000000 |
||||
*/ |
||||
#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ |
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT4U CFG_DBAT4U |
||||
|
||||
/*
|
||||
* BAT5 128K Cacheable, non-guarded |
||||
* 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) |
||||
*/ |
||||
#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
||||
#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT5L CFG_DBAT5L |
||||
#define CFG_IBAT5U CFG_DBAT5U |
||||
|
||||
/*
|
||||
* BAT6 32M Cache-inhibited, guarded |
||||
* 0xfe00_0000 32M FLASH |
||||
*/ |
||||
#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ |
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT6U CFG_DBAT6U |
||||
|
||||
#define CFG_DBAT7L 0x00000000 |
||||
#define CFG_DBAT7U 0x00000000 |
||||
#define CFG_IBAT7L 0x00000000 |
||||
#define CFG_IBAT7U 0x00000000 |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_I2C |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_CMD_PCI |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
/* The mac addresses for all ethernet interface */ |
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_ETHADDR 02:E0:0C:00:00:01 |
||||
#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD |
||||
#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD |
||||
#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD |
||||
#endif |
||||
|
||||
#define CONFIG_HAS_ETH1 1 |
||||
#define CONFIG_HAS_ETH2 1 |
||||
#define CONFIG_HAS_ETH3 1 |
||||
|
||||
#define CONFIG_IPADDR 192.168.0.50 |
||||
|
||||
#define CONFIG_HOSTNAME sbc8641d |
||||
#define CONFIG_ROOTPATH /opt/eldk/ppc_74xx |
||||
#define CONFIG_BOOTFILE uImage |
||||
|
||||
#define CONFIG_SERVERIP 192.168.0.2 |
||||
#define CONFIG_GATEWAYIP 192.168.0.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
|
||||
/* default location for tftp and bootm */ |
||||
#define CONFIG_LOADADDR 1000000 |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=uRamdisk\0" \
|
||||
"dtbaddr=400000\0" \
|
||||
"dtbfile=sbc8641d.dtb\0" \
|
||||
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
|
||||
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
|
||||
"maxcpus=1" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $dtbaddr $dtbfile;" \
|
||||
"bootm $loadaddr - $dtbaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $dtbaddr $dtbfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $dtbaddr" |
||||
|
||||
#define CONFIG_FLASHBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"bootm ffd00000 ffb00000 ffa00000" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue