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@ -784,6 +784,14 @@ |
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#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ |
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#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ |
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#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ |
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#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ |
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#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ |
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/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ |
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#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ |
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#define CPC0_ECR (0xaa) /* edge conditioner register */ |
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#define ecr (0xaa) /* edge conditioner register (405gpr) */ |
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/* Bit definitions */ |
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