These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Dave Liu <daveliu@freescale.com> Cc: Anton Vorontsov <avorontsov@ru.mvista.com>master
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@ -1,12 +0,0 @@ |
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if TARGET_MPC8360EMDS |
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|
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config SYS_BOARD |
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default "mpc8360emds" |
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|
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config SYS_VENDOR |
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default "freescale" |
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|
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config SYS_CONFIG_NAME |
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default "MPC8360EMDS" |
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|
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endif |
@ -1,15 +0,0 @@ |
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MPC8360EMDS BOARD |
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M: Dave Liu <daveliu@freescale.com> |
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S: Maintained |
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F: board/freescale/mpc8360emds/ |
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F: include/configs/MPC8360EMDS.h |
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F: configs/MPC8360EMDS_33_defconfig |
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F: configs/MPC8360EMDS_33_ATM_defconfig |
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F: configs/MPC8360EMDS_33_HOST_33_defconfig |
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F: configs/MPC8360EMDS_33_HOST_66_defconfig |
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F: configs/MPC8360EMDS_33_SLAVE_defconfig |
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F: configs/MPC8360EMDS_66_defconfig |
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F: configs/MPC8360EMDS_66_ATM_defconfig |
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F: configs/MPC8360EMDS_66_HOST_33_defconfig |
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F: configs/MPC8360EMDS_66_HOST_66_defconfig |
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F: configs/MPC8360EMDS_66_SLAVE_defconfig |
@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += mpc8360emds.o
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obj-$(CONFIG_PCI) += pci.o
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@ -1,155 +0,0 @@ |
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Freescale MPC8360EMDS Board |
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----------------------------------------- |
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1. Board Switches and Jumpers |
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1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board |
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For some reason, the HW designers describe the switch settings |
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in terms of 0 and 1, and then map that to physical switches where |
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the label "On" refers to logic 0 and "Off" is logic 1. |
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|
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Switch bits are numbered 1 through, like, 4 6 8 or 10, but the |
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bits may contribute to signals that are numbered based at 0, |
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and some of those signals may be high-bit-number-0 too. Heed |
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well the names and labels and do not get confused. |
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|
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"Off" == 1 |
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"On" == 0 |
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|
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SW18 is switch 18 as silk-screened onto the board. |
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SW4[8] is the bit labeled 8 on Switch 4. |
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SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. |
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SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3. |
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SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" |
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and bits labeled 8 is set as "Off". |
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|
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1.1 There are three type boards for MPC8360E silicon up to now, They are |
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* MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE) |
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* MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT) |
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* MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE) |
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|
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1.2 For all the MPC8360EMDS Board |
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|
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First, make sure the board default setting is consistent with the |
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document shipped with your board. Then apply the following setting: |
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SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus) |
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SW4[1-8]= 0011_0000 (Flash boot on local bus) |
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SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH) |
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SW10[1-8]= 0000_1000 (core PLL setting) |
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SW11[1-8]= 0000_0100 (SW11 is on the another side of the board) |
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JP6 1-2 |
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on board Oscillator: 66M |
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|
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1.3 Since different board/chip rev. combinations have AC timing issues, |
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u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default |
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by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers). |
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|
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When the rev2.x silicon mount on these boards, and if you are using |
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u-boot version after this patch, to make the ethernet interfaces usable, |
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and to enable RGMII-ID on your board, you have to setup the jumpers |
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correctly. |
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|
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* MPC8360E-MDS-PB PROTO |
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nothing to do |
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* MPC8360E-MDS-PB PILOT |
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JP9 and JP8 should be ON |
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* MPC8360EA-MDS-PB PROTO |
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JP2 and JP3 should be ON |
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|
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2. Memory Map |
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2.1. The memory map should look pretty much like this: |
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0x0000_0000 0x7fff_ffff DDR 2G |
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0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M |
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0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M |
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0xc000_0000 0xdfff_ffff Empty 512M |
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0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M |
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0xe020_0000 0xe02f_ffff Empty 1M |
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0xe030_0000 0xe03f_ffff PCI IO 1M |
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0xe040_0000 0xefff_ffff Empty 252M |
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0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M |
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0xf400_0000 0xf7ff_ffff Empty 64M |
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0xf800_0000 0xf800_7fff BCSR on CS1 32K |
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0xf800_8000 0xf800_ffff PIB CS4 32K |
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0xf801_0000 0xf801_7fff PIB CS5 32K |
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0xfe00_0000 0xfeff_ffff FLASH on CS0 16M |
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3. Definitions |
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3.1 Explanation of NEW definitions in: |
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include/configs/MPC8360EMDS.h |
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CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 |
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CONFIG_MPC8360 MPC8360 specific |
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CONFIG_MPC8360EMDS MPC8360EMDS board specific |
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|
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4. Compilation |
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MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip). |
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Assuming you're using BASH shell: |
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export CROSS_COMPILE=your-cross-compile-prefix |
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cd u-boot |
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make distclean |
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make MPC8360EMDS_XX_config |
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make |
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|
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MPC8360EMDS support ATM, PCI in host and slave mode. |
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To make u-boot support ATM : |
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1) Make MPC8360EMDS_XX_ATM_config |
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To make u-boot support PCI host 66M : |
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1) DIP SW support PCI mode as described in Section 1.1. |
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2) Make MPC8360EMDS_XX_HOST_66_config |
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To make u-boot support PCI host 33M : |
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1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1 |
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2) Make MPC8360EMDS_XX_HOST_33_config |
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To make u-boot support PCI slave 66M : |
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1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1 |
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2) Make MPC8360EMDS_XX_SLAVE_config |
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(where XX is: |
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33 - 33.33MHz oscillator |
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66 - 66MHz oscillator) |
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5. Downloading and Flashing Images |
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5.0 Download over serial line using Kermit: |
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loadb |
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[Drop to kermit: |
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^\c |
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send <u-boot-bin-image> |
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c |
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] |
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Or via tftp: |
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tftp 10000 u-boot.bin |
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5.1 Reflash U-boot Image using U-boot |
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tftp 20000 u-boot.bin |
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protect off fef00000 fef3ffff |
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erase fef00000 fef3ffff |
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cp.b 20000 fef00000 xxxx |
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or |
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cp.b 20000 fef00000 3ffff |
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You have to supply the correct byte count with 'xxxx' from the TFTP result log. |
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Maybe 3ffff will work too, that corresponds to the erased sectors. |
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6. Notes |
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1) The console baudrate for MPC8360EMDS is 115200bps. |
@ -1,453 +0,0 @@ |
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/*
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* Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc. |
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* Dave Liu <daveliu@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc83xx.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <phy.h> |
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#include <fsl_mdio.h> |
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#if defined(CONFIG_PCI) |
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#include <pci.h> |
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#endif |
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#include <spd_sdram.h> |
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#include <asm/mmu.h> |
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#include <asm/io.h> |
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#include <asm/mmu.h> |
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#if defined(CONFIG_OF_LIBFDT) |
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#include <libfdt.h> |
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#endif |
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#include <hwconfig.h> |
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#include <fdt_support.h> |
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#if defined(CONFIG_PQ_MDS_PIB) |
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#include "../common/pq-mds-pib.h" |
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#endif |
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#include "../../../drivers/qe/uec.h" |
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const qe_iop_conf_t qe_iop_conf_tab[] = { |
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/* GETH1 */ |
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{0, 3, 1, 0, 1}, /* TxD0 */ |
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{0, 4, 1, 0, 1}, /* TxD1 */ |
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{0, 5, 1, 0, 1}, /* TxD2 */ |
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{0, 6, 1, 0, 1}, /* TxD3 */ |
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{1, 6, 1, 0, 3}, /* TxD4 */ |
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{1, 7, 1, 0, 1}, /* TxD5 */ |
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{1, 9, 1, 0, 2}, /* TxD6 */ |
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{1, 10, 1, 0, 2}, /* TxD7 */ |
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{0, 9, 2, 0, 1}, /* RxD0 */ |
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{0, 10, 2, 0, 1}, /* RxD1 */ |
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{0, 11, 2, 0, 1}, /* RxD2 */ |
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{0, 12, 2, 0, 1}, /* RxD3 */ |
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{0, 13, 2, 0, 1}, /* RxD4 */ |
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{1, 1, 2, 0, 2}, /* RxD5 */ |
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{1, 0, 2, 0, 2}, /* RxD6 */ |
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{1, 4, 2, 0, 2}, /* RxD7 */ |
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{0, 7, 1, 0, 1}, /* TX_EN */ |
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{0, 8, 1, 0, 1}, /* TX_ER */ |
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{0, 15, 2, 0, 1}, /* RX_DV */ |
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{0, 16, 2, 0, 1}, /* RX_ER */ |
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{0, 0, 2, 0, 1}, /* RX_CLK */ |
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{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ |
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{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ |
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/* GETH2 */ |
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{0, 17, 1, 0, 1}, /* TxD0 */ |
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{0, 18, 1, 0, 1}, /* TxD1 */ |
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{0, 19, 1, 0, 1}, /* TxD2 */ |
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{0, 20, 1, 0, 1}, /* TxD3 */ |
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{1, 2, 1, 0, 1}, /* TxD4 */ |
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{1, 3, 1, 0, 2}, /* TxD5 */ |
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{1, 5, 1, 0, 3}, /* TxD6 */ |
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{1, 8, 1, 0, 3}, /* TxD7 */ |
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{0, 23, 2, 0, 1}, /* RxD0 */ |
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{0, 24, 2, 0, 1}, /* RxD1 */ |
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{0, 25, 2, 0, 1}, /* RxD2 */ |
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{0, 26, 2, 0, 1}, /* RxD3 */ |
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{0, 27, 2, 0, 1}, /* RxD4 */ |
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{1, 12, 2, 0, 2}, /* RxD5 */ |
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{1, 13, 2, 0, 3}, /* RxD6 */ |
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{1, 11, 2, 0, 2}, /* RxD7 */ |
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{0, 21, 1, 0, 1}, /* TX_EN */ |
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{0, 22, 1, 0, 1}, /* TX_ER */ |
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{0, 29, 2, 0, 1}, /* RX_DV */ |
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{0, 30, 2, 0, 1}, /* RX_ER */ |
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{0, 31, 2, 0, 1}, /* RX_CLK */ |
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{2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ |
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{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ |
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{0, 1, 3, 0, 2}, /* MDIO */ |
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{0, 2, 1, 0, 1}, /* MDC */ |
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{5, 0, 1, 0, 2}, /* UART2_SOUT */ |
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{5, 1, 2, 0, 3}, /* UART2_CTS */ |
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{5, 2, 1, 0, 1}, /* UART2_RTS */ |
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{5, 3, 2, 0, 2}, /* UART2_SIN */ |
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ |
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}; |
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/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */ |
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static int board_handle_erratum2(void) |
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{ |
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const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
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return REVID_MAJOR(immr->sysconf.spridr) == 2 && |
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REVID_MINOR(immr->sysconf.spridr) == 1; |
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} |
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int board_early_init_f(void) |
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{ |
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const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
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u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; |
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/* Enable flash write */ |
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bcsr[0xa] &= ~0x04; |
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/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */ |
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if (REVID_MAJOR(immr->sysconf.spridr) == 2) |
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bcsr[0xe] = 0x30; |
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/* Enable second UART */ |
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bcsr[0x9] &= ~0x01; |
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if (board_handle_erratum2()) { |
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void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8); |
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/*
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* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) |
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* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) |
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*/ |
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setbits_be32(immap, 0x0c003000); |
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/*
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* IMMR + 0x14AC[20:27] = 10101010 |
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* (data delay for both UCC's) |
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*/ |
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clrsetbits_be32(immap + 4, 0xff0, 0xaa0); |
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} |
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return 0; |
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} |
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int board_early_init_r(void) |
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{ |
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gd_t *gd; |
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#ifdef CONFIG_PQ_MDS_PIB |
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pib_init(); |
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#endif |
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/*
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* BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB |
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* So re-setup PCI MEM space used BAT5 after relocated to DDR |
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*/ |
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gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
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if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { |
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write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); |
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write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); |
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} |
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return 0; |
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} |
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#ifdef CONFIG_UEC_ETH |
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static uec_info_t uec_info[] = { |
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#ifdef CONFIG_UEC_ETH1 |
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STD_UEC_INFO(1), |
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#endif |
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#ifdef CONFIG_UEC_ETH2 |
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STD_UEC_INFO(2), |
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#endif |
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}; |
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int board_eth_init(bd_t *bd) |
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{ |
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if (board_handle_erratum2()) { |
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int i; |
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for (i = 0; i < ARRAY_SIZE(uec_info); i++) { |
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uec_info[i].enet_interface_type = |
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PHY_INTERFACE_MODE_RGMII_RXID; |
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uec_info[i].speed = SPEED_1000; |
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} |
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} |
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return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); |
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} |
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#endif /* CONFIG_UEC_ETH */ |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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extern void ddr_enable_ecc(unsigned int dram_size); |
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#endif |
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int fixed_sdram(void); |
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static int sdram_init(unsigned int base); |
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phys_size_t initdram(int board_type) |
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{ |
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
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u32 msize = 0; |
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u32 lbc_sdram_size; |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; |
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#if defined(CONFIG_SPD_EEPROM) |
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msize = spd_sdram(); |
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#else |
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msize = fixed_sdram(); |
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#endif |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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/*
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* Initialize DDR ECC byte |
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*/ |
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ddr_enable_ecc(msize * 1024 * 1024); |
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#endif |
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/*
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* Initialize SDRAM if it is on local bus. |
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*/ |
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lbc_sdram_size = sdram_init(msize * 1024 * 1024); |
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if (!msize) |
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msize = lbc_sdram_size; |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return (msize * 1024 * 1024); |
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} |
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#if !defined(CONFIG_SPD_EEPROM) |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
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u32 msize = CONFIG_SYS_DDR_SIZE; |
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u32 ddr_size = msize << 20; |
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u32 ddr_size_log2 = __ilog2(ddr_size); |
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u32 half_ddr_size = ddr_size >> 1; |
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im->sysconf.ddrlaw[0].bar = |
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CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; |
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im->sysconf.ddrlaw[0].ar = |
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
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#if (CONFIG_SYS_DDR_SIZE != 256) |
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#warning Currenly any ddr size other than 256 is not supported |
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#endif |
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#ifdef CONFIG_DDR_II |
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; |
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; |
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; |
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; |
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; |
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; |
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; |
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#else |
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|
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) |
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#warning Chip select bounds is only configurable in 16MB increments |
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#endif |
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im->ddr.csbnds[0].csbnds = |
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | |
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(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >> |
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CSBNDS_EA_SHIFT) & CSBNDS_EA); |
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im->ddr.csbnds[1].csbnds = |
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(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >> |
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CSBNDS_SA_SHIFT) & CSBNDS_SA) | |
||||
(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> |
||||
CSBNDS_EA_SHIFT) & CSBNDS_EA); |
||||
|
||||
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; |
||||
im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG; |
||||
|
||||
im->ddr.cs_config[2] = 0; |
||||
im->ddr.cs_config[3] = 0; |
||||
|
||||
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
||||
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
||||
im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
||||
|
||||
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; |
||||
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
||||
#endif |
||||
udelay(200); |
||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
||||
|
||||
return msize; |
||||
} |
||||
#endif /*!CONFIG_SYS_SPD_EEPROM */ |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: Freescale MPC8360EMDS\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* if MPC8360EMDS is soldered with SDRAM |
||||
*/ |
||||
#ifdef CONFIG_SYS_LB_SDRAM |
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus. |
||||
*/ |
||||
|
||||
static int sdram_init(unsigned int base) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
fsl_lbc_t *lbc = LBC_BASE_ADDR; |
||||
const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; |
||||
int rem = base % sdram_size; |
||||
uint *sdram_addr; |
||||
|
||||
/* window base address should be aligned to the window size */ |
||||
if (rem) |
||||
base = base - rem + sdram_size; |
||||
|
||||
/*
|
||||
* Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB |
||||
* After relocated to DDR, reuse BAT5 for PCI MEM space |
||||
*/ |
||||
if (base > CONFIG_MAX_MEM_MAPPED) { |
||||
unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; |
||||
unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; |
||||
|
||||
/* Setup the BAT6 for SDRAM */ |
||||
write_bat(DBAT6, batu, batl); |
||||
write_bat(IBAT6, batu, batl); |
||||
} |
||||
|
||||
sdram_addr = (uint *)base; |
||||
/*
|
||||
* Setup SDRAM Base and Option Registers |
||||
*/ |
||||
set_lbc_br(2, base | CONFIG_SYS_BR2); |
||||
set_lbc_or(2, CONFIG_SYS_OR2); |
||||
immap->sysconf.lblaw[2].bar = base; |
||||
immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2; |
||||
|
||||
/*setup mtrpt, lsrt and lbcr for LB bus */ |
||||
lbc->lbcr = CONFIG_SYS_LBC_LBCR; |
||||
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; |
||||
lbc->lsrt = CONFIG_SYS_LBC_LSRT; |
||||
asm("sync"); |
||||
|
||||
/*
|
||||
* Configure the SDRAM controller Machine Mode Register. |
||||
*/ |
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */ |
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */ |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
|
||||
/*
|
||||
* We need do 8 times auto refresh operation. |
||||
*/ |
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; /* 1 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 2 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 3 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 4 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 5 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 6 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 7 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 8 times */ |
||||
udelay(100); |
||||
|
||||
/* Mode register write operation */ |
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; |
||||
asm("sync"); |
||||
*(sdram_addr + 0xcc) = 0xff; |
||||
udelay(100); |
||||
|
||||
/* Normal operation */ |
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
|
||||
/*
|
||||
* In non-aligned case we don't [normally] use that memory because |
||||
* there is a hole. |
||||
*/ |
||||
if (rem) |
||||
return 0; |
||||
return CONFIG_SYS_LBC_SDRAM_SIZE; |
||||
} |
||||
#else |
||||
static int sdram_init(unsigned int base) { return 0; } |
||||
#endif |
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) |
||||
static void ft_board_fixup_qe_usb(void *blob, bd_t *bd) |
||||
{ |
||||
if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) |
||||
return; |
||||
|
||||
do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode", |
||||
"peripheral", sizeof("peripheral"), 1); |
||||
} |
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
ft_cpu_setup(blob, bd); |
||||
#ifdef CONFIG_PCI |
||||
ft_pci_setup(blob, bd); |
||||
#endif |
||||
ft_board_fixup_qe_usb(blob, bd); |
||||
/*
|
||||
* mpc8360ea pb mds errata 2: RGMII timing |
||||
* if on mpc8360ea rev. 2.1, |
||||
* change both ucc phy-connection-types from rgmii-id to rgmii-rxid |
||||
*/ |
||||
if (board_handle_erratum2()) { |
||||
int nodeoffset; |
||||
const char *prop; |
||||
int path; |
||||
|
||||
nodeoffset = fdt_path_offset(blob, "/aliases"); |
||||
if (nodeoffset >= 0) { |
||||
#if defined(CONFIG_HAS_ETH0) |
||||
/* fixup UCC 1 if using rgmii-id mode */ |
||||
prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); |
||||
if (prop) { |
||||
path = fdt_path_offset(blob, prop); |
||||
prop = fdt_getprop(blob, path, |
||||
"phy-connection-type", 0); |
||||
if (prop && (strcmp(prop, "rgmii-id") == 0)) |
||||
fdt_fixup_phy_connection(blob, path, |
||||
PHY_INTERFACE_MODE_RGMII_RXID); |
||||
} |
||||
#endif |
||||
#if defined(CONFIG_HAS_ETH1) |
||||
/* fixup UCC 2 if using rgmii-id mode */ |
||||
prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); |
||||
if (prop) { |
||||
path = fdt_path_offset(blob, prop); |
||||
prop = fdt_getprop(blob, path, |
||||
"phy-connection-type", 0); |
||||
if (prop && (strcmp(prop, "rgmii-id") == 0)) |
||||
fdt_fixup_phy_connection(blob, path, |
||||
PHY_INTERFACE_MODE_RGMII_RXID); |
||||
} |
||||
#endif |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
@ -1,147 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* PCI Configuration space access support for MPC83xx PCI Bridge |
||||
*/ |
||||
|
||||
#include <asm/mmu.h> |
||||
#include <asm/io.h> |
||||
#include <common.h> |
||||
#include <mpc83xx.h> |
||||
#include <pci.h> |
||||
#include <i2c.h> |
||||
#include <asm/fsl_i2c.h> |
||||
#include "../common/pq-mds-pib.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static struct pci_region pci1_regions[] = { |
||||
{ |
||||
bus_start: CONFIG_SYS_PCI1_MEM_BASE, |
||||
phys_start: CONFIG_SYS_PCI1_MEM_PHYS, |
||||
size: CONFIG_SYS_PCI1_MEM_SIZE, |
||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH |
||||
}, |
||||
{ |
||||
bus_start: CONFIG_SYS_PCI1_IO_BASE, |
||||
phys_start: CONFIG_SYS_PCI1_IO_PHYS, |
||||
size: CONFIG_SYS_PCI1_IO_SIZE, |
||||
flags: PCI_REGION_IO |
||||
}, |
||||
{ |
||||
bus_start: CONFIG_SYS_PCI1_MMIO_BASE, |
||||
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, |
||||
size: CONFIG_SYS_PCI1_MMIO_SIZE, |
||||
flags: PCI_REGION_MEM |
||||
}, |
||||
}; |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
static struct pci_region pci2_regions[] = { |
||||
{ |
||||
bus_start: CONFIG_SYS_PCI2_MEM_BASE, |
||||
phys_start: CONFIG_SYS_PCI2_MEM_PHYS, |
||||
size: CONFIG_SYS_PCI2_MEM_SIZE, |
||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH |
||||
}, |
||||
{ |
||||
bus_start: CONFIG_SYS_PCI2_IO_BASE, |
||||
phys_start: CONFIG_SYS_PCI2_IO_PHYS, |
||||
size: CONFIG_SYS_PCI2_IO_SIZE, |
||||
flags: PCI_REGION_IO |
||||
}, |
||||
{ |
||||
bus_start: CONFIG_SYS_PCI2_MMIO_BASE, |
||||
phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, |
||||
size: CONFIG_SYS_PCI2_MMIO_SIZE, |
||||
flags: PCI_REGION_MEM |
||||
}, |
||||
}; |
||||
#endif |
||||
|
||||
void pci_init_board(void) |
||||
#ifdef CONFIG_PCISLAVE |
||||
{ |
||||
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; |
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw; |
||||
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; |
||||
struct pci_region *reg[] = { pci1_regions }; |
||||
|
||||
/* Configure PCI Local Access Windows */ |
||||
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; |
||||
|
||||
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; |
||||
|
||||
mpc83xx_pci_init(1, reg); |
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
pci_ctrl[0].pitar0 = 0x0; |
||||
pci_ctrl[0].pibar0 = 0x0; |
||||
pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | |
||||
PIWAR_WTT_SNOOP | PIWAR_IWS_4K; |
||||
|
||||
pci_ctrl[0].pitar1 = 0x0; |
||||
pci_ctrl[0].pibar1 = 0x0; |
||||
pci_ctrl[0].piebar1 = 0x0; |
||||
pci_ctrl[0].piwar1 &= ~PIWAR_EN; |
||||
|
||||
pci_ctrl[0].pitar2 = 0x0; |
||||
pci_ctrl[0].pibar2 = 0x0; |
||||
pci_ctrl[0].piebar2 = 0x0; |
||||
pci_ctrl[0].piwar2 &= ~PIWAR_EN; |
||||
|
||||
/* Unlock the configuration bit */ |
||||
mpc83xx_pcislave_unlock(0); |
||||
printf("PCI: Agent mode enabled\n"); |
||||
} |
||||
#else |
||||
{ |
||||
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; |
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; |
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw; |
||||
#ifndef CONFIG_MPC83XX_PCI2 |
||||
struct pci_region *reg[] = { pci1_regions }; |
||||
#else |
||||
struct pci_region *reg[] = { pci1_regions, pci2_regions }; |
||||
#endif |
||||
|
||||
/* initialize the PCA9555PW IO expander on the PIB board */ |
||||
pib_init(); |
||||
|
||||
#if defined(CONFIG_PCI_66M) |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
||||
printf("PCI clock is 66MHz\n"); |
||||
#elif defined(CONFIG_PCI_33M) |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | |
||||
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; |
||||
printf("PCI clock is 33MHz\n"); |
||||
#else |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
||||
printf("PCI clock is 66MHz\n"); |
||||
#endif |
||||
udelay(2000); |
||||
|
||||
/* Configure PCI Local Access Windows */ |
||||
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; |
||||
|
||||
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; |
||||
|
||||
udelay(2000); |
||||
|
||||
#ifndef CONFIG_MPC83XX_PCI2 |
||||
mpc83xx_pci_init(1, reg); |
||||
#else |
||||
mpc83xx_pci_init(2, reg); |
||||
#endif |
||||
} |
||||
#endif /* CONFIG_PCISLAVE */ |
@ -1,12 +0,0 @@ |
||||
if TARGET_MPC8360ERDK |
||||
|
||||
config SYS_BOARD |
||||
default "mpc8360erdk" |
||||
|
||||
config SYS_VENDOR |
||||
default "freescale" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "MPC8360ERDK" |
||||
|
||||
endif |
@ -1,7 +0,0 @@ |
||||
MPC8360ERDK BOARD |
||||
#M: Anton Vorontsov <avorontsov@ru.mvista.com> |
||||
S: Orphan (since 2014-03) |
||||
F: board/freescale/mpc8360erdk/ |
||||
F: include/configs/MPC8360ERDK.h |
||||
F: configs/MPC8360ERDK_defconfig |
||||
F: configs/MPC8360ERDK_33_defconfig |
@ -1,9 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += mpc8360erdk.o
|
||||
obj-$(CONFIG_CMD_NAND) += nand.o
|
@ -1,350 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* |
||||
* Copyright (C) 2007 Logic Product Development, Inc. |
||||
* Peter Barada <peterb@logicpd.com> |
||||
* |
||||
* Copyright (C) 2007 MontaVista Software, Inc. |
||||
* Anton Vorontsov <avorontsov@ru.mvista.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <mpc83xx.h> |
||||
#include <i2c.h> |
||||
#include <miiphy.h> |
||||
#include <asm/io.h> |
||||
#include <asm/mmu.h> |
||||
#include <pci.h> |
||||
#include <libfdt.h> |
||||
|
||||
const qe_iop_conf_t qe_iop_conf_tab[] = { |
||||
/* MDIO */ |
||||
{0, 1, 3, 0, 2}, /* MDIO */ |
||||
{0, 2, 1, 0, 1}, /* MDC */ |
||||
|
||||
/* UCC1 - UEC (Gigabit) */ |
||||
{0, 3, 1, 0, 1}, /* TxD0 */ |
||||
{0, 4, 1, 0, 1}, /* TxD1 */ |
||||
{0, 5, 1, 0, 1}, /* TxD2 */ |
||||
{0, 6, 1, 0, 1}, /* TxD3 */ |
||||
{0, 9, 2, 0, 1}, /* RxD0 */ |
||||
{0, 10, 2, 0, 1}, /* RxD1 */ |
||||
{0, 11, 2, 0, 1}, /* RxD2 */ |
||||
{0, 12, 2, 0, 1}, /* RxD3 */ |
||||
{0, 7, 1, 0, 1}, /* TX_EN */ |
||||
{0, 8, 1, 0, 1}, /* TX_ER */ |
||||
{0, 15, 2, 0, 1}, /* RX_DV */ |
||||
{0, 0, 2, 0, 1}, /* RX_CLK */ |
||||
{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ |
||||
{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ |
||||
|
||||
/* UCC2 - UEC (Gigabit) */ |
||||
{0, 17, 1, 0, 1}, /* TxD0 */ |
||||
{0, 18, 1, 0, 1}, /* TxD1 */ |
||||
{0, 19, 1, 0, 1}, /* TxD2 */ |
||||
{0, 20, 1, 0, 1}, /* TxD3 */ |
||||
{0, 23, 2, 0, 1}, /* RxD0 */ |
||||
{0, 24, 2, 0, 1}, /* RxD1 */ |
||||
{0, 25, 2, 0, 1}, /* RxD2 */ |
||||
{0, 26, 2, 0, 1}, /* RxD3 */ |
||||
{0, 21, 1, 0, 1}, /* TX_EN */ |
||||
{0, 22, 1, 0, 1}, /* TX_ER */ |
||||
{0, 29, 2, 0, 1}, /* RX_DV */ |
||||
{0, 31, 2, 0, 1}, /* RX_CLK */ |
||||
{2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */ |
||||
{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ |
||||
|
||||
/* UCC7 - UEC */ |
||||
{4, 0, 1, 0, 1}, /* TxD0 */ |
||||
{4, 1, 1, 0, 1}, /* TxD1 */ |
||||
{4, 2, 1, 0, 1}, /* TxD2 */ |
||||
{4, 3, 1, 0, 1}, /* TxD3 */ |
||||
{4, 6, 2, 0, 1}, /* RxD0 */ |
||||
{4, 7, 2, 0, 1}, /* RxD1 */ |
||||
{4, 8, 2, 0, 1}, /* RxD2 */ |
||||
{4, 9, 2, 0, 1}, /* RxD3 */ |
||||
{4, 4, 1, 0, 1}, /* TX_EN */ |
||||
{4, 5, 1, 0, 1}, /* TX_ER */ |
||||
{4, 12, 2, 0, 1}, /* RX_DV */ |
||||
{4, 13, 2, 0, 1}, /* RX_ER */ |
||||
{4, 10, 2, 0, 1}, /* COL */ |
||||
{4, 11, 2, 0, 1}, /* CRS */ |
||||
{2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */ |
||||
{2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */ |
||||
|
||||
/* UCC4 - UEC */ |
||||
{1, 14, 1, 0, 1}, /* TxD0 */ |
||||
{1, 15, 1, 0, 1}, /* TxD1 */ |
||||
{1, 16, 1, 0, 1}, /* TxD2 */ |
||||
{1, 17, 1, 0, 1}, /* TxD3 */ |
||||
{1, 20, 2, 0, 1}, /* RxD0 */ |
||||
{1, 21, 2, 0, 1}, /* RxD1 */ |
||||
{1, 22, 2, 0, 1}, /* RxD2 */ |
||||
{1, 23, 2, 0, 1}, /* RxD3 */ |
||||
{1, 18, 1, 0, 1}, /* TX_EN */ |
||||
{1, 19, 1, 0, 2}, /* TX_ER */ |
||||
{1, 26, 2, 0, 1}, /* RX_DV */ |
||||
{1, 27, 2, 0, 1}, /* RX_ER */ |
||||
{1, 24, 2, 0, 1}, /* COL */ |
||||
{1, 25, 2, 0, 1}, /* CRS */ |
||||
{2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */ |
||||
{2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */ |
||||
|
||||
/* PCI1 */ |
||||
{5, 4, 2, 0, 3}, /* PCI_M66EN */ |
||||
{5, 5, 1, 0, 3}, /* PCI_INTA */ |
||||
{5, 6, 1, 0, 3}, /* PCI_RSTO */ |
||||
{5, 7, 3, 0, 3}, /* PCI_C_BE0 */ |
||||
{5, 8, 3, 0, 3}, /* PCI_C_BE1 */ |
||||
{5, 9, 3, 0, 3}, /* PCI_C_BE2 */ |
||||
{5, 10, 3, 0, 3}, /* PCI_C_BE3 */ |
||||
{5, 11, 3, 0, 3}, /* PCI_PAR */ |
||||
{5, 12, 3, 0, 3}, /* PCI_FRAME */ |
||||
{5, 13, 3, 0, 3}, /* PCI_TRDY */ |
||||
{5, 14, 3, 0, 3}, /* PCI_IRDY */ |
||||
{5, 15, 3, 0, 3}, /* PCI_STOP */ |
||||
{5, 16, 3, 0, 3}, /* PCI_DEVSEL */ |
||||
{5, 17, 0, 0, 0}, /* PCI_IDSEL */ |
||||
{5, 18, 3, 0, 3}, /* PCI_SERR */ |
||||
{5, 19, 3, 0, 3}, /* PCI_PERR */ |
||||
{5, 20, 3, 0, 3}, /* PCI_REQ0 */ |
||||
{5, 21, 2, 0, 3}, /* PCI_REQ1 */ |
||||
{5, 22, 2, 0, 3}, /* PCI_GNT2 */ |
||||
{5, 23, 3, 0, 3}, /* PCI_GNT0 */ |
||||
{5, 24, 1, 0, 3}, /* PCI_GNT1 */ |
||||
{5, 25, 1, 0, 3}, /* PCI_GNT2 */ |
||||
{5, 26, 0, 0, 0}, /* PCI_CLK0 */ |
||||
{5, 27, 0, 0, 0}, /* PCI_CLK1 */ |
||||
{5, 28, 0, 0, 0}, /* PCI_CLK2 */ |
||||
{5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */ |
||||
{6, 0, 3, 0, 3}, /* PCI_AD0 */ |
||||
{6, 1, 3, 0, 3}, /* PCI_AD1 */ |
||||
{6, 2, 3, 0, 3}, /* PCI_AD2 */ |
||||
{6, 3, 3, 0, 3}, /* PCI_AD3 */ |
||||
{6, 4, 3, 0, 3}, /* PCI_AD4 */ |
||||
{6, 5, 3, 0, 3}, /* PCI_AD5 */ |
||||
{6, 6, 3, 0, 3}, /* PCI_AD6 */ |
||||
{6, 7, 3, 0, 3}, /* PCI_AD7 */ |
||||
{6, 8, 3, 0, 3}, /* PCI_AD8 */ |
||||
{6, 9, 3, 0, 3}, /* PCI_AD9 */ |
||||
{6, 10, 3, 0, 3}, /* PCI_AD10 */ |
||||
{6, 11, 3, 0, 3}, /* PCI_AD11 */ |
||||
{6, 12, 3, 0, 3}, /* PCI_AD12 */ |
||||
{6, 13, 3, 0, 3}, /* PCI_AD13 */ |
||||
{6, 14, 3, 0, 3}, /* PCI_AD14 */ |
||||
{6, 15, 3, 0, 3}, /* PCI_AD15 */ |
||||
{6, 16, 3, 0, 3}, /* PCI_AD16 */ |
||||
{6, 17, 3, 0, 3}, /* PCI_AD17 */ |
||||
{6, 18, 3, 0, 3}, /* PCI_AD18 */ |
||||
{6, 19, 3, 0, 3}, /* PCI_AD19 */ |
||||
{6, 20, 3, 0, 3}, /* PCI_AD20 */ |
||||
{6, 21, 3, 0, 3}, /* PCI_AD21 */ |
||||
{6, 22, 3, 0, 3}, /* PCI_AD22 */ |
||||
{6, 23, 3, 0, 3}, /* PCI_AD23 */ |
||||
{6, 24, 3, 0, 3}, /* PCI_AD24 */ |
||||
{6, 25, 3, 0, 3}, /* PCI_AD25 */ |
||||
{6, 26, 3, 0, 3}, /* PCI_AD26 */ |
||||
{6, 27, 3, 0, 3}, /* PCI_AD27 */ |
||||
{6, 28, 3, 0, 3}, /* PCI_AD28 */ |
||||
{6, 29, 3, 0, 3}, /* PCI_AD29 */ |
||||
{6, 30, 3, 0, 3}, /* PCI_AD30 */ |
||||
{6, 31, 3, 0, 3}, /* PCI_AD31 */ |
||||
|
||||
/* NAND */ |
||||
{4, 18, 2, 0, 0}, /* NAND_RYnBY */ |
||||
|
||||
/* DUART - UART2 */ |
||||
{5, 0, 1, 0, 2}, /* UART2_SOUT */ |
||||
{5, 2, 1, 0, 1}, /* UART2_RTS */ |
||||
{5, 3, 2, 0, 2}, /* UART2_SIN */ |
||||
{5, 1, 2, 0, 3}, /* UART2_CTS */ |
||||
|
||||
/* UCC5 - UART3 */ |
||||
{3, 0, 1, 0, 1}, /* UART3_TX */ |
||||
{3, 4, 1, 0, 1}, /* UART3_RTS */ |
||||
{3, 6, 2, 0, 1}, /* UART3_RX */ |
||||
{3, 12, 2, 0, 0}, /* UART3_CTS */ |
||||
{3, 13, 2, 0, 0}, /* UCC5_CD */ |
||||
|
||||
/* UCC6 - UART4 */ |
||||
{3, 14, 1, 0, 1}, /* UART4_TX */ |
||||
{3, 18, 1, 0, 1}, /* UART4_RTS */ |
||||
{3, 20, 2, 0, 1}, /* UART4_RX */ |
||||
{3, 26, 2, 0, 0}, /* UART4_CTS */ |
||||
{3, 27, 2, 0, 0}, /* UCC6_CD */ |
||||
|
||||
/* Fujitsu MB86277 (MINT) graphics controller */ |
||||
{0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */ |
||||
{1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */ |
||||
{1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */ |
||||
{2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */ |
||||
|
||||
/* AD7843 ADC/Touchscreen controller */ |
||||
{4, 14, 1, 0, 0}, /* SPI_nCS0 */ |
||||
{4, 28, 3, 0, 3}, /* SPI_MOSI */ |
||||
{4, 29, 3, 0, 3}, /* SPI_MISO */ |
||||
{4, 30, 3, 0, 3}, /* SPI_CLK */ |
||||
|
||||
/* Freescale QUICC Engine USB Host Controller (FHCI) */ |
||||
{1, 2, 1, 0, 3}, /* USBOE */ |
||||
{1, 3, 1, 0, 3}, /* USBTP */ |
||||
{1, 8, 1, 0, 1}, /* USBTN */ |
||||
{1, 9, 2, 1, 3}, /* USBRP */ |
||||
{1, 10, 2, 0, 3}, /* USBRXD */ |
||||
{1, 11, 2, 1, 3}, /* USBRN */ |
||||
{2, 20, 2, 0, 1}, /* CLK21 */ |
||||
{4, 20, 1, 0, 0}, /* SPEED */ |
||||
{4, 21, 1, 0, 0}, /* SUSPND */ |
||||
|
||||
/* END of table */ |
||||
{0, 0, 0, 0, QE_IOP_TAB_END}, |
||||
}; |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); |
||||
u32 val; |
||||
|
||||
/*
|
||||
* Because of errata in the UCCs, we have to write to the reserved |
||||
* registers to slow the clocks down. |
||||
*/ |
||||
val = in_be32(reg); |
||||
/* UCC1 */ |
||||
val |= 0x00003000; |
||||
/* UCC2 */ |
||||
val |= 0x0c000000; |
||||
out_be32(reg, val); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int fixed_sdram(void) |
||||
{ |
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
||||
u32 msize = 0; |
||||
u32 ddr_size; |
||||
u32 ddr_size_log2; |
||||
|
||||
msize = CONFIG_SYS_DDR_SIZE; |
||||
for (ddr_size = msize << 20, ddr_size_log2 = 0; |
||||
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { |
||||
if (ddr_size & 1) |
||||
return -1; |
||||
} |
||||
|
||||
im->sysconf.ddrlaw[0].ar = |
||||
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
||||
|
||||
im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; |
||||
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; |
||||
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
||||
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
||||
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
||||
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
||||
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; |
||||
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; |
||||
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; |
||||
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; |
||||
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
||||
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; |
||||
udelay(200); |
||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
||||
|
||||
return msize; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
extern void ddr_enable_ecc(unsigned int dram_size); |
||||
#endif |
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
||||
u32 msize = 0; |
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
||||
return -1; |
||||
|
||||
/* DDR SDRAM - Main SODIMM */ |
||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; |
||||
msize = fixed_sdram(); |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
/*
|
||||
* Initialize DDR ECC byte |
||||
*/ |
||||
ddr_enable_ecc(msize * 1024 * 1024); |
||||
#endif |
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */ |
||||
return (msize * 1024 * 1024); |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: Freescale/Logic MPC8360ERDK\n"); |
||||
return 0; |
||||
} |
||||
|
||||
static struct pci_region pci_regions[] = { |
||||
{ |
||||
.bus_start = CONFIG_SYS_PCI1_MEM_BASE, |
||||
.phys_start = CONFIG_SYS_PCI1_MEM_PHYS, |
||||
.size = CONFIG_SYS_PCI1_MEM_SIZE, |
||||
.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH, |
||||
}, |
||||
{ |
||||
.bus_start = CONFIG_SYS_PCI1_MMIO_BASE, |
||||
.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS, |
||||
.size = CONFIG_SYS_PCI1_MMIO_SIZE, |
||||
.flags = PCI_REGION_MEM, |
||||
}, |
||||
{ |
||||
.bus_start = CONFIG_SYS_PCI1_IO_BASE, |
||||
.phys_start = CONFIG_SYS_PCI1_IO_PHYS, |
||||
.size = CONFIG_SYS_PCI1_IO_SIZE, |
||||
.flags = PCI_REGION_IO, |
||||
}, |
||||
}; |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; |
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; |
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw; |
||||
struct pci_region *reg[] = { pci_regions, }; |
||||
|
||||
#if defined(CONFIG_PCI_33M) |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | |
||||
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; |
||||
printf("PCI clock is 33MHz\n"); |
||||
#else |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
||||
printf("PCI clock is 66MHz\n"); |
||||
#endif |
||||
|
||||
udelay(2000); |
||||
|
||||
/* Configure PCI Local Access Windows */ |
||||
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; |
||||
|
||||
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; |
||||
|
||||
mpc83xx_pci_init(1, reg); |
||||
} |
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) |
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
ft_cpu_setup(blob, bd); |
||||
ft_pci_setup(blob, bd); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
@ -1,89 +0,0 @@ |
||||
/*
|
||||
* MPC8360E-RDK support for the NAND on FSL UPM |
||||
* |
||||
* Copyright (C) 2007 MontaVista Software, Inc. |
||||
* Anton Vorontsov <avorontsov@ru.mvista.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/immap_83xx.h> |
||||
#include <linux/mtd/mtd.h> |
||||
#include <linux/mtd/fsl_upm.h> |
||||
#include <nand.h> |
||||
|
||||
static struct immap *im = (struct immap *)CONFIG_SYS_IMMR; |
||||
|
||||
static const u32 upm_array[] = { |
||||
0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */ |
||||
0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */ |
||||
0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */ |
||||
0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */ |
||||
0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */ |
||||
0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */ |
||||
0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */ |
||||
0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */ |
||||
0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */ |
||||
0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */ |
||||
0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */ |
||||
0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */ |
||||
0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ |
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ |
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ |
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */ |
||||
}; |
||||
|
||||
static void upm_setup(struct fsl_upm *upm) |
||||
{ |
||||
int i; |
||||
|
||||
/* write upm array */ |
||||
out_be32(upm->mxmr, MxMR_OP_WARR); |
||||
|
||||
for (i = 0; i < 64; i++) { |
||||
out_be32(upm->mdr, upm_array[i]); |
||||
out_8(upm->io_addr, 0x0); |
||||
} |
||||
|
||||
/* normal operation */ |
||||
out_be32(upm->mxmr, MxMR_OP_NORM); |
||||
while (in_be32(upm->mxmr) != MxMR_OP_NORM) |
||||
eieio(); |
||||
} |
||||
|
||||
static int dev_ready(int chip_nr) |
||||
{ |
||||
if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) { |
||||
debug("nand ready\n"); |
||||
return 1; |
||||
} |
||||
|
||||
debug("nand busy\n"); |
||||
return 0; |
||||
} |
||||
|
||||
static struct fsl_upm_nand fun = { |
||||
.upm = { |
||||
.io_addr = (void *)CONFIG_SYS_NAND_BASE, |
||||
}, |
||||
.width = 8, |
||||
.upm_cmd_offset = 8, |
||||
.upm_addr_offset = 16, |
||||
.dev_ready = dev_ready, |
||||
.wait_flags = FSL_UPM_WAIT_RUN_PATTERN, |
||||
.chip_delay = 50, |
||||
}; |
||||
|
||||
int board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
fun.upm.mxmr = &im->im_lbc.mamr; |
||||
fun.upm.mdr = &im->im_lbc.mdr; |
||||
fun.upm.mar = &im->im_lbc.mar; |
||||
|
||||
upm_setup(&fun.upm); |
||||
|
||||
return fsl_upm_nand_init(nand, &fun); |
||||
} |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PCI,PCISLAVE" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PCI,PCISLAVE" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360EMDS=y |
@ -1,4 +0,0 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360ERDK=y |
@ -1,3 +0,0 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_MPC8360ERDK=y |
@ -1,735 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2006,2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 family */ |
||||
#define CONFIG_QE 1 /* Has QE */ |
||||
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
||||
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000 |
||||
|
||||
#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ |
||||
#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ |
||||
|
||||
/*
|
||||
* System Clock Setup |
||||
*/ |
||||
#ifdef CONFIG_CLKIN_33MHZ |
||||
#ifdef CONFIG_PCISLAVE |
||||
#define CONFIG_83XX_PCICLK 33330000 /* in HZ */ |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 33330000 /* in Hz */ |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#define CONFIG_SYS_CLK_FREQ 33330000 |
||||
#endif |
||||
|
||||
#elif defined(CONFIG_CLKIN_66MHZ) |
||||
#ifdef CONFIG_PCISLAVE |
||||
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#define CONFIG_SYS_CLK_FREQ 66000000 |
||||
#endif |
||||
#else |
||||
#error Unknown oscillator frequency. |
||||
#endif |
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word |
||||
*/ |
||||
#ifdef CONFIG_CLKIN_33MHZ |
||||
#define CONFIG_SYS_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_8X1 |\
|
||||
HRCWL_VCO_1X2 |\
|
||||
HRCWL_CE_PLL_VCO_DIV_4 |\
|
||||
HRCWL_CE_PLL_DIV_1X1 |\
|
||||
HRCWL_CE_TO_PLL_1X15 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
#elif defined(CONFIG_CLKIN_66MHZ) |
||||
#define CONFIG_SYS_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 |\
|
||||
HRCWL_VCO_1X2 |\
|
||||
HRCWL_CE_PLL_VCO_DIV_4 |\
|
||||
HRCWL_CE_PLL_DIV_1X1 |\
|
||||
HRCWL_CE_TO_PLL_1X6 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCISLAVE |
||||
#define CONFIG_SYS_HRCW_HIGH (\ |
||||
HRCWH_PCI_AGENT |\
|
||||
HRCWH_PCI1_ARBITER_DISABLE |\
|
||||
HRCWH_PCICKDRV_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT) |
||||
#else |
||||
#define CONFIG_SYS_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCICKDRV_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT) |
||||
#endif |
||||
|
||||
/*
|
||||
* System IO Config |
||||
*/ |
||||
#define CONFIG_SYS_SICRH 0x00000000 |
||||
#define CONFIG_SYS_SICRL 0x40000000 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
||||
#define CONFIG_BOARD_EARLY_INIT_R |
||||
|
||||
/*
|
||||
* IMMR new address |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xE0000000 |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
/* + 256M */ |
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
||||
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
||||
|
||||
#define CONFIG_SYS_83XX_DDR_USES_CS0 |
||||
|
||||
#define CONFIG_DDR_ECC /* support DDR ECC function */ |
||||
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ |
||||
|
||||
/*
|
||||
* DDRCDR - DDR Control Driver Register |
||||
*/ |
||||
#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
||||
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* Determine DDR configuration from I2C interface. |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ |
||||
#else |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
*/ |
||||
#define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
||||
#if defined(CONFIG_DDR_II) |
||||
#define CONFIG_SYS_DDRCDR 0x80080001 |
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102 |
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00220802 |
||||
#define CONFIG_SYS_DDR_TIMING_1 0x38357322 |
||||
#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 |
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
||||
#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 |
||||
#define CONFIG_SYS_DDR_MODE 0x47d00432 |
||||
#define CONFIG_SYS_DDR_MODE2 0x8000c000 |
||||
#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 |
||||
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
||||
#else |
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
||||
| CSCONFIG_ROW_BIT_13 \
|
||||
| CSCONFIG_COL_BIT_9) |
||||
#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG |
||||
#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ |
||||
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ |
||||
#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ |
||||
#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ |
||||
#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */ |
||||
#endif |
||||
#endif |
||||
|
||||
/*
|
||||
* Memory test |
||||
*/ |
||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00100000 |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
||||
#define CONFIG_SYS_RAMBOOT |
||||
#else |
||||
#undef CONFIG_SYS_RAMBOOT |
||||
#endif |
||||
|
||||
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 |
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
||||
#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
||||
|
||||
/* Window base at flash base */ |
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ |
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD) |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ |
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM |
||||
|
||||
/*
|
||||
* BCSR on the Local Bus |
||||
*/ |
||||
#define CONFIG_SYS_BCSR 0xF8000000 |
||||
/* Access window base at BCSR base */ |
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR |
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) |
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ |
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V) |
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ |
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD) |
||||
/* 0xFFFFE9F7 */ |
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ |
||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
#define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */ |
||||
|
||||
#ifdef CONFIG_SYS_LB_SDRAM |
||||
#define CONFIG_SYS_LBLAWBAR2 0 |
||||
#define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB) |
||||
|
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ |
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* |
||||
* For BR2, need: |
||||
* Base address = BR[0:16] = dynamic |
||||
* port size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861 |
||||
*/ |
||||
|
||||
/* Port size=32bit, MSEL=DRAM */ |
||||
#define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */ |
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
||||
* |
||||
* For OR2, need: |
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100 |
||||
* XAM, OR2[17:18] = 11 |
||||
* 9 columns OR2[19-21] = 010 |
||||
* 13 rows OR2[23-25] = 100 |
||||
* EAD set for extra time OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ |
||||
| OR_SDRAM_XAM \
|
||||
| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
|
||||
| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
|
||||
| OR_SDRAM_EAD) |
||||
/* 0xFC006901 */ |
||||
|
||||
/* LB sdram refresh timer, about 6us */ |
||||
#define CONFIG_SYS_LBC_LSRT 0x32000000 |
||||
/* LB refresh timer prescal, 266MHz/32 */ |
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000 |
||||
|
||||
#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 |
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence. |
||||
*/ |
||||
#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
||||
#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) |
||||
#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) |
||||
#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) |
||||
#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Windows to access Platform I/O Boards (PIB) via local bus |
||||
*/ |
||||
#define CONFIG_SYS_PIB_BASE 0xF8008000 |
||||
#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) |
||||
|
||||
/* [RFC] This LBLAW only covers the 2nd window (CS5) */ |
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM \ |
||||
CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE |
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
||||
|
||||
/*
|
||||
* CS4 on Local Bus, to PIB |
||||
*/ |
||||
/* CS4 base address at 0xf8008000 */ |
||||
#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \ |
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V) |
||||
/* 0xF8008801 */ |
||||
#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \ |
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD) |
||||
/* 0xffffe9f7 */ |
||||
|
||||
/*
|
||||
* CS5 on Local Bus, to PIB |
||||
*/ |
||||
/* CS5 base address at 0xf8010000 */ |
||||
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \ |
||||
CONFIG_SYS_PIB_WINDOW_SIZE) \
|
||||
| BR_PS_8 \
|
||||
| BR_MS_GPCM \
|
||||
| BR_V) |
||||
/* 0xF8010801 */ |
||||
#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \ |
||||
| OR_GPCM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD) |
||||
/* 0xffffe9f7 */ |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_FSL |
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 |
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } |
||||
|
||||
/*
|
||||
* Config on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 |
||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 |
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ |
||||
|
||||
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
||||
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 |
||||
|
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_PCI_INDIRECT_BRIDGE |
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_83XX_PCI_STREAMING |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#define CONFIG_HWCONFIG 1 |
||||
|
||||
/*
|
||||
* QE UEC ethernet configuration |
||||
*/ |
||||
#define CONFIG_UEC_ETH |
||||
#define CONFIG_ETHPRIME "UEC0" |
||||
#define CONFIG_PHY_MODE_NEED_CHANGE |
||||
|
||||
#define CONFIG_UEC_ETH1 /* GETH1 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH1 |
||||
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
||||
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE |
||||
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 |
||||
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH |
||||
#define CONFIG_SYS_UEC1_PHY_ADDR 0 |
||||
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
||||
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
||||
#endif |
||||
|
||||
#define CONFIG_UEC_ETH2 /* GETH2 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH2 |
||||
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
||||
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE |
||||
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 |
||||
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH |
||||
#define CONFIG_SYS_UEC2_PHY_ADDR 1 |
||||
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
||||
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_ADDR \ |
||||
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_SDRAM |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_CMD_PCI |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) |
||||
#undef CONFIG_CMD_SAVEENV |
||||
#undef CONFIG_CMD_LOADS |
||||
#endif |
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 256 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CONFIG_SYS_HID0_INIT 0x000000000 |
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
||||
HID0_ENABLE_INSTRUCTION_CACHE) |
||||
#define CONFIG_SYS_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
||||
#define CONFIG_BAT_RW |
||||
|
||||
/* DDR/LBC SDRAM: cacheable */ |
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
||||
| BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ |
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
||||
|
||||
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ |
||||
| BATU_BL_4M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
||||
|
||||
/* BCSR: cache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ |
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ |
||||
| BATU_BL_128K \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ |
||||
| BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ |
||||
| BATU_BL_32M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ |
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
||||
|
||||
/* DDR/LBC SDRAM next 256M: cacheable */ |
||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \ |
||||
| BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \ |
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
||||
| BATU_BL_128K \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
||||
|
||||
#ifdef CONFIG_PCI |
||||
/* PCI MEM space: cacheable */ |
||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ |
||||
| BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ |
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
||||
/* PCI MMIO space: cache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ |
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ |
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
||||
#else |
||||
#define CONFIG_SYS_IBAT6L (0) |
||||
#define CONFIG_SYS_IBAT6U (0) |
||||
#define CONFIG_SYS_IBAT7L (0) |
||||
#define CONFIG_SYS_IBAT7U (0) |
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_UEC_ETH) |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_HAS_ETH1 |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=ramfs.83xx\0" \
|
||||
"fdtaddr=780000\0" \
|
||||
"fdtfile=mpc836x_mds.dtb\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
||||
"$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -1,620 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* |
||||
* Copyright (C) 2007 Logic Product Development, Inc. |
||||
* Peter Barada <peterb@logicpd.com> |
||||
* |
||||
* Copyright (C) 2007 MontaVista Software, Inc. |
||||
* Anton Vorontsov <avorontsov@ru.mvista.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 family */ |
||||
#define CONFIG_QE 1 /* Has QE */ |
||||
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
||||
#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFF800000 |
||||
|
||||
/*
|
||||
* System Clock Setup |
||||
*/ |
||||
#ifdef CONFIG_CLKIN_33MHZ |
||||
#define CONFIG_83XX_CLKIN 33333333 |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 |
||||
#define CONFIG_PCI_33M 1 |
||||
#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1 |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 66000000 |
||||
#define CONFIG_SYS_CLK_FREQ 66000000 |
||||
#define CONFIG_PCI_66M 1 |
||||
#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1 |
||||
#endif /* CONFIG_CLKIN_33MHZ */ |
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word |
||||
*/ |
||||
#define CONFIG_SYS_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
|
||||
HRCWL_CORE_TO_CSB_2X1 |\
|
||||
HRCWL_CE_TO_PLL_1X15) |
||||
|
||||
#define CONFIG_SYS_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCICKDRV_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_SECONDARY_DDR_DISABLE |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LALE_EARLY) |
||||
|
||||
/*
|
||||
* System IO Config |
||||
*/ |
||||
#define CONFIG_SYS_SICRH 0x00000000 |
||||
#define CONFIG_SYS_SICRL 0x40000000 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R |
||||
|
||||
/*
|
||||
* IMMR new address |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xE0000000 |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
||||
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
||||
|
||||
#define CONFIG_SYS_83XX_DDR_USES_CS0 |
||||
|
||||
#define CONFIG_DDR_ECC /* support DDR ECC function */ |
||||
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ |
||||
|
||||
/*
|
||||
* DDRCDR - DDR Control Driver Register |
||||
*/ |
||||
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ |
||||
| DDRCDR_ODT \
|
||||
| DDRCDR_Q_DRN) |
||||
/* 0x80080001 */ |
||||
|
||||
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ |
||||
|
||||
/*
|
||||
* Manually set up DDR parameters |
||||
*/ |
||||
#define CONFIG_DDR_II |
||||
#define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
||||
| CSCONFIG_ROW_BIT_13 \
|
||||
| CSCONFIG_COL_BIT_10 \
|
||||
| CSCONFIG_ODT_WR_ONLY_CURRENT) |
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
||||
| SDRAM_CFG_ECC_EN) |
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 |
||||
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
||||
#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \ |
||||
| (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) |
||||
#define CONFIG_SYS_DDR_MODE 0x47800432 |
||||
#define CONFIG_SYS_DDR_MODE2 0x8000c000 |
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ |
||||
(9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
|
||||
(3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
|
||||
(3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_WWT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_RRT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_WRT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_RWT_SHIFT)) |
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \ |
||||
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
|
||||
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
|
||||
(3 << TIMING_CFG1_WRREC_SHIFT) | \
|
||||
(10 << TIMING_CFG1_REFREC_SHIFT) | \
|
||||
(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
|
||||
(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
|
||||
(3 << TIMING_CFG1_PRETOACT_SHIFT)) |
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ |
||||
(4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
|
||||
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
|
||||
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
|
||||
(2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
|
||||
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
|
||||
(0 << TIMING_CFG2_CPO_SHIFT)) |
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
||||
|
||||
/*
|
||||
* Memory test |
||||
*/ |
||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00100000 |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
||||
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */ |
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
||||
#define CONFIG_SYS_RAMBOOT |
||||
#else |
||||
#undef CONFIG_SYS_RAMBOOT |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 |
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */ |
||||
|
||||
/* Window base at flash base */ |
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ |
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET \
|
||||
| OR_GPCM_EAD) |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ |
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM |
||||
|
||||
/*
|
||||
* NAND flash on the local bus |
||||
*/ |
||||
#define CONFIG_SYS_NAND_BASE 0x60000000 |
||||
#define CONFIG_CMD_NAND 1 |
||||
#define CONFIG_NAND_FSL_UPM 1 |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
||||
/*
|
||||
* [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB |
||||
* ... What's correct? |
||||
*/ |
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) |
||||
|
||||
/* Port size 8 bit, UPMA */ |
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ |
||||
| BR_PS_8 \
|
||||
| BR_MS_UPMA \
|
||||
| BR_V) |
||||
/* 0x60000881 */ |
||||
#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD) |
||||
/* 0xFC000001 */ |
||||
|
||||
/*
|
||||
* Fujitsu MB86277 (MINT) graphics controller |
||||
*/ |
||||
#define CONFIG_SYS_VIDEO_BASE 0x70000000 |
||||
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE |
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) |
||||
|
||||
/* Port size 32 bit, UPMB */ |
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \ |
||||
| BR_PS_32 \
|
||||
| BR_MS_UPMB \
|
||||
| BR_V) |
||||
/* 0x000018a1 */ |
||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD) |
||||
/* 0xFC000001 */ |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
/* Pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_FSL |
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 |
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CONFIG_PCI |
||||
|
||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 |
||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000 |
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 |
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_PCI_INDIRECT_BRIDGE |
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
/*
|
||||
* QE UEC ethernet configuration |
||||
*/ |
||||
#define CONFIG_UEC_ETH |
||||
#define CONFIG_ETHPRIME "UEC0" |
||||
|
||||
#define CONFIG_UEC_ETH1 /* GETH1 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH1 |
||||
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
||||
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE |
||||
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 |
||||
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH |
||||
#define CONFIG_SYS_UEC1_PHY_ADDR 2 |
||||
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID |
||||
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
||||
#endif |
||||
|
||||
#define CONFIG_UEC_ETH2 /* GETH2 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH2 |
||||
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
||||
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE |
||||
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 |
||||
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH |
||||
#define CONFIG_SYS_UEC2_PHY_ADDR 4 |
||||
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID |
||||
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
||||
#define CONFIG_ENV_SIZE 0x20000 |
||||
#else /* CONFIG_SYS_RAMBOOT */ |
||||
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#endif /* CONFIG_SYS_RAMBOOT */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_CMD_PCI |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) |
||||
#undef CONFIG_CMD_SAVEENV |
||||
#undef CONFIG_CMD_LOADS |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 256 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CONFIG_SYS_HID0_INIT 0x000000000 |
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
||||
HID0_ENABLE_INSTRUCTION_CACHE) |
||||
#define CONFIG_SYS_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
||||
|
||||
/* DDR: cache cacheable */ |
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
||||
| BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ |
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
||||
|
||||
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ |
||||
| BATU_BL_4M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
||||
|
||||
/* NAND: cache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \ |
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \ |
||||
| BATU_BL_64M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ |
||||
| BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ |
||||
| BATU_BL_32M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ |
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \ |
||||
| BATL_PP_RW) |
||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ |
||||
| BATU_BL_128K \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
||||
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \ |
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \ |
||||
| BATU_BL_64M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
||||
|
||||
#ifdef CONFIG_PCI |
||||
/* PCI MEM space: cacheable */ |
||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ |
||||
| BATL_PP_RW \
|
||||
| BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ |
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
||||
/* PCI MMIO space: cache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ |
||||
| BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ |
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP) |
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
||||
#else /* CONFIG_PCI */ |
||||
#define CONFIG_SYS_IBAT6L (0) |
||||
#define CONFIG_SYS_IBAT6U (0) |
||||
#define CONFIG_SYS_IBAT7L (0) |
||||
#define CONFIG_SYS_IBAT7U (0) |
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_UEC_ETH) |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_HAS_ETH2 |
||||
#define CONFIG_HAS_ETH3 |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADADDR a00000 |
||||
#define CONFIG_HOSTNAME mpc8360erdk |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
|
||||
#define CONFIG_ROOTPATH "/nfsroot/" |
||||
|
||||
#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"loadaddr=a00000\0" \
|
||||
"fdtaddr=900000\0" \
|
||||
"fdtfile=mpc836x_rdk.dtb\0" \
|
||||
"fsfile=fs\0" \
|
||||
"ubootfile=u-boot.bin\0" \
|
||||
"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
|
||||
"-(rootfs)\0" \
|
||||
"setbootargs=setenv bootargs console=$consoledev,$baudrate " \
|
||||
"$mtdparts panic=1\0" \
|
||||
"adddhcpargs=setenv bootargs $bootargs ip=on\0" \
|
||||
"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
|
||||
"$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
|
||||
"addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
|
||||
"rootfstype=jffs2 rw\0" \
|
||||
"tftp_get_uboot=tftp 100000 $ubootfile\0" \
|
||||
"tftp_get_kernel=tftp $loadaddr $bootfile\0" \
|
||||
"tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
|
||||
"tftp_get_fs=tftp c00000 $fsfile\0" \
|
||||
"nand_erase_kernel=nand erase 0 400000\0" \
|
||||
"nand_erase_dtb=nand erase 400000 20000\0" \
|
||||
"nand_erase_fs=nand erase 420000 3be0000\0" \
|
||||
"nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
|
||||
"nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
|
||||
"nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
|
||||
"nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
|
||||
"nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
|
||||
"nor_reflash=protect off ff800000 ff87ffff ; " \
|
||||
"erase ff800000 ff87ffff ; " \
|
||||
"cp.b 100000 ff800000 $filesize\0" \
|
||||
"nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
|
||||
"nand_write_kernel\0" \
|
||||
"nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
|
||||
"nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
|
||||
"nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
|
||||
"nand_reflash_fs\0" \
|
||||
"boot_m=bootm $loadaddr - $fdtaddr\0" \
|
||||
"dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
|
||||
"nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
|
||||
"boot_m\0" \
|
||||
"nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
|
||||
"boot_m\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run dhcpboot" |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue