@ -301,7 +301,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE * addr = ( FLASH_WORD_SIZE * ) ( info - > start [ 0 ] ) ;
volatile FLASH_WORD_SIZE * addr2 ;
int flag , prot , sect , l_sect ;
int flag , prot , sect ;
int i ;
if ( ( s_first < 0 ) | | ( s_first > s_last ) ) {
@ -331,8 +331,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
printf ( " \n " ) ;
}
l_sect = - 1 ;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ( ) ;
@ -360,7 +358,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
addr [ ADDR1 ] = ( FLASH_WORD_SIZE ) 0x00550055 ;
addr2 [ 0 ] = ( FLASH_WORD_SIZE ) 0x00300030 ; /* sector erase */
}
l_sect = sect ;
/*
* Wait for each sector to complete , it ' s more
* reliable . According to AMD Spec , you must
@ -379,16 +376,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
/* wait at least 80us - let's wait 1 ms */
udelay ( 1000 ) ;
#if 0
/*
* We wait for the last triggered sector
*/
if ( l_sect < 0 )
goto DONE ;
wait_for_DQ7 ( info , l_sect ) ;
DONE :
# endif
/* reset to read mode */
addr = ( FLASH_WORD_SIZE * ) info - > start [ 0 ] ;
addr [ 0 ] = ( FLASH_WORD_SIZE ) 0x00F000F0 ; /* reset bank */