This patch adds support for the AT91SAM9263 chip and the AT91SAM9263EK board. Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>master
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Stelian Pop <stelian.pop@leadtechdesign.com>
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# Lead Tech Design <www.leadtechdesign.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y += at91sam9263ek.o
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COBJS-y += led.o
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COBJS-y += partition.o
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COBJS-$(CONFIG_CMD_NAND) += nand.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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/*
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* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian.pop@leadtechdesign.com> |
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* Lead Tech Design <www.leadtechdesign.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/at91sam9263.h> |
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#include <asm/arch/at91sam9263_matrix.h> |
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#include <asm/arch/at91sam9_smc.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_rstc.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/io.h> |
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) |
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#include <net.h> |
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#endif |
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DECLARE_GLOBAL_DATA_PTR; |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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static void at91sam9263ek_serial_hw_init(void) |
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{ |
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#ifdef CONFIG_USART0 |
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at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ |
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at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); |
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#endif |
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#ifdef CONFIG_USART1 |
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at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ |
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at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); |
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#endif |
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#ifdef CONFIG_USART2 |
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at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ |
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at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); |
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#endif |
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#ifdef CONFIG_USART3 /* DBGU */ |
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at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ |
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at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); |
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#endif |
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} |
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#ifdef CONFIG_CMD_NAND |
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static void at91sam9263ek_nand_hw_init(void) |
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{ |
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unsigned long csa; |
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/* Enable CS3 */ |
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csa = at91_sys_read(AT91_MATRIX_EBI0CSA); |
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at91_sys_write(AT91_MATRIX_EBI0CSA, |
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csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); |
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/* Configure SMC CS3 for NAND/SmartMedia */ |
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at91_sys_write(AT91_SMC_SETUP(3), |
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AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | |
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); |
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at91_sys_write(AT91_SMC_PULSE(3), |
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); |
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at91_sys_write(AT91_SMC_CYCLE(3), |
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); |
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at91_sys_write(AT91_SMC_MODE(3), |
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE | |
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AT91_SMC_EXNWMODE_DISABLE | |
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#ifdef CFG_NAND_DBW_16 |
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AT91_SMC_DBW_16 | |
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#else /* CFG_NAND_DBW_8 */ |
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AT91_SMC_DBW_8 | |
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#endif |
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AT91_SMC_TDF_(2)); |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | |
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1 << AT91SAM9263_ID_PIOCDE); |
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/* Configure RDY/BSY */ |
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at91_set_gpio_input(AT91_PIN_PA22, 1); |
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/* Enable NandFlash */ |
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at91_set_gpio_output(AT91_PIN_PD15, 1); |
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} |
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#endif |
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#ifdef CONFIG_HAS_DATAFLASH |
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static void at91sam9263ek_spi_hw_init(void) |
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{ |
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at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */ |
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at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ |
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at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ |
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at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ |
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/* Enable clock */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); |
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} |
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#endif |
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#ifdef CONFIG_MACB |
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static void at91sam9263ek_macb_hw_init(void) |
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{ |
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/* Enable clock */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); |
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/*
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* Disable pull-up on: |
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* RXDV (PC25) => PHY normal mode (not Test mode) |
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* ERX0 (PE25) => PHY ADDR0 |
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* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 |
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* |
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* PHY has internal pull-down |
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*/ |
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writel(pin_to_mask(AT91_PIN_PC25), |
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pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); |
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writel(pin_to_mask(AT91_PIN_PE25) | |
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pin_to_mask(AT91_PIN_PE26), |
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pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); |
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/* Need to reset PHY -> 500ms reset */ |
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | |
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AT91_RSTC_ERSTL | (0x0D << 8) | |
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AT91_RSTC_URSTEN); |
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); |
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/* Wait for end hardware reset */ |
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); |
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/* Re-enable pull-up */ |
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writel(pin_to_mask(AT91_PIN_PC25), |
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pin_to_controller(AT91_PIN_PC0) + PIO_PUER); |
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writel(pin_to_mask(AT91_PIN_PE25) | |
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pin_to_mask(AT91_PIN_PE26), |
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pin_to_controller(AT91_PIN_PE0) + PIO_PUER); |
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at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ |
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at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ |
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at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ |
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at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ |
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at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ |
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at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ |
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at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ |
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at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ |
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at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ |
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at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ |
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#ifndef CONFIG_RMII |
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at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ |
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at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ |
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at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ |
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at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ |
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at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ |
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at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ |
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at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ |
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at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ |
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#endif |
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} |
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#endif |
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#ifdef CONFIG_USB_OHCI_NEW |
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static void at91sam9263ek_uhp_hw_init(void) |
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{ |
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/* Enable VBus on UHP ports */ |
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at91_set_gpio_output(AT91_PIN_PA21, 0); |
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at91_set_gpio_output(AT91_PIN_PA24, 0); |
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} |
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#endif |
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int board_init(void) |
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{ |
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/* Enable Ctrlc */ |
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console_init_f(); |
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/* arch number of AT91SAM9263EK-Board */ |
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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at91sam9263ek_serial_hw_init(); |
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#ifdef CONFIG_CMD_NAND |
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at91sam9263ek_nand_hw_init(); |
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#endif |
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#ifdef CONFIG_HAS_DATAFLASH |
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at91sam9263ek_spi_hw_init(); |
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#endif |
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#ifdef CONFIG_MACB |
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at91sam9263ek_macb_hw_init(); |
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#endif |
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#ifdef CONFIG_USB_OHCI_NEW |
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at91sam9263ek_uhp_hw_init(); |
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#endif |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; |
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return 0; |
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} |
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#ifdef CONFIG_RESET_PHY_R |
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void reset_phy(void) |
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{ |
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#ifdef CONFIG_MACB |
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/*
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* Initialize ethernet HW addr prior to starting Linux, |
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* needed for nfsroot |
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*/ |
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eth_init(gd->bd); |
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#endif |
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} |
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#endif |
@ -0,0 +1 @@ |
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TEXT_BASE = 0x23f00000
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@ -0,0 +1,78 @@ |
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/*
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* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian.pop@leadtechdesign.com> |
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* Lead Tech Design <www.leadtechdesign.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/at91sam9263.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/io.h> |
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#define RED_LED AT91_PIN_PB7 /* this is the power led */ |
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#define GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ |
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#define YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */ |
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void red_LED_on(void) |
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{ |
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at91_set_gpio_value(RED_LED, 1); |
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} |
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void red_LED_off(void) |
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{ |
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at91_set_gpio_value(RED_LED, 0); |
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} |
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void green_LED_on(void) |
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{ |
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at91_set_gpio_value(GREEN_LED, 0); |
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} |
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void green_LED_off(void) |
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{ |
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at91_set_gpio_value(GREEN_LED, 1); |
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} |
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void yellow_LED_on(void) |
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{ |
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at91_set_gpio_value(YELLOW_LED, 0); |
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} |
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void yellow_LED_off(void) |
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{ |
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at91_set_gpio_value(YELLOW_LED, 1); |
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} |
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void coloured_LED_init(void) |
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{ |
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/* Enable clock */ |
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | |
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1 << AT91SAM9263_ID_PIOCDE); |
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at91_set_gpio_output(RED_LED, 1); |
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at91_set_gpio_output(GREEN_LED, 1); |
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at91_set_gpio_output(YELLOW_LED, 1); |
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at91_set_gpio_value(RED_LED, 0); |
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at91_set_gpio_value(GREEN_LED, 1); |
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at91_set_gpio_value(YELLOW_LED, 1); |
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} |
@ -0,0 +1,79 @@ |
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/*
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* (C) Copyright 2007-2008 |
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* Stelian Pop <stelian.pop@leadtechdesign.com> |
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* Lead Tech Design <www.leadtechdesign.com> |
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* |
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* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/at91sam9263.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/at91_pio.h> |
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#include <nand.h> |
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/*
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* hardware specific access to control-lines |
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*/ |
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#define MASK_ALE (1 << 21) /* our ALE is AD21 */ |
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#define MASK_CLE (1 << 22) /* our CLE is AD22 */ |
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static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) |
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{ |
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struct nand_chip *this = mtd->priv; |
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
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IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
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switch (cmd) { |
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case NAND_CTL_SETCLE: |
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IO_ADDR_W |= MASK_CLE; |
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break; |
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case NAND_CTL_SETALE: |
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IO_ADDR_W |= MASK_ALE; |
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break; |
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case NAND_CTL_CLRNCE: |
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at91_set_gpio_value(AT91_PIN_PD15, 1); |
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break; |
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case NAND_CTL_SETNCE: |
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at91_set_gpio_value(AT91_PIN_PD15, 0); |
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break; |
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} |
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this->IO_ADDR_W = (void *) IO_ADDR_W; |
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} |
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static int at91sam9263ek_nand_ready(struct mtd_info *mtd) |
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{ |
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return at91_get_gpio_value(AT91_PIN_PA22); |
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} |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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nand->eccmode = NAND_ECC_SOFT; |
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#ifdef CFG_NAND_DBW_16 |
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nand->options = NAND_BUSWIDTH_16; |
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#endif |
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nand->hwcontrol = at91sam9263ek_nand_hwcontrol; |
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nand->dev_ready = at91sam9263ek_nand_ready; |
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nand->chip_delay = 20; |
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return 0; |
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} |
@ -0,0 +1,39 @@ |
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/*
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* (C) Copyright 2008 |
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* Ulf Samuelsson <ulf@atmel.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <asm/hardware.h> |
||||
#include <dataflash.h> |
||||
|
||||
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; |
||||
|
||||
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { |
||||
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ |
||||
}; |
||||
|
||||
/*define the area offsets*/ |
||||
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { |
||||
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, |
||||
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, |
||||
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, |
||||
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, |
||||
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, |
||||
}; |
@ -0,0 +1,127 @@ |
||||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] |
||||
* |
||||
* (C) 2007 Atmel Corporation. |
||||
* |
||||
* Common definitions. |
||||
* Based on AT91SAM9263 datasheet revision B (Preliminary). |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef AT91SAM9263_H |
||||
#define AT91SAM9263_H |
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts. |
||||
*/ |
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
||||
#define AT91_ID_SYS 1 /* System Peripherals */ |
||||
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ |
||||
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ |
||||
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ |
||||
#define AT91SAM9263_ID_US0 7 /* USART 0 */ |
||||
#define AT91SAM9263_ID_US1 8 /* USART 1 */ |
||||
#define AT91SAM9263_ID_US2 9 /* USART 2 */ |
||||
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ |
||||
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ |
||||
#define AT91SAM9263_ID_CAN 12 /* CAN */ |
||||
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ |
||||
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ |
||||
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ |
||||
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ |
||||
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ |
||||
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ |
||||
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ |
||||
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ |
||||
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ |
||||
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ |
||||
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ |
||||
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ |
||||
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ |
||||
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ |
||||
#define AT91SAM9263_ID_UHP 29 /* USB Host port */ |
||||
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ |
||||
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ |
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses. |
||||
*/ |
||||
#define AT91SAM9263_BASE_UDP 0xfff78000 |
||||
#define AT91SAM9263_BASE_TCB0 0xfff7c000 |
||||
#define AT91SAM9263_BASE_TC0 0xfff7c000 |
||||
#define AT91SAM9263_BASE_TC1 0xfff7c040 |
||||
#define AT91SAM9263_BASE_TC2 0xfff7c080 |
||||
#define AT91SAM9263_BASE_MCI0 0xfff80000 |
||||
#define AT91SAM9263_BASE_MCI1 0xfff84000 |
||||
#define AT91SAM9263_BASE_TWI 0xfff88000 |
||||
#define AT91SAM9263_BASE_US0 0xfff8c000 |
||||
#define AT91SAM9263_BASE_US1 0xfff90000 |
||||
#define AT91SAM9263_BASE_US2 0xfff94000 |
||||
#define AT91SAM9263_BASE_SSC0 0xfff98000 |
||||
#define AT91SAM9263_BASE_SSC1 0xfff9c000 |
||||
#define AT91SAM9263_BASE_AC97C 0xfffa0000 |
||||
#define AT91SAM9263_BASE_SPI0 0xfffa4000 |
||||
#define AT91SAM9263_BASE_SPI1 0xfffa8000 |
||||
#define AT91SAM9263_BASE_CAN 0xfffac000 |
||||
#define AT91SAM9263_BASE_PWMC 0xfffb8000 |
||||
#define AT91SAM9263_BASE_EMAC 0xfffbc000 |
||||
#define AT91SAM9263_BASE_ISI 0xfffc4000 |
||||
#define AT91SAM9263_BASE_2DGE 0xfffc8000 |
||||
#define AT91_BASE_SYS 0xffffe000 |
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS) |
||||
*/ |
||||
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) |
||||
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) |
||||
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) |
||||
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) |
||||
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) |
||||
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) |
||||
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) |
||||
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) |
||||
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) |
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) |
||||
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) |
||||
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) |
||||
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) |
||||
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) |
||||
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) |
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) |
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) |
||||
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) |
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) |
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) |
||||
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) |
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
||||
|
||||
#define AT91_USART0 AT91SAM9263_BASE_US0 |
||||
#define AT91_USART1 AT91SAM9263_BASE_US1 |
||||
#define AT91_USART2 AT91SAM9263_BASE_US2 |
||||
|
||||
#define AT91_SMC AT91_SMC0 |
||||
|
||||
/*
|
||||
* Internal Memory. |
||||
*/ |
||||
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ |
||||
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ |
||||
|
||||
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ |
||||
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ |
||||
|
||||
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ |
||||
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ |
||||
|
||||
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ |
||||
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ |
||||
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ |
||||
|
||||
|
||||
#endif |
@ -0,0 +1,129 @@ |
||||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] |
||||
* |
||||
* Copyright (C) 2006 Atmel Corporation. |
||||
* |
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers. |
||||
* Based on AT91SAM9263 datasheet revision B (Preliminary). |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef AT91SAM9263_MATRIX_H |
||||
#define AT91SAM9263_MATRIX_H |
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ |
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ |
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ |
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ |
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ |
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ |
||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ |
||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ |
||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ |
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ |
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0) |
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0) |
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0) |
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0) |
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) |
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ |
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ |
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ |
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ |
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ |
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ |
||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ |
||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ |
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) |
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ |
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ |
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) |
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) |
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ |
||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ |
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ |
||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ |
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ |
||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ |
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ |
||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ |
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ |
||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ |
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ |
||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ |
||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ |
||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ |
||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ |
||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ |
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ |
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ |
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ |
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ |
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ |
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ |
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ |
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ |
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ |
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ |
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
||||
#define AT91_MATRIX_RCB2 (1 << 2) |
||||
#define AT91_MATRIX_RCB3 (1 << 3) |
||||
#define AT91_MATRIX_RCB4 (1 << 4) |
||||
#define AT91_MATRIX_RCB5 (1 << 5) |
||||
#define AT91_MATRIX_RCB6 (1 << 6) |
||||
#define AT91_MATRIX_RCB7 (1 << 7) |
||||
#define AT91_MATRIX_RCB8 (1 << 8) |
||||
|
||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ |
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ |
||||
#define AT91_MATRIX_ITCM_0 (0 << 0) |
||||
#define AT91_MATRIX_ITCM_16 (5 << 0) |
||||
#define AT91_MATRIX_ITCM_32 (6 << 0) |
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ |
||||
#define AT91_MATRIX_DTCM_0 (0 << 4) |
||||
#define AT91_MATRIX_DTCM_16 (5 << 4) |
||||
#define AT91_MATRIX_DTCM_32 (6 << 4) |
||||
|
||||
#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ |
||||
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
||||
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) |
||||
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) |
||||
#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ |
||||
#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) |
||||
#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) |
||||
#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ |
||||
#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) |
||||
#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) |
||||
#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ |
||||
#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) |
||||
#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) |
||||
#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) |
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) |
||||
|
||||
#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ |
||||
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
||||
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) |
||||
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) |
||||
#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ |
||||
#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) |
||||
#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) |
||||
#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) |
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) |
||||
|
||||
#endif |
@ -0,0 +1,195 @@ |
||||
/*
|
||||
* (C) Copyright 2007-2008 |
||||
* Stelian Pop <stelian.pop@leadtechdesign.com> |
||||
* Lead Tech Design <www.leadtechdesign.com> |
||||
* |
||||
* Configuation settings for the AT91SAM9263EK board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* ARM asynchronous clock */ |
||||
#define AT91_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal */ |
||||
#define AT91_MASTER_CLOCK 99959500 /* peripheral = main / 2 */ |
||||
#define CFG_HZ 1000000 /* 1us resolution */ |
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */ |
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ |
||||
#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ |
||||
#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ |
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_SKIP_RELOCATE_UBOOT |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_ATMEL_USART 1 |
||||
#undef CONFIG_USART0 |
||||
#undef CONFIG_USART1 |
||||
#undef CONFIG_USART2 |
||||
#define CONFIG_USART3 1 /* USART 3 is DBGU */ |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
/* #define CONFIG_ENV_OVERWRITE 1 */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1 |
||||
#define CONFIG_BOOTP_BOOTPATH 1 |
||||
#define CONFIG_BOOTP_GATEWAY 1 |
||||
#define CONFIG_BOOTP_HOSTNAME 1 |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#undef CONFIG_CMD_BDI |
||||
#undef CONFIG_CMD_IMI |
||||
#undef CONFIG_CMD_AUTOSCRIPT |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_LOADS |
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#define CONFIG_CMD_PING 1 |
||||
#define CONFIG_CMD_DHCP 1 |
||||
#define CONFIG_CMD_NAND 1 |
||||
#define CONFIG_CMD_USB 1 |
||||
|
||||
/* SDRAM */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM 0x20000000 |
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ |
||||
|
||||
/* DataFlash */ |
||||
#define CONFIG_HAS_DATAFLASH 1 |
||||
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) |
||||
#define CFG_MAX_DATAFLASH_BANKS 1 |
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ |
||||
#define AT91_SPI_CLK 15000000 |
||||
#define DATAFLASH_TCSS (0x1a << 16) |
||||
#define DATAFLASH_TCHS (0x1 << 24) |
||||
|
||||
/* NOR flash, if populated */ |
||||
#if 1 |
||||
#define CFG_NO_FLASH 1 |
||||
#else |
||||
#define CFG_FLASH_CFI 1 |
||||
#define CFG_FLASH_CFI_DRIVER 1 |
||||
#define PHYS_FLASH_1 0x10000000 |
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
#define CFG_MAX_FLASH_SECT 256 |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
#endif |
||||
|
||||
/* NAND flash */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CFG_MAX_NAND_DEVICE 1 |
||||
#define CFG_NAND_BASE 0x40000000 |
||||
#define CFG_NAND_DBW_8 1 |
||||
|
||||
/* Ethernet */ |
||||
#define CONFIG_MACB 1 |
||||
#define CONFIG_RMII 1 |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_NET_RETRY_COUNT 20 |
||||
#define CONFIG_RESET_PHY_R 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_OHCI_NEW 1 |
||||
#define LITTLEENDIAN 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
#define CFG_USB_OHCI_CPU_INIT 1 |
||||
#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ |
||||
#define CFG_USB_OHCI_SLOT_NAME "at91sam9263" |
||||
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 |
||||
#define CONFIG_USB_STORAGE 1 |
||||
|
||||
#define CFG_LOAD_ADDR 0x22000000 /* load address */ |
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM |
||||
#define CFG_MEMTEST_END 0x23e00000 |
||||
|
||||
#define CFG_USE_DATAFLASH 1 |
||||
#undef CFG_USE_NANDFLASH |
||||
|
||||
#ifdef CFG_USE_DATAFLASH |
||||
|
||||
/* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
||||
#define CFG_ENV_IS_IN_DATAFLASH 1 |
||||
#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
||||
#define CFG_ENV_OFFSET 0x4200 |
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) |
||||
#define CFG_ENV_SIZE 0x4200 |
||||
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
||||
"root=/dev/mtdblock0 " \
|
||||
"mtdparts=at91_nand:-(root) "\
|
||||
"rw rootfstype=jffs2" |
||||
|
||||
#else /* CFG_USE_NANDFLASH */ |
||||
|
||||
/* bootstrap + u-boot + env + linux in nandflash */ |
||||
#define CFG_ENV_IS_IN_NAND 1 |
||||
#define CFG_ENV_OFFSET 0x60000 |
||||
#define CFG_ENV_OFFSET_REDUND 0x80000 |
||||
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
||||
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
||||
"root=/dev/mtdblock5 " \
|
||||
"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
|
||||
"rw rootfstype=jffs2" |
||||
|
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
||||
|
||||
#define CFG_PROMPT "U-Boot> " |
||||
#define CFG_CBSIZE 256 |
||||
#define CFG_MAXARGS 16 |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
#define CFG_LONGHELP 1 |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
|
||||
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) |
||||
#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ |
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
#error CONFIG_USE_IRQ not supported |
||||
#endif |
||||
|
||||
#endif |
Loading…
Reference in new issue