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@ -951,6 +951,11 @@ static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2, |
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} |
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} |
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/**
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* rw_mgr_mem_initialize() - Initialize RW Manager |
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* |
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* Initialize RW Manager. |
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*/ |
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static void rw_mgr_mem_initialize(void) |
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{ |
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debug("%s:%d\n", __func__, __LINE__); |
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@ -969,7 +974,7 @@ static void rw_mgr_mem_initialize(void) |
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* significant bits |
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*/ |
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/* start with memory RESET activated */ |
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/* Start with memory RESET activated */ |
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/* tINIT = 200us */ |
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@ -986,7 +991,7 @@ static void rw_mgr_mem_initialize(void) |
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SEQ_TINIT_CNTR2_VAL, |
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RW_MGR_INIT_RESET_0_CKE_0); |
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/* indicate that memory is stable */ |
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/* Indicate that memory is stable. */ |
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writel(1, &phy_mgr_cfg->reset_mem_stbl); |
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/*
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@ -1007,7 +1012,7 @@ static void rw_mgr_mem_initialize(void) |
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SEQ_TRESET_CNTR2_VAL, |
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RW_MGR_INIT_RESET_1_CKE_0); |
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/* bring up clock enable */ |
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/* Bring up clock enable. */ |
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/* tXRP < 250 ck cycles */ |
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delay_for_n_mem_clocks(250); |
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