UniPhier SoCs (except PH1-sLD3) have several nodes in common. Factor out them into uniphier-common32.dtsi. This improves the code maintainability. PH1-sLD3 is so old that it has more or less different register maps than the others. So, it cannot be included in this refactoring. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>master
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/* |
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* Device Tree Source commonly used by UniPhier ARM SoCs |
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* |
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ X11 |
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*/ |
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/include/ "skeleton.dtsi" |
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/ { |
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soc: soc { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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interrupt-parent = <&intc>; |
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extbus: extbus { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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}; |
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serial0: serial@54006800 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006800 0x40>; |
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interrupts = <0 33 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart0>; |
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clocks = <&uart_clk>; |
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}; |
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serial1: serial@54006900 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006900 0x40>; |
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interrupts = <0 35 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart1>; |
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clocks = <&uart_clk>; |
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}; |
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serial2: serial@54006a00 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006a00 0x40>; |
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interrupts = <0 37 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart2>; |
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clocks = <&uart_clk>; |
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}; |
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serial3: serial@54006b00 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006b00 0x40>; |
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interrupts = <0 177 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart3>; |
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clocks = <&uart_clk>; |
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}; |
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system-bus-controller@58c00000 { |
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compatible = "socionext,uniphier-system-bus-controller"; |
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reg = <0x58c00000 0x400>, <0x59800000 0x2000>; |
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}; |
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timer@60000200 { |
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compatible = "arm,cortex-a9-global-timer"; |
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reg = <0x60000200 0x20>; |
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interrupts = <1 11 0x104>; |
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clocks = <&arm_timer_clk>; |
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}; |
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timer@60000600 { |
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compatible = "arm,cortex-a9-twd-timer"; |
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reg = <0x60000600 0x20>; |
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interrupts = <1 13 0x104>; |
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clocks = <&arm_timer_clk>; |
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}; |
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intc: interrupt-controller@60001000 { |
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compatible = "arm,cortex-a9-gic"; |
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reg = <0x60001000 0x1000>, |
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<0x60000100 0x100>; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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}; |
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pinctrl: pinctrl@5f801000 { |
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/* specify compatible in each SoC DTSI */ |
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reg = <0x5f801000 0xe00>; |
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}; |
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nand: nand@68000000 { |
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compatible = "denali,denali-nand-dt"; |
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reg = <0x68000000 0x20>, <0x68100000 0x1000>; |
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reg-names = "nand_data", "denali_reg"; |
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}; |
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}; |
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}; |
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/include/ "uniphier-pinctrl.dtsi" |
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