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MIPS: add support for Broadcom MIPS BCM6362 SoC family

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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
master
Álvaro Fernández Rojas 7 years ago committed by Daniel Schwierzeck
parent 1b075ba016
commit 8f240a3b45
6 changed files with 309 additions and 0 deletions
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  1. 186
      arch/mips/dts/brcm,bcm6362.dtsi
  2. 12
      arch/mips/mach-bmips/Kconfig
  3. 25
      include/configs/bmips_bcm6362.h
  4. 33
      include/dt-bindings/clock/bcm6362-clock.h
  5. 25
      include/dt-bindings/power-domain/bcm6362-power-domain.h
  6. 28
      include/dt-bindings/reset/bcm6362-reset.h

186
arch/mips/dts/brcm,bcm6362.dtsi
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@ -0,0 +1,186 @@
/*
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <dt-bindings/clock/bcm6362-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power-domain/bcm6362-power-domain.h>
#include <dt-bindings/reset/bcm6362-reset.h>
#include "skeleton.dtsi"
/ {
compatible = "brcm,bcm6362";
aliases {
spi0 = &lsspi;
spi1 = &hsspi;
};
cpus {
reg = <0x10000000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
cpu@0 {
compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
u-boot,dm-pre-reloc;
};
cpu@1 {
compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
u-boot,dm-pre-reloc;
};
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
u-boot,dm-pre-reloc;
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133333333>;
};
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
u-boot,dm-pre-reloc;
};
periph_clk: periph-clk {
compatible = "brcm,bcm6345-clk";
reg = <0x10000004 0x4>;
#clock-cells = <1>;
};
};
ubus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
u-boot,dm-pre-reloc;
pll_cntl: syscon@10000008 {
compatible = "syscon";
reg = <0x10000008 0x4>;
};
syscon-reboot {
compatible = "syscon-reboot";
regmap = <&pll_cntl>;
offset = <0x0>;
mask = <0x1>;
};
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
reg = <0x10000010 0x4>;
#reset-cells = <1>;
};
wdt: watchdog@1000005c {
compatible = "brcm,bcm6345-wdt";
reg = <0x1000005c 0xc>;
clocks = <&periph_osc>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt>;
};
gpio1: gpio-controller@10000080 {
compatible = "brcm,bcm6345-gpio";
reg = <0x10000080 0x4>, <0x10000088 0x4>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
status = "disabled";
};
gpio0: gpio-controller@10000084 {
compatible = "brcm,bcm6345-gpio";
reg = <0x10000084 0x4>, <0x1000008c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
uart0: serial@10000100 {
compatible = "brcm,bcm6345-uart";
reg = <0x10000100 0x18>;
clocks = <&periph_osc>;
status = "disabled";
};
uart1: serial@10000120 {
compatible = "brcm,bcm6345-uart";
reg = <0x10000120 0x18>;
clocks = <&periph_osc>;
status = "disabled";
};
lsspi: spi@10000800 {
compatible = "brcm,bcm6358-spi";
reg = <0x10000800 0x70c>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&periph_clk BCM6362_CLK_SPI>;
resets = <&periph_rst BCM6362_RST_SPI>;
spi-max-frequency = <20000000>;
num-cs = <8>;
status = "disabled";
};
hsspi: spi@10001000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10001000 0x600>;
clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
resets = <&periph_rst BCM6362_RST_SPI>;
spi-max-frequency = <50000000>;
num-cs = <8>;
status = "disabled";
};
leds: led-controller@10001900 {
compatible = "brcm,bcm6328-leds";
reg = <0x10001900 0x24>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
periph_pwr: power-controller@10001848 {
compatible = "brcm,bcm6328-power-domain";
reg = <0x10001848 0x4>;
#power-domain-cells = <1>;
};
memory-controller@10003000 {
compatible = "brcm,bcm6328-mc";
reg = <0x10003000 0x864>;
u-boot,dm-pre-reloc;
};
};
};

12
arch/mips/mach-bmips/Kconfig
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@ -12,6 +12,7 @@ config SYS_SOC
default "bcm6348" if SOC_BMIPS_BCM6348
default "bcm6358" if SOC_BMIPS_BCM6358
default "bcm6368" if SOC_BMIPS_BCM6368
default "bcm6362" if SOC_BMIPS_BCM6362
default "bcm63268" if SOC_BMIPS_BCM63268
choice
@ -94,6 +95,17 @@ config SOC_BMIPS_BCM6368
help
This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
config SOC_BMIPS_BCM6362
bool "BMIPS BCM6362 family"
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select MIPS_TUNE_4KC
select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
This supports BMIPS BCM6362 family including BCM6361 and BCM6362.
config SOC_BMIPS_BCM63268
bool "BMIPS BCM63268 family"
select SUPPORTS_BIG_ENDIAN

25
include/configs/bmips_bcm6362.h
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/*
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_BMIPS_BCM6362_H
#define __CONFIG_BMIPS_BCM6362_H
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
#endif
#endif /* __CONFIG_BMIPS_BCM6362_H */

33
include/dt-bindings/clock/bcm6362-clock.h
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@ -0,0 +1,33 @@
/*
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_CLOCK_BCM6362_H
#define __DT_BINDINGS_CLOCK_BCM6362_H
#define BCM6362_CLK_GLESS 0
#define BCM6362_CLK_ADSL_QPROC 1
#define BCM6362_CLK_ADSL_AFE 2
#define BCM6362_CLK_ADSL 3
#define BCM6362_CLK_MIPS 4
#define BCM6362_CLK_WLAN_OCP 5
#define BCM6362_CLK_SWPKT_USB 7
#define BCM6362_CLK_SWPKT_SAR 8
#define BCM6362_CLK_SAR 9
#define BCM6362_CLK_ROBOSW 10
#define BCM6362_CLK_PCM 11
#define BCM6362_CLK_USBD 12
#define BCM6362_CLK_USBH 13
#define BCM6362_CLK_IPSEC 14
#define BCM6362_CLK_SPI 15
#define BCM6362_CLK_HSSPI 16
#define BCM6362_CLK_PCIE 17
#define BCM6362_CLK_FAP 18
#define BCM6362_CLK_PHYMIPS 19
#define BCM6362_CLK_NAND 20
#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */

25
include/dt-bindings/power-domain/bcm6362-power-domain.h
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/*
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
#define BCM6362_PWR_SAR 0
#define BCM6362_PWR_IPSEC 1
#define BCM6362_PWR_MIPS 2
#define BCM6362_PWR_DECT 3
#define BCM6362_PWR_USBH 4
#define BCM6362_PWR_USBD 5
#define BCM6362_PWR_ROBOSW 6
#define BCM6362_PWR_PCM 7
#define BCM6362_PWR_PERIPH 8
#define BCM6362_PWR_ADSL_PHY 9
#define BCM6362_PWR_GMII_PADS 10
#define BCM6362_PWR_FAP 11
#define BCM6362_PWR_PCIE 12
#define BCM6362_PWR_WLAN_PADS 13
#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */

28
include/dt-bindings/reset/bcm6362-reset.h
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@ -0,0 +1,28 @@
/*
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_RESET_BCM6362_H
#define __DT_BINDINGS_RESET_BCM6362_H
#define BCM6362_RST_SPI 0
#define BCM6362_RST_IPSEC 1
#define BCM6362_RST_EPHY 2
#define BCM6362_RST_SAR 3
#define BCM6362_RST_ENETSW 4
#define BCM6362_RST_USBD 5
#define BCM6362_RST_USBH 6
#define BCM6362_RST_PCM 7
#define BCM6362_RST_PCIE_CORE 8
#define BCM6362_RST_PCIE 9
#define BCM6362_RST_PCIE_EXT 10
#define BCM6362_RST_WLAN_SHIM 11
#define BCM6362_RST_DDR_PHY 12
#define BCM6362_RST_FAP 13
#define BCM6362_RST_WLAN_UBUS 14
#endif /* __DT_BINDINGS_RESET_BCM6362_H */
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