armv8: mmu: fix page table mapping

To page mapping the lowest 2 bits needs to be 0x3.
If not fix this, the final lowest 3 bits for page mapping is 0x1
which is marked as reserved.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

arch/arm/cpu/armv8/cache_v8.c

@@ -230,7 +230,10 @@ static void add_map(struct mm_region *map)
 				/* Page fits, create block PTE */
 				debug("Setting PTE %p to block virt=%llx\n",
 				      pte, virt);
-				*pte = phys | attrs;
+				if (level == 3)
+					*pte = phys | attrs | PTE_TYPE_PAGE;
+				else
+					*pte = phys | attrs;
 				virt += blocksize;
 				phys += blocksize;
 				size -= blocksize;

arch/arm/include/asm/armv8/mmu.h

@@ -43,6 +43,7 @@
 #define PTE_TYPE_MASK		(3 << 0)
 #define PTE_TYPE_FAULT		(0 << 0)
 #define PTE_TYPE_TABLE		(3 << 0)
+#define PTE_TYPE_PAGE		(3 << 0)
 #define PTE_TYPE_BLOCK		(1 << 0)
 #define PTE_TYPE_VALID		(1 << 0)