Tom Rini
6 years ago
commit
904e546970
@ -0,0 +1,167 @@ |
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/* |
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* Copyright (C) 2015 Altera Corporation <www.altera.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi" |
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|
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/ { |
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model = "Altera SOCFPGA Arria 10"; |
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compatible = "altr,socfpga-arria10", "altr,socfpga"; |
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|
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aliases { |
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ethernet0 = &gmac0; |
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serial0 = &uart1; |
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}; |
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|
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chosen { |
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bootargs = "earlyprintk"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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memory@0 { |
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name = "memory"; |
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device_type = "memory"; |
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reg = <0x0 0x40000000>; /* 1GB */ |
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}; |
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|
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a10leds { |
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compatible = "gpio-leds"; |
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|
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a10sr_led0 { |
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label = "a10sr-led0"; |
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gpios = <&a10sr_gpio 0 1>; |
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}; |
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|
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a10sr_led1 { |
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label = "a10sr-led1"; |
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gpios = <&a10sr_gpio 1 1>; |
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}; |
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|
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a10sr_led2 { |
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label = "a10sr-led2"; |
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gpios = <&a10sr_gpio 2 1>; |
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}; |
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|
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a10sr_led3 { |
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label = "a10sr-led3"; |
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gpios = <&a10sr_gpio 3 1>; |
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}; |
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}; |
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|
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soc { |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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|
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&gmac0 { |
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phy-mode = "rgmii"; |
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phy-addr = <0xffffffff>; /* probe for phy addr */ |
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|
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/* |
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* These skews assume the user's FPGA design is adding 600ps of delay |
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* for TX_CLK on Arria 10. |
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* |
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* All skews are offset since hardware skew values for the ksz9031 |
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* range from a negative skew to a positive skew. |
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* See the micrel-ksz90x1.txt Documentation file for details. |
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*/ |
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txd0-skew-ps = <0>; /* -420ps */ |
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txd1-skew-ps = <0>; /* -420ps */ |
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txd2-skew-ps = <0>; /* -420ps */ |
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txd3-skew-ps = <0>; /* -420ps */ |
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rxd0-skew-ps = <420>; /* 0ps */ |
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rxd1-skew-ps = <420>; /* 0ps */ |
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rxd2-skew-ps = <420>; /* 0ps */ |
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rxd3-skew-ps = <420>; /* 0ps */ |
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txen-skew-ps = <0>; /* -420ps */ |
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txc-skew-ps = <1860>; /* 960ps */ |
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rxdv-skew-ps = <420>; /* 0ps */ |
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rxc-skew-ps = <1680>; /* 780ps */ |
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max-frame-size = <3800>; |
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status = "okay"; |
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}; |
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|
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&gpio1 { |
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status = "okay"; |
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}; |
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|
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&spi1 { |
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status = "okay"; |
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|
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resource-manager@0 { |
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compatible = "altr,a10sr"; |
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reg = <0>; |
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spi-max-frequency = <100000>; |
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/* low-level active IRQ at GPIO1_5 */ |
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interrupt-parent = <&portb>; |
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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a10sr_gpio: gpio-controller { |
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compatible = "altr,a10sr-gpio"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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a10sr_rst: reset-controller { |
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compatible = "altr,a10sr-reset"; |
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#reset-cells = <1>; |
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}; |
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}; |
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}; |
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&i2c1 { |
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status = "okay"; |
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/* |
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* adjust the falling times to decrease the i2c frequency to 50Khz |
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* because the LCD module does not work at the standard 100Khz |
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*/ |
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clock-frequency = <100000>; |
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i2c-sda-falling-time-ns = <6000>; |
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i2c-scl-falling-time-ns = <6000>; |
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eeprom@51 { |
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compatible = "atmel,24c32"; |
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reg = <0x51>; |
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pagesize = <32>; |
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}; |
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rtc@68 { |
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compatible = "dallas,ds1339"; |
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reg = <0x68>; |
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}; |
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ltc@5c { |
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compatible = "ltc2977"; |
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reg = <0x5c>; |
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}; |
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}; |
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&uart1 { |
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clock-frequency = <50000000>; |
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u-boot,dm-pre-reloc; |
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status = "okay"; |
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}; |
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|
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&usb0 { |
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status = "okay"; |
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disable-over-current; |
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}; |
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|
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&watchdog1 { |
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status = "okay"; |
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}; |
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@ -0,0 +1,380 @@ |
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// SPDX-License-Identifier: GPL-2.0
|
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
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* |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock_manager.h> |
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#include <asm/arch/handoff_s10.h> |
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#include <asm/arch/system_manager.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static const struct socfpga_clock_manager *clock_manager_base = |
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(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; |
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static const struct socfpga_system_manager *sysmgr_regs = |
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
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|
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/*
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* function to write the bypass register which requires a poll of the |
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* busy bit |
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*/ |
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static void cm_write_bypass_mainpll(u32 val) |
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{ |
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writel(val, &clock_manager_base->main_pll.bypass); |
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cm_wait_for_fsm(); |
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} |
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static void cm_write_bypass_perpll(u32 val) |
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{ |
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writel(val, &clock_manager_base->per_pll.bypass); |
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cm_wait_for_fsm(); |
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} |
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|
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/* function to write the ctrl register which requires a poll of the busy bit */ |
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static void cm_write_ctrl(u32 val) |
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{ |
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writel(val, &clock_manager_base->ctrl); |
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cm_wait_for_fsm(); |
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} |
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|
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/*
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* Setup clocks while making no assumptions about previous state of the clocks. |
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*/ |
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void cm_basic_init(const struct cm_config * const cfg) |
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{ |
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u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib; |
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if (cfg == 0) |
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return; |
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|
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/* Put all plls in bypass */ |
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cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL); |
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cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL); |
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|
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/* setup main PLL dividers where calculate the vcocalib value */ |
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mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & |
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CLKMGR_FDBCK_MDIV_MASK; |
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refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & |
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CLKMGR_PLLGLOB_REFCLKDIV_MASK; |
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mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; |
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hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - |
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CLKMGR_HSCNT_CONST; |
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vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | |
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((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << |
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CLKMGR_VCOCALIB_MSCNT_OFFSET); |
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writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & |
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~CLKMGR_PLLGLOB_RST_MASK), |
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&clock_manager_base->main_pll.pllglob); |
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writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck); |
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writel(vcocalib, &clock_manager_base->main_pll.vcocalib); |
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writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); |
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writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); |
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writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv); |
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|
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/* setup peripheral PLL dividers */ |
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/* calculate the vcocalib value */ |
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mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & |
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CLKMGR_FDBCK_MDIV_MASK; |
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refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & |
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CLKMGR_PLLGLOB_REFCLKDIV_MASK; |
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mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; |
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hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - |
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CLKMGR_HSCNT_CONST; |
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vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | |
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((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << |
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CLKMGR_VCOCALIB_MSCNT_OFFSET); |
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writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & |
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~CLKMGR_PLLGLOB_RST_MASK), |
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&clock_manager_base->per_pll.pllglob); |
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writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck); |
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writel(vcocalib, &clock_manager_base->per_pll.vcocalib); |
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writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0); |
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writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); |
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writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl); |
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writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv); |
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/* Take both PLL out of reset and power up */ |
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setbits_le32(&clock_manager_base->main_pll.pllglob, |
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); |
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setbits_le32(&clock_manager_base->per_pll.pllglob, |
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); |
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#define LOCKED_MASK \ |
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(CLKMGR_STAT_MAINPLL_LOCKED | \
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CLKMGR_STAT_PERPLL_LOCKED) |
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cm_wait_for_lock(LOCKED_MASK); |
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/*
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* Dividers for C2 to C9 only init after PLLs are lock. As dividers |
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* only take effect upon value change, we shall set a maximum value as |
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* default value. |
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*/ |
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writel(0xff, &clock_manager_base->main_pll.mpuclk); |
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writel(0xff, &clock_manager_base->main_pll.nocclk); |
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writel(0xff, &clock_manager_base->main_pll.cntr2clk); |
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writel(0xff, &clock_manager_base->main_pll.cntr3clk); |
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writel(0xff, &clock_manager_base->main_pll.cntr4clk); |
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writel(0xff, &clock_manager_base->main_pll.cntr5clk); |
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writel(0xff, &clock_manager_base->main_pll.cntr6clk); |
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writel(0xff, &clock_manager_base->main_pll.cntr7clk); |
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writel(0xff, &clock_manager_base->main_pll.cntr8clk); |
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writel(0xff, &clock_manager_base->main_pll.cntr9clk); |
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writel(0xff, &clock_manager_base->per_pll.cntr2clk); |
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writel(0xff, &clock_manager_base->per_pll.cntr3clk); |
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writel(0xff, &clock_manager_base->per_pll.cntr4clk); |
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writel(0xff, &clock_manager_base->per_pll.cntr5clk); |
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writel(0xff, &clock_manager_base->per_pll.cntr6clk); |
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writel(0xff, &clock_manager_base->per_pll.cntr7clk); |
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writel(0xff, &clock_manager_base->per_pll.cntr8clk); |
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writel(0xff, &clock_manager_base->per_pll.cntr9clk); |
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writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk); |
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writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk); |
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writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk); |
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writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk); |
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writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk); |
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writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk); |
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writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk); |
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writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk); |
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writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk); |
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writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk); |
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writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk); |
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writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk); |
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writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk); |
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writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk); |
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writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk); |
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writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk); |
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writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk); |
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writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk); |
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|
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/* Take all PLLs out of bypass */ |
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cm_write_bypass_mainpll(0); |
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cm_write_bypass_perpll(0); |
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/* clear safe mode / out of boot mode */ |
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cm_write_ctrl(readl(&clock_manager_base->ctrl) |
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& ~(CLKMGR_CTRL_SAFEMODE)); |
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|
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/* Now ungate non-hw-managed clocks */ |
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writel(~0, &clock_manager_base->main_pll.en); |
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writel(~0, &clock_manager_base->per_pll.en); |
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|
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/* Clear the loss of lock bits (write 1 to clear) */ |
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writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK, |
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&clock_manager_base->intrclr); |
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} |
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static unsigned long cm_get_main_vco_clk_hz(void) |
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{ |
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unsigned long fref, refdiv, mdiv, reg, vco; |
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reg = readl(&clock_manager_base->main_pll.pllglob); |
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fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & |
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CLKMGR_PLLGLOB_VCO_PSRC_MASK; |
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switch (fref) { |
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case CLKMGR_VCO_PSRC_EOSC1: |
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fref = cm_get_osc_clk_hz(); |
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break; |
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case CLKMGR_VCO_PSRC_INTOSC: |
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fref = cm_get_intosc_clk_hz(); |
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break; |
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case CLKMGR_VCO_PSRC_F2S: |
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fref = cm_get_fpga_clk_hz(); |
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break; |
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} |
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|
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refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & |
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CLKMGR_PLLGLOB_REFCLKDIV_MASK; |
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|
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reg = readl(&clock_manager_base->main_pll.fdbck); |
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mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; |
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|
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vco = fref / refdiv; |
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vco = vco * (CLKMGR_MDIV_CONST + mdiv); |
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return vco; |
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} |
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static unsigned long cm_get_per_vco_clk_hz(void) |
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{ |
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unsigned long fref, refdiv, mdiv, reg, vco; |
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|
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reg = readl(&clock_manager_base->per_pll.pllglob); |
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fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & |
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CLKMGR_PLLGLOB_VCO_PSRC_MASK; |
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switch (fref) { |
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case CLKMGR_VCO_PSRC_EOSC1: |
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fref = cm_get_osc_clk_hz(); |
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break; |
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case CLKMGR_VCO_PSRC_INTOSC: |
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fref = cm_get_intosc_clk_hz(); |
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break; |
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case CLKMGR_VCO_PSRC_F2S: |
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fref = cm_get_fpga_clk_hz(); |
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break; |
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} |
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|
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refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & |
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CLKMGR_PLLGLOB_REFCLKDIV_MASK; |
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|
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reg = readl(&clock_manager_base->per_pll.fdbck); |
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mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; |
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|
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vco = fref / refdiv; |
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vco = vco * (CLKMGR_MDIV_CONST + mdiv); |
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return vco; |
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} |
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|
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unsigned long cm_get_mpu_clk_hz(void) |
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{ |
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unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk); |
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|
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clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; |
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|
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switch (clock) { |
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case CLKMGR_CLKSRC_MAIN: |
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clock = cm_get_main_vco_clk_hz(); |
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clock /= (readl(&clock_manager_base->main_pll.pllc0) & |
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CLKMGR_PLLC0_DIV_MASK); |
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break; |
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|
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case CLKMGR_CLKSRC_PER: |
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clock = cm_get_per_vco_clk_hz(); |
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clock /= (readl(&clock_manager_base->per_pll.pllc0) & |
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CLKMGR_CLKCNT_MSK); |
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break; |
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|
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case CLKMGR_CLKSRC_OSC1: |
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clock = cm_get_osc_clk_hz(); |
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break; |
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|
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case CLKMGR_CLKSRC_INTOSC: |
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clock = cm_get_intosc_clk_hz(); |
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break; |
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|
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case CLKMGR_CLKSRC_FPGA: |
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clock = cm_get_fpga_clk_hz(); |
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break; |
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} |
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|
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clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) & |
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CLKMGR_CLKCNT_MSK); |
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return clock; |
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} |
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|
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unsigned int cm_get_l3_main_clk_hz(void) |
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{ |
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u32 clock = readl(&clock_manager_base->main_pll.nocclk); |
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|
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clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; |
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|
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switch (clock) { |
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case CLKMGR_CLKSRC_MAIN: |
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clock = cm_get_main_vco_clk_hz(); |
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clock /= (readl(&clock_manager_base->main_pll.pllc1) & |
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CLKMGR_PLLC0_DIV_MASK); |
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break; |
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|
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case CLKMGR_CLKSRC_PER: |
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clock = cm_get_per_vco_clk_hz(); |
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clock /= (readl(&clock_manager_base->per_pll.pllc1) & |
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CLKMGR_CLKCNT_MSK); |
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break; |
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|
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case CLKMGR_CLKSRC_OSC1: |
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clock = cm_get_osc_clk_hz(); |
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break; |
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|
||||
case CLKMGR_CLKSRC_INTOSC: |
||||
clock = cm_get_intosc_clk_hz(); |
||||
break; |
||||
|
||||
case CLKMGR_CLKSRC_FPGA: |
||||
clock = cm_get_fpga_clk_hz(); |
||||
break; |
||||
} |
||||
|
||||
clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) & |
||||
CLKMGR_CLKCNT_MSK); |
||||
return clock; |
||||
} |
||||
|
||||
unsigned int cm_get_mmc_controller_clk_hz(void) |
||||
{ |
||||
u32 clock = readl(&clock_manager_base->per_pll.cntr6clk); |
||||
|
||||
clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; |
||||
|
||||
switch (clock) { |
||||
case CLKMGR_CLKSRC_MAIN: |
||||
clock = cm_get_l3_main_clk_hz(); |
||||
clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) & |
||||
CLKMGR_CLKCNT_MSK); |
||||
break; |
||||
|
||||
case CLKMGR_CLKSRC_PER: |
||||
clock = cm_get_l3_main_clk_hz(); |
||||
clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) & |
||||
CLKMGR_CLKCNT_MSK); |
||||
break; |
||||
|
||||
case CLKMGR_CLKSRC_OSC1: |
||||
clock = cm_get_osc_clk_hz(); |
||||
break; |
||||
|
||||
case CLKMGR_CLKSRC_INTOSC: |
||||
clock = cm_get_intosc_clk_hz(); |
||||
break; |
||||
|
||||
case CLKMGR_CLKSRC_FPGA: |
||||
clock = cm_get_fpga_clk_hz(); |
||||
break; |
||||
} |
||||
return clock / 4; |
||||
} |
||||
|
||||
unsigned int cm_get_l4_sp_clk_hz(void) |
||||
{ |
||||
u32 clock = cm_get_l3_main_clk_hz(); |
||||
|
||||
clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >> |
||||
CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK)); |
||||
return clock; |
||||
} |
||||
|
||||
unsigned int cm_get_qspi_controller_clk_hz(void) |
||||
{ |
||||
return readl(&sysmgr_regs->boot_scratch_cold0); |
||||
} |
||||
|
||||
unsigned int cm_get_spi_controller_clk_hz(void) |
||||
{ |
||||
u32 clock = cm_get_l3_main_clk_hz(); |
||||
|
||||
clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >> |
||||
CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK)); |
||||
return clock; |
||||
} |
||||
|
||||
unsigned int cm_get_l4_sys_free_clk_hz(void) |
||||
{ |
||||
return cm_get_l3_main_clk_hz() / 4; |
||||
} |
||||
|
||||
void cm_print_clock_quick_summary(void) |
||||
{ |
||||
printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000)); |
||||
printf("L3 main %d kHz\n", cm_get_l3_main_clk_hz() / 1000); |
||||
printf("Main VCO %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000)); |
||||
printf("Per VCO %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000)); |
||||
printf("EOSC1 %d kHz\n", cm_get_osc_clk_hz() / 1000); |
||||
printf("HPS MMC %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); |
||||
printf("UART %d kHz\n", cm_get_l4_sp_clk_hz() / 1000); |
||||
} |
||||
@ -0,0 +1,210 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
* |
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _CLOCK_MANAGER_S10_ |
||||
#define _CLOCK_MANAGER_S10_ |
||||
|
||||
/* Clock speed accessors */ |
||||
unsigned long cm_get_mpu_clk_hz(void); |
||||
unsigned long cm_get_sdram_clk_hz(void); |
||||
unsigned int cm_get_l4_sp_clk_hz(void); |
||||
unsigned int cm_get_mmc_controller_clk_hz(void); |
||||
unsigned int cm_get_qspi_controller_clk_hz(void); |
||||
unsigned int cm_get_spi_controller_clk_hz(void); |
||||
const unsigned int cm_get_osc_clk_hz(void); |
||||
const unsigned int cm_get_f2s_per_ref_clk_hz(void); |
||||
const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); |
||||
const unsigned int cm_get_intosc_clk_hz(void); |
||||
const unsigned int cm_get_fpga_clk_hz(void); |
||||
|
||||
#define CLKMGR_EOSC1_HZ 25000000 |
||||
#define CLKMGR_INTOSC_HZ 460000000 |
||||
#define CLKMGR_FPGA_CLK_HZ 50000000 |
||||
|
||||
/* Clock configuration accessors */ |
||||
const struct cm_config * const cm_get_default_config(void); |
||||
|
||||
struct cm_config { |
||||
/* main group */ |
||||
u32 main_pll_mpuclk; |
||||
u32 main_pll_nocclk; |
||||
u32 main_pll_cntr2clk; |
||||
u32 main_pll_cntr3clk; |
||||
u32 main_pll_cntr4clk; |
||||
u32 main_pll_cntr5clk; |
||||
u32 main_pll_cntr6clk; |
||||
u32 main_pll_cntr7clk; |
||||
u32 main_pll_cntr8clk; |
||||
u32 main_pll_cntr9clk; |
||||
u32 main_pll_nocdiv; |
||||
u32 main_pll_pllglob; |
||||
u32 main_pll_fdbck; |
||||
u32 main_pll_pllc0; |
||||
u32 main_pll_pllc1; |
||||
u32 spare; |
||||
|
||||
/* peripheral group */ |
||||
u32 per_pll_cntr2clk; |
||||
u32 per_pll_cntr3clk; |
||||
u32 per_pll_cntr4clk; |
||||
u32 per_pll_cntr5clk; |
||||
u32 per_pll_cntr6clk; |
||||
u32 per_pll_cntr7clk; |
||||
u32 per_pll_cntr8clk; |
||||
u32 per_pll_cntr9clk; |
||||
u32 per_pll_emacctl; |
||||
u32 per_pll_gpiodiv; |
||||
u32 per_pll_pllglob; |
||||
u32 per_pll_fdbck; |
||||
u32 per_pll_pllc0; |
||||
u32 per_pll_pllc1; |
||||
|
||||
/* incoming clock */ |
||||
u32 hps_osc_clk_hz; |
||||
u32 fpga_clk_hz; |
||||
}; |
||||
|
||||
void cm_basic_init(const struct cm_config * const cfg); |
||||
|
||||
struct socfpga_clock_manager_main_pll { |
||||
u32 en; |
||||
u32 ens; |
||||
u32 enr; |
||||
u32 bypass; |
||||
u32 bypasss; |
||||
u32 bypassr; |
||||
u32 mpuclk; |
||||
u32 nocclk; |
||||
u32 cntr2clk; |
||||
u32 cntr3clk; |
||||
u32 cntr4clk; |
||||
u32 cntr5clk; |
||||
u32 cntr6clk; |
||||
u32 cntr7clk; |
||||
u32 cntr8clk; |
||||
u32 cntr9clk; |
||||
u32 nocdiv; |
||||
u32 pllglob; |
||||
u32 fdbck; |
||||
u32 mem; |
||||
u32 memstat; |
||||
u32 pllc0; |
||||
u32 pllc1; |
||||
u32 vcocalib; |
||||
u32 _pad_0x90_0xA0[5]; |
||||
}; |
||||
|
||||
struct socfpga_clock_manager_per_pll { |
||||
u32 en; |
||||
u32 ens; |
||||
u32 enr; |
||||
u32 bypass; |
||||
u32 bypasss; |
||||
u32 bypassr; |
||||
u32 cntr2clk; |
||||
u32 cntr3clk; |
||||
u32 cntr4clk; |
||||
u32 cntr5clk; |
||||
u32 cntr6clk; |
||||
u32 cntr7clk; |
||||
u32 cntr8clk; |
||||
u32 cntr9clk; |
||||
u32 emacctl; |
||||
u32 gpiodiv; |
||||
u32 pllglob; |
||||
u32 fdbck; |
||||
u32 mem; |
||||
u32 memstat; |
||||
u32 pllc0; |
||||
u32 pllc1; |
||||
u32 vcocalib; |
||||
u32 _pad_0x100_0x124[10]; |
||||
}; |
||||
|
||||
struct socfpga_clock_manager { |
||||
u32 ctrl; |
||||
u32 stat; |
||||
u32 testioctrl; |
||||
u32 intrgen; |
||||
u32 intrmsk; |
||||
u32 intrclr; |
||||
u32 intrsts; |
||||
u32 intrstk; |
||||
u32 intrraw; |
||||
u32 _pad_0x24_0x2c[3]; |
||||
struct socfpga_clock_manager_main_pll main_pll; |
||||
struct socfpga_clock_manager_per_pll per_pll; |
||||
}; |
||||
|
||||
#define CLKMGR_CTRL_SAFEMODE BIT(0) |
||||
#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007 |
||||
#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f |
||||
|
||||
#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001 |
||||
#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002 |
||||
#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004 |
||||
#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008 |
||||
#define CLKMGR_STAT_BUSY BIT(0) |
||||
#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) |
||||
#define CLKMGR_STAT_PERPLL_LOCKED BIT(9) |
||||
|
||||
#define CLKMGR_PLLGLOB_PD_MASK 0x00000001 |
||||
#define CLKMGR_PLLGLOB_RST_MASK 0x00000002 |
||||
#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3 |
||||
#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 |
||||
#define CLKMGR_VCO_PSRC_EOSC1 0 |
||||
#define CLKMGR_VCO_PSRC_INTOSC 1 |
||||
#define CLKMGR_VCO_PSRC_F2S 2 |
||||
#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f |
||||
#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 |
||||
|
||||
#define CLKMGR_CLKSRC_MASK 0x7 |
||||
#define CLKMGR_CLKSRC_OFFSET 16 |
||||
#define CLKMGR_CLKSRC_MAIN 0 |
||||
#define CLKMGR_CLKSRC_PER 1 |
||||
#define CLKMGR_CLKSRC_OSC1 2 |
||||
#define CLKMGR_CLKSRC_INTOSC 3 |
||||
#define CLKMGR_CLKSRC_FPGA 4 |
||||
#define CLKMGR_CLKCNT_MSK 0x7ff |
||||
|
||||
#define CLKMGR_FDBCK_MDIV_MASK 0xff |
||||
#define CLKMGR_FDBCK_MDIV_OFFSET 24 |
||||
|
||||
#define CLKMGR_PLLC0_DIV_MASK 0xff |
||||
#define CLKMGR_PLLC1_DIV_MASK 0xff |
||||
#define CLKMGR_PLLC0_EN_OFFSET 27 |
||||
#define CLKMGR_PLLC1_EN_OFFSET 24 |
||||
|
||||
#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 |
||||
#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8 |
||||
#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16 |
||||
#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 |
||||
#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 |
||||
#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 |
||||
|
||||
#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3 |
||||
#define CLKMGR_NOCDIV_DIV1 0 |
||||
#define CLKMGR_NOCDIV_DIV2 1 |
||||
#define CLKMGR_NOCDIV_DIV4 2 |
||||
#define CLKMGR_NOCDIV_DIV8 3 |
||||
#define CLKMGR_CSPDBGCLK_DIV1 0 |
||||
#define CLKMGR_CSPDBGCLK_DIV4 1 |
||||
|
||||
#define CLKMGR_MSCNT_CONST 200 |
||||
#define CLKMGR_MDIV_CONST 6 |
||||
#define CLKMGR_HSCNT_CONST 9 |
||||
|
||||
#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff |
||||
#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9 |
||||
#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff |
||||
|
||||
#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26 |
||||
#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27 |
||||
#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28 |
||||
|
||||
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020 |
||||
|
||||
#endif /* _CLOCK_MANAGER_S10_ */ |
||||
@ -0,0 +1,34 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
* |
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _HANDOFF_S10_H_ |
||||
#define _HANDOFF_S10_H_ |
||||
|
||||
/*
|
||||
* Offset for HW handoff from Quartus tools |
||||
*/ |
||||
#define S10_HANDOFF_BASE 0xFFE3F000 |
||||
#define S10_HANDOFF_MUX (S10_HANDOFF_BASE + 0x10) |
||||
#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0) |
||||
#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330) |
||||
#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0) |
||||
#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580) |
||||
#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610) |
||||
#define S10_HANDOFF_MAGIC_MUX 0x504D5558 |
||||
#define S10_HANDOFF_MAGIC_IOCTL 0x494F4354 |
||||
#define S10_HANDOFF_MAGIC_FPGA 0x46504741 |
||||
#define S10_HANDOFF_MAGIC_DELAY 0x444C4159 |
||||
#define S10_HANDOFF_MAGIC_CLOCK 0x434C4B53 |
||||
#define S10_HANDOFF_MAGIC_MISC 0x4D495343 |
||||
#define S10_HANDOFF_OFFSET_LENGTH 0x4 |
||||
#define S10_HANDOFF_OFFSET_DATA 0x10 |
||||
|
||||
#define S10_HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) |
||||
#define S10_HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) |
||||
|
||||
#define S10_HANDOFF_SIZE 4096 |
||||
|
||||
#endif /* _HANDOFF_S10_H_ */ |
||||
@ -0,0 +1,116 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
* |
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _RESET_MANAGER_S10_ |
||||
#define _RESET_MANAGER_S10_ |
||||
|
||||
void reset_cpu(ulong addr); |
||||
void reset_deassert_peripherals_handoff(void); |
||||
|
||||
void socfpga_bridges_reset(int enable); |
||||
|
||||
void socfpga_per_reset(u32 reset, int set); |
||||
void socfpga_per_reset_all(void); |
||||
|
||||
struct socfpga_reset_manager { |
||||
u32 status; |
||||
u32 mpu_rst_stat; |
||||
u32 misc_stat; |
||||
u32 padding1; |
||||
u32 hdsk_en; |
||||
u32 hdsk_req; |
||||
u32 hdsk_ack; |
||||
u32 hdsk_stall; |
||||
u32 mpumodrst; |
||||
u32 per0modrst; |
||||
u32 per1modrst; |
||||
u32 brgmodrst; |
||||
u32 padding2; |
||||
u32 cold_mod_reset; |
||||
u32 padding3; |
||||
u32 dbg_mod_reset; |
||||
u32 tap_mod_reset; |
||||
u32 padding4; |
||||
u32 padding5; |
||||
u32 brg_warm_mask; |
||||
u32 padding6[3]; |
||||
u32 tst_stat; |
||||
u32 padding7; |
||||
u32 hdsk_timeout; |
||||
u32 mpul2flushtimeout; |
||||
u32 dbghdsktimeout; |
||||
}; |
||||
|
||||
#define RSTMGR_MPUMODRST_CORE0 0 |
||||
#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 |
||||
#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 |
||||
|
||||
/*
|
||||
* Define a reset identifier, from which a permodrst bank ID |
||||
* and reset ID can be extracted using the subsequent macros |
||||
* RSTMGR_RESET() and RSTMGR_BANK(). |
||||
*/ |
||||
#define RSTMGR_BANK_OFFSET 8 |
||||
#define RSTMGR_BANK_MASK 0x7 |
||||
#define RSTMGR_RESET_OFFSET 0 |
||||
#define RSTMGR_RESET_MASK 0x1f |
||||
#define RSTMGR_DEFINE(_bank, _offset) \ |
||||
((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) |
||||
|
||||
/* Extract reset ID from the reset identifier. */ |
||||
#define RSTMGR_RESET(_reset) \ |
||||
(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) |
||||
|
||||
/* Extract bank ID from the reset identifier. */ |
||||
#define RSTMGR_BANK(_reset) \ |
||||
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) |
||||
|
||||
/*
|
||||
* SocFPGA Stratix10 reset IDs, bank mapping is as follows: |
||||
* 0 ... mpumodrst |
||||
* 1 ... per0modrst |
||||
* 2 ... per1modrst |
||||
* 3 ... brgmodrst |
||||
*/ |
||||
#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) |
||||
#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) |
||||
#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) |
||||
#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3) |
||||
#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4) |
||||
#define RSTMGR_NAND RSTMGR_DEFINE(1, 5) |
||||
#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) |
||||
#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8) |
||||
#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9) |
||||
#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10) |
||||
#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11) |
||||
#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12) |
||||
#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13) |
||||
#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15) |
||||
#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) |
||||
#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) |
||||
#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) |
||||
#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) |
||||
#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) |
||||
#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) |
||||
#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3) |
||||
#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) |
||||
#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8) |
||||
#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9) |
||||
#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10) |
||||
#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11) |
||||
#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12) |
||||
#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) |
||||
#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) |
||||
#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24) |
||||
#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25) |
||||
#define RSTMGR_SDR RSTMGR_DEFINE(3, 6) |
||||
|
||||
void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state); |
||||
|
||||
/* Create a human-readable reference to SoCFPGA reset. */ |
||||
#define SOCFPGA_RESET(_name) RSTMGR_##_name |
||||
|
||||
#endif /* _RESET_MANAGER_S10_ */ |
||||
@ -0,0 +1,442 @@ |
||||
/*
|
||||
* Copyright Altera Corporation (C) 2014-2015 |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef _SOCFPGA_SDRAM_GEN5_H_ |
||||
#define _SOCFPGA_SDRAM_GEN5_H_ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
unsigned long sdram_calculate_size(void); |
||||
int sdram_mmr_init_full(unsigned int sdr_phy_reg); |
||||
int sdram_calibration_full(void); |
||||
|
||||
const struct socfpga_sdram_config *socfpga_get_sdram_config(void); |
||||
|
||||
void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); |
||||
void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem); |
||||
const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void); |
||||
const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void); |
||||
const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void); |
||||
|
||||
#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) |
||||
|
||||
struct socfpga_sdr_ctrl { |
||||
u32 ctrl_cfg; |
||||
u32 dram_timing1; |
||||
u32 dram_timing2; |
||||
u32 dram_timing3; |
||||
u32 dram_timing4; /* 0x10 */ |
||||
u32 lowpwr_timing; |
||||
u32 dram_odt; |
||||
u32 extratime1; |
||||
u32 __padding0[3]; |
||||
u32 dram_addrw; /* 0x2c */ |
||||
u32 dram_if_width; /* 0x30 */ |
||||
u32 dram_dev_width; |
||||
u32 dram_sts; |
||||
u32 dram_intr; |
||||
u32 sbe_count; /* 0x40 */ |
||||
u32 dbe_count; |
||||
u32 err_addr; |
||||
u32 drop_count; |
||||
u32 drop_addr; /* 0x50 */ |
||||
u32 lowpwr_eq; |
||||
u32 lowpwr_ack; |
||||
u32 static_cfg; |
||||
u32 ctrl_width; /* 0x60 */ |
||||
u32 cport_width; |
||||
u32 cport_wmap; |
||||
u32 cport_rmap; |
||||
u32 rfifo_cmap; /* 0x70 */ |
||||
u32 wfifo_cmap; |
||||
u32 cport_rdwr; |
||||
u32 port_cfg; |
||||
u32 fpgaport_rst; /* 0x80 */ |
||||
u32 __padding1; |
||||
u32 fifo_cfg; |
||||
u32 protport_default; |
||||
u32 prot_rule_addr; /* 0x90 */ |
||||
u32 prot_rule_id; |
||||
u32 prot_rule_data; |
||||
u32 prot_rule_rdwr; |
||||
u32 __padding2[3]; |
||||
u32 mp_priority; /* 0xac */ |
||||
u32 mp_weight0; /* 0xb0 */ |
||||
u32 mp_weight1; |
||||
u32 mp_weight2; |
||||
u32 mp_weight3; |
||||
u32 mp_pacing0; /* 0xc0 */ |
||||
u32 mp_pacing1; |
||||
u32 mp_pacing2; |
||||
u32 mp_pacing3; |
||||
u32 mp_threshold0; /* 0xd0 */ |
||||
u32 mp_threshold1; |
||||
u32 mp_threshold2; |
||||
u32 __padding3[29]; |
||||
u32 phy_ctrl0; /* 0x150 */ |
||||
u32 phy_ctrl1; |
||||
u32 phy_ctrl2; |
||||
}; |
||||
|
||||
/* SDRAM configuration structure for the SPL. */ |
||||
struct socfpga_sdram_config { |
||||
u32 ctrl_cfg; |
||||
u32 dram_timing1; |
||||
u32 dram_timing2; |
||||
u32 dram_timing3; |
||||
u32 dram_timing4; |
||||
u32 lowpwr_timing; |
||||
u32 dram_odt; |
||||
u32 extratime1; |
||||
u32 dram_addrw; |
||||
u32 dram_if_width; |
||||
u32 dram_dev_width; |
||||
u32 dram_intr; |
||||
u32 lowpwr_eq; |
||||
u32 static_cfg; |
||||
u32 ctrl_width; |
||||
u32 cport_width; |
||||
u32 cport_wmap; |
||||
u32 cport_rmap; |
||||
u32 rfifo_cmap; |
||||
u32 wfifo_cmap; |
||||
u32 cport_rdwr; |
||||
u32 port_cfg; |
||||
u32 fpgaport_rst; |
||||
u32 fifo_cfg; |
||||
u32 mp_priority; |
||||
u32 mp_weight0; |
||||
u32 mp_weight1; |
||||
u32 mp_weight2; |
||||
u32 mp_weight3; |
||||
u32 mp_pacing0; |
||||
u32 mp_pacing1; |
||||
u32 mp_pacing2; |
||||
u32 mp_pacing3; |
||||
u32 mp_threshold0; |
||||
u32 mp_threshold1; |
||||
u32 mp_threshold2; |
||||
u32 phy_ctrl0; |
||||
}; |
||||
|
||||
struct socfpga_sdram_rw_mgr_config { |
||||
u8 activate_0_and_1; |
||||
u8 activate_0_and_1_wait1; |
||||
u8 activate_0_and_1_wait2; |
||||
u8 activate_1; |
||||
u8 clear_dqs_enable; |
||||
u8 guaranteed_read; |
||||
u8 guaranteed_read_cont; |
||||
u8 guaranteed_write; |
||||
u8 guaranteed_write_wait0; |
||||
u8 guaranteed_write_wait1; |
||||
u8 guaranteed_write_wait2; |
||||
u8 guaranteed_write_wait3; |
||||
u8 idle; |
||||
u8 idle_loop1; |
||||
u8 idle_loop2; |
||||
u8 init_reset_0_cke_0; |
||||
u8 init_reset_1_cke_0; |
||||
u8 lfsr_wr_rd_bank_0; |
||||
u8 lfsr_wr_rd_bank_0_data; |
||||
u8 lfsr_wr_rd_bank_0_dqs; |
||||
u8 lfsr_wr_rd_bank_0_nop; |
||||
u8 lfsr_wr_rd_bank_0_wait; |
||||
u8 lfsr_wr_rd_bank_0_wl_1; |
||||
u8 lfsr_wr_rd_dm_bank_0; |
||||
u8 lfsr_wr_rd_dm_bank_0_data; |
||||
u8 lfsr_wr_rd_dm_bank_0_dqs; |
||||
u8 lfsr_wr_rd_dm_bank_0_nop; |
||||
u8 lfsr_wr_rd_dm_bank_0_wait; |
||||
u8 lfsr_wr_rd_dm_bank_0_wl_1; |
||||
u8 mrs0_dll_reset; |
||||
u8 mrs0_dll_reset_mirr; |
||||
u8 mrs0_user; |
||||
u8 mrs0_user_mirr; |
||||
u8 mrs1; |
||||
u8 mrs1_mirr; |
||||
u8 mrs2; |
||||
u8 mrs2_mirr; |
||||
u8 mrs3; |
||||
u8 mrs3_mirr; |
||||
u8 precharge_all; |
||||
u8 read_b2b; |
||||
u8 read_b2b_wait1; |
||||
u8 read_b2b_wait2; |
||||
u8 refresh_all; |
||||
u8 rreturn; |
||||
u8 sgle_read; |
||||
u8 zqcl; |
||||
|
||||
u8 true_mem_data_mask_width; |
||||
u8 mem_address_mirroring; |
||||
u8 mem_data_mask_width; |
||||
u8 mem_data_width; |
||||
u8 mem_dq_per_read_dqs; |
||||
u8 mem_dq_per_write_dqs; |
||||
u8 mem_if_read_dqs_width; |
||||
u8 mem_if_write_dqs_width; |
||||
u8 mem_number_of_cs_per_dimm; |
||||
u8 mem_number_of_ranks; |
||||
u8 mem_virtual_groups_per_read_dqs; |
||||
u8 mem_virtual_groups_per_write_dqs; |
||||
}; |
||||
|
||||
struct socfpga_sdram_io_config { |
||||
u16 delay_per_opa_tap; |
||||
u8 delay_per_dchain_tap; |
||||
u8 delay_per_dqs_en_dchain_tap; |
||||
u8 dll_chain_length; |
||||
u8 dqdqs_out_phase_max; |
||||
u8 dqs_en_delay_max; |
||||
u8 dqs_en_delay_offset; |
||||
u8 dqs_en_phase_max; |
||||
u8 dqs_in_delay_max; |
||||
u8 dqs_in_reserve; |
||||
u8 dqs_out_reserve; |
||||
u8 io_in_delay_max; |
||||
u8 io_out1_delay_max; |
||||
u8 io_out2_delay_max; |
||||
u8 shift_dqs_en_when_shift_dqs; |
||||
}; |
||||
|
||||
struct socfpga_sdram_misc_config { |
||||
u32 reg_file_init_seq_signature; |
||||
u8 afi_rate_ratio; |
||||
u8 calib_lfifo_offset; |
||||
u8 calib_vfifo_offset; |
||||
u8 enable_super_quick_calibration; |
||||
u8 max_latency_count_width; |
||||
u8 read_valid_fifo_size; |
||||
u8 tinit_cntr0_val; |
||||
u8 tinit_cntr1_val; |
||||
u8 tinit_cntr2_val; |
||||
u8 treset_cntr0_val; |
||||
u8 treset_cntr1_val; |
||||
u8 treset_cntr2_val; |
||||
}; |
||||
|
||||
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 |
||||
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 |
||||
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 |
||||
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 |
||||
#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 |
||||
#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 |
||||
#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 |
||||
#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 |
||||
#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 |
||||
#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 |
||||
#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 |
||||
#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 |
||||
#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 |
||||
#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 |
||||
#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 |
||||
#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 |
||||
#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 |
||||
#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 |
||||
/* Register template: sdr::ctrlgrp::dramtiming1 */ |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 |
||||
#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f |
||||
/* Register template: sdr::ctrlgrp::dramtiming2 */ |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 |
||||
#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff |
||||
/* Register template: sdr::ctrlgrp::dramtiming3 */ |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 |
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f |
||||
/* Register template: sdr::ctrlgrp::dramtiming4 */ |
||||
#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 |
||||
#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 |
||||
#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 |
||||
#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 |
||||
#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 |
||||
#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff |
||||
/* Register template: sdr::ctrlgrp::lowpwrtiming */ |
||||
#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 |
||||
#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 |
||||
#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 |
||||
#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff |
||||
/* Register template: sdr::ctrlgrp::dramaddrw */ |
||||
#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 |
||||
#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 |
||||
#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 |
||||
#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 |
||||
#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 |
||||
#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 |
||||
#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 |
||||
#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f |
||||
/* Register template: sdr::ctrlgrp::dramifwidth */ |
||||
#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 |
||||
#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff |
||||
/* Register template: sdr::ctrlgrp::dramdevwidth */ |
||||
#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 |
||||
#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f |
||||
/* Register template: sdr::ctrlgrp::dramintr */ |
||||
#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 |
||||
#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 |
||||
#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 |
||||
#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 |
||||
/* Register template: sdr::ctrlgrp::staticcfg */ |
||||
#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 |
||||
#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 |
||||
#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 |
||||
#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 |
||||
#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 |
||||
#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 |
||||
/* Register template: sdr::ctrlgrp::ctrlwidth */ |
||||
#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 |
||||
#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 |
||||
/* Register template: sdr::ctrlgrp::cportwidth */ |
||||
#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 |
||||
#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff |
||||
/* Register template: sdr::ctrlgrp::cportwmap */ |
||||
#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 |
||||
#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff |
||||
/* Register template: sdr::ctrlgrp::cportrmap */ |
||||
#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 |
||||
#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff |
||||
/* Register template: sdr::ctrlgrp::rfifocmap */ |
||||
#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 |
||||
#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff |
||||
/* Register template: sdr::ctrlgrp::wfifocmap */ |
||||
#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 |
||||
#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff |
||||
/* Register template: sdr::ctrlgrp::cportrdwr */ |
||||
#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 |
||||
#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff |
||||
/* Register template: sdr::ctrlgrp::portcfg */ |
||||
#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 |
||||
#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 |
||||
#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 |
||||
#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff |
||||
/* Register template: sdr::ctrlgrp::fifocfg */ |
||||
#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 |
||||
#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 |
||||
#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 |
||||
#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff |
||||
/* Register template: sdr::ctrlgrp::mppriority */ |
||||
#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 |
||||
#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff |
||||
/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff |
||||
/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff |
||||
/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff |
||||
/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 |
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff |
||||
/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff |
||||
/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff |
||||
/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff |
||||
/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 |
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff |
||||
/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ |
||||
#define \ |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 |
||||
#define \ |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
|
||||
0xffffffff |
||||
/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ |
||||
#define \ |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 |
||||
#define \ |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
|
||||
0xffffffff |
||||
/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ |
||||
#define \ |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 |
||||
#define \ |
||||
SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
|
||||
0x0000ffff |
||||
/* Register template: sdr::ctrlgrp::remappriority */ |
||||
#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 |
||||
#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff |
||||
/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ |
||||
(((x) << 12) & 0xfffff000) |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ |
||||
(((x) << 10) & 0x00000c00) |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ |
||||
(((x) << 6) & 0x000000c0) |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ |
||||
(((x) << 8) & 0x00000100) |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ |
||||
(((x) << 9) & 0x00000200) |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ |
||||
(((x) << 4) & 0x00000030) |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ |
||||
(((x) << 2) & 0x0000000c) |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ |
||||
(((x) << 0) & 0x00000003) |
||||
/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ |
||||
(((x) << 12) & 0xfffff000) |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ |
||||
(((x) << 0) & 0x00000fff) |
||||
/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ |
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ |
||||
(((x) << 0) & 0x00000fff) |
||||
/* Register template: sdr::ctrlgrp::dramodt */ |
||||
#define SDR_CTRLGRP_DRAMODT_READ_LSB 4 |
||||
#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 |
||||
#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 |
||||
#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f |
||||
/* Field instance: sdr::ctrlgrp::dramsts */ |
||||
#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 |
||||
#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 |
||||
/* Register template: sdr::ctrlgrp::extratime1 */ |
||||
#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20 |
||||
#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24 |
||||
#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28 |
||||
|
||||
/* SDRAM width macro for configuration with ECC */ |
||||
#define SDRAM_WIDTH_32BIT_WITH_ECC 40 |
||||
#define SDRAM_WIDTH_16BIT_WITH_ECC 24 |
||||
|
||||
#endif |
||||
#endif /* _SOCFPGA_SDRAM_GEN5_H_ */ |
||||
@ -0,0 +1,176 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
* |
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _SYSTEM_MANAGER_S10_ |
||||
#define _SYSTEM_MANAGER_S10_ |
||||
|
||||
void sysmgr_pinmux_init(void); |
||||
void populate_sysmgr_fpgaintf_module(void); |
||||
void populate_sysmgr_pinmux(void); |
||||
void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); |
||||
void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); |
||||
void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); |
||||
void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); |
||||
|
||||
struct socfpga_system_manager { |
||||
/* System Manager Module */ |
||||
u32 siliconid1; /* 0x00 */ |
||||
u32 siliconid2; |
||||
u32 wddbg; |
||||
u32 _pad_0xc; |
||||
u32 mpu_status; /* 0x10 */ |
||||
u32 mpu_ace; |
||||
u32 _pad_0x18_0x1c[2]; |
||||
u32 dma; /* 0x20 */ |
||||
u32 dma_periph; |
||||
/* SDMMC Controller Group */ |
||||
u32 sdmmcgrp_ctrl; |
||||
u32 sdmmcgrp_l3master; |
||||
/* NAND Flash Controller Register Group */ |
||||
u32 nandgrp_bootstrap; /* 0x30 */ |
||||
u32 nandgrp_l3master; |
||||
/* USB Controller Group */ |
||||
u32 usb0_l3master; |
||||
u32 usb1_l3master; |
||||
/* EMAC Group */ |
||||
u32 emac_gbl; /* 0x40 */ |
||||
u32 emac0; |
||||
u32 emac1; |
||||
u32 emac2; |
||||
u32 emac0_ace; /* 0x50 */ |
||||
u32 emac1_ace; |
||||
u32 emac2_ace; |
||||
u32 nand_axuser; |
||||
u32 _pad_0x60_0x64[2]; /* 0x60 */ |
||||
/* FPGA interface Group */ |
||||
u32 fpgaintf_en_1; |
||||
u32 fpgaintf_en_2; |
||||
u32 fpgaintf_en_3; /* 0x70 */ |
||||
u32 dma_l3master; |
||||
u32 etr_l3master; |
||||
u32 _pad_0x7c; |
||||
u32 sec_ctrl_slt; /* 0x80 */ |
||||
u32 osc_trim; |
||||
u32 _pad_0x88_0x8c[2]; |
||||
/* ECC Group */ |
||||
u32 ecc_intmask_value; /* 0x90 */ |
||||
u32 ecc_intmask_set; |
||||
u32 ecc_intmask_clr; |
||||
u32 ecc_intstatus_serr; |
||||
u32 ecc_intstatus_derr; /* 0xa0 */ |
||||
u32 _pad_0xa4_0xac[3]; |
||||
u32 noc_addr_remap; /* 0xb0 */ |
||||
u32 hmc_clk; |
||||
u32 io_pa_ctrl; |
||||
u32 _pad_0xbc; |
||||
/* NOC Group */ |
||||
u32 noc_timeout; /* 0xc0 */ |
||||
u32 noc_idlereq_set; |
||||
u32 noc_idlereq_clr; |
||||
u32 noc_idlereq_value; |
||||
u32 noc_idleack; /* 0xd0 */ |
||||
u32 noc_idlestatus; |
||||
u32 fpga2soc_ctrl; |
||||
u32 fpga_config; |
||||
u32 iocsrclk_gate; /* 0xe0 */ |
||||
u32 gpo; |
||||
u32 gpi; |
||||
u32 _pad_0xec; |
||||
u32 mpu; /* 0xf0 */ |
||||
u32 sdm_hps_spare; |
||||
u32 hps_sdm_spare; |
||||
u32 _pad_0xfc_0x1fc[65]; |
||||
/* Boot scratch register group */ |
||||
u32 boot_scratch_cold0; /* 0x200 */ |
||||
u32 boot_scratch_cold1; |
||||
u32 boot_scratch_cold2; |
||||
u32 boot_scratch_cold3; |
||||
u32 boot_scratch_cold4; /* 0x210 */ |
||||
u32 boot_scratch_cold5; |
||||
u32 boot_scratch_cold6; |
||||
u32 boot_scratch_cold7; |
||||
u32 boot_scratch_cold8; /* 0x220 */ |
||||
u32 boot_scratch_cold9; |
||||
u32 _pad_0x228_0xffc[886]; |
||||
/* Pin select and pin control group */ |
||||
u32 pinsel0[40]; /* 0x1000 */ |
||||
u32 _pad_0x10a0_0x10fc[24]; |
||||
u32 pinsel40[8]; |
||||
u32 _pad_0x1120_0x112c[4]; |
||||
u32 ioctrl0[28]; |
||||
u32 _pad_0x11a0_0x11fc[24]; |
||||
u32 ioctrl28[20]; |
||||
u32 _pad_0x1250_0x12fc[44]; |
||||
/* Use FPGA mux */ |
||||
u32 rgmii0usefpga; /* 0x1300 */ |
||||
u32 rgmii1usefpga; |
||||
u32 rgmii2usefpga; |
||||
u32 i2c0usefpga; |
||||
u32 i2c1usefpga; |
||||
u32 i2c_emac0_usefpga; |
||||
u32 i2c_emac1_usefpga; |
||||
u32 i2c_emac2_usefpga; |
||||
u32 nandusefpga; |
||||
u32 _pad_0x1324; |
||||
u32 spim0usefpga; |
||||
u32 spim1usefpga; |
||||
u32 spis0usefpga; |
||||
u32 spis1usefpga; |
||||
u32 uart0usefpga; |
||||
u32 uart1usefpga; |
||||
u32 mdio0usefpga; |
||||
u32 mdio1usefpga; |
||||
u32 mdio2usefpga; |
||||
u32 _pad_0x134c; |
||||
u32 jtagusefpga; |
||||
u32 sdmmcusefpga; |
||||
u32 hps_osc_clk; |
||||
u32 _pad_0x135c_0x13fc[41]; |
||||
u32 iodelay0[40]; |
||||
u32 _pad_0x14a0_0x14fc[24]; |
||||
u32 iodelay40[8]; |
||||
|
||||
}; |
||||
|
||||
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) |
||||
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) |
||||
#define SYSMGR_ECC_OCRAM_EN BIT(0) |
||||
#define SYSMGR_ECC_OCRAM_SERR BIT(3) |
||||
#define SYSMGR_ECC_OCRAM_DERR BIT(4) |
||||
#define SYSMGR_FPGAINTF_USEFPGA 0x1 |
||||
|
||||
#define SYSMGR_FPGAINTF_NAND BIT(4) |
||||
#define SYSMGR_FPGAINTF_SDMMC BIT(8) |
||||
#define SYSMGR_FPGAINTF_SPIM0 BIT(16) |
||||
#define SYSMGR_FPGAINTF_SPIM1 BIT(24) |
||||
#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0) |
||||
#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8) |
||||
#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16) |
||||
|
||||
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 |
||||
#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 |
||||
|
||||
/* EMAC Group Bit definitions */ |
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 |
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 |
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 |
||||
|
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 |
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 |
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 |
||||
|
||||
#define SYSMGR_NOC_H2F_MSK 0x00000001 |
||||
#define SYSMGR_NOC_LWH2F_MSK 0x00000010 |
||||
#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001 |
||||
|
||||
#define SYSMGR_DMA_IRQ_NS 0xFF000000 |
||||
#define SYSMGR_DMA_MGR_NS 0x00010000 |
||||
|
||||
#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF |
||||
|
||||
#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F |
||||
|
||||
#endif /* _SYSTEM_MANAGER_S10_ */ |
||||
@ -0,0 +1,140 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/reset_manager.h> |
||||
#include <asm/arch/system_manager.h> |
||||
#include <dt-bindings/reset/altr,rst-mgr-s10.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static const struct socfpga_reset_manager *reset_manager_base = |
||||
(void *)SOCFPGA_RSTMGR_ADDRESS; |
||||
static const struct socfpga_system_manager *system_manager_base = |
||||
(void *)SOCFPGA_SYSMGR_ADDRESS; |
||||
|
||||
/* Assert or de-assert SoCFPGA reset manager reset. */ |
||||
void socfpga_per_reset(u32 reset, int set) |
||||
{ |
||||
const void *reg; |
||||
|
||||
if (RSTMGR_BANK(reset) == 0) |
||||
reg = &reset_manager_base->mpumodrst; |
||||
else if (RSTMGR_BANK(reset) == 1) |
||||
reg = &reset_manager_base->per0modrst; |
||||
else if (RSTMGR_BANK(reset) == 2) |
||||
reg = &reset_manager_base->per1modrst; |
||||
else if (RSTMGR_BANK(reset) == 3) |
||||
reg = &reset_manager_base->brgmodrst; |
||||
else /* Invalid reset register, do nothing */ |
||||
return; |
||||
|
||||
if (set) |
||||
setbits_le32(reg, 1 << RSTMGR_RESET(reset)); |
||||
else |
||||
clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); |
||||
} |
||||
|
||||
/*
|
||||
* Assert reset on every peripheral but L4WD0. |
||||
* Watchdog must be kept intact to prevent glitches |
||||
* and/or hangs. |
||||
*/ |
||||
void socfpga_per_reset_all(void) |
||||
{ |
||||
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); |
||||
|
||||
/* disable all except OCP and l4wd0. OCP disable later */ |
||||
writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK), |
||||
&reset_manager_base->per0modrst); |
||||
writel(~l4wd0, &reset_manager_base->per0modrst); |
||||
writel(0xffffffff, &reset_manager_base->per1modrst); |
||||
} |
||||
|
||||
void socfpga_bridges_reset(int enable) |
||||
{ |
||||
if (enable) { |
||||
/* clear idle request to all bridges */ |
||||
setbits_le32(&system_manager_base->noc_idlereq_clr, ~0); |
||||
|
||||
/* Release bridges from reset state per handoff value */ |
||||
clrbits_le32(&reset_manager_base->brgmodrst, ~0); |
||||
|
||||
/* Poll until all idleack to 0 */ |
||||
while (readl(&system_manager_base->noc_idleack)) |
||||
; |
||||
} else { |
||||
/* set idle request to all bridges */ |
||||
writel(~0, &system_manager_base->noc_idlereq_set); |
||||
|
||||
/* Enable the NOC timeout */ |
||||
writel(1, &system_manager_base->noc_timeout); |
||||
|
||||
/* Poll until all idleack to 1 */ |
||||
while ((readl(&system_manager_base->noc_idleack) ^ |
||||
(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) |
||||
; |
||||
|
||||
/* Poll until all idlestatus to 1 */ |
||||
while ((readl(&system_manager_base->noc_idlestatus) ^ |
||||
(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) |
||||
; |
||||
|
||||
/* Put all bridges (except NOR DDR scheduler) into reset */ |
||||
setbits_le32(&reset_manager_base->brgmodrst, |
||||
~RSTMGR_BRGMODRST_DDRSCH_MASK); |
||||
|
||||
/* Disable NOC timeout */ |
||||
writel(0, &system_manager_base->noc_timeout); |
||||
} |
||||
} |
||||
|
||||
/* of_reset_id: emac reset id
|
||||
* state: 0 - disable reset, !0 - enable reset |
||||
*/ |
||||
void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state) |
||||
{ |
||||
u32 reset_emac; |
||||
u32 reset_emacocp; |
||||
|
||||
/* hardcode this now */ |
||||
switch (of_reset_id) { |
||||
case EMAC0_RESET: |
||||
reset_emac = SOCFPGA_RESET(EMAC0); |
||||
reset_emacocp = SOCFPGA_RESET(EMAC0_OCP); |
||||
break; |
||||
case EMAC1_RESET: |
||||
reset_emac = SOCFPGA_RESET(EMAC1); |
||||
reset_emacocp = SOCFPGA_RESET(EMAC1_OCP); |
||||
break; |
||||
case EMAC2_RESET: |
||||
reset_emac = SOCFPGA_RESET(EMAC2); |
||||
reset_emacocp = SOCFPGA_RESET(EMAC2_OCP); |
||||
break; |
||||
default: |
||||
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); |
||||
hang(); |
||||
break; |
||||
} |
||||
|
||||
/* Reset ECC OCP first */ |
||||
socfpga_per_reset(reset_emacocp, state); |
||||
|
||||
/* Release the EMAC controller from reset */ |
||||
socfpga_per_reset(reset_emac, state); |
||||
} |
||||
|
||||
/*
|
||||
* Release peripherals from reset based on handoff |
||||
*/ |
||||
void reset_deassert_peripherals_handoff(void) |
||||
{ |
||||
writel(0, &reset_manager_base->per1modrst); |
||||
/* Enable OCP first */ |
||||
writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst); |
||||
writel(0, &reset_manager_base->per0modrst); |
||||
} |
||||
@ -0,0 +1,91 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/system_manager.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static struct socfpga_system_manager *sysmgr_regs = |
||||
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
||||
|
||||
/*
|
||||
* Configure all the pin muxes |
||||
*/ |
||||
void sysmgr_pinmux_init(void) |
||||
{ |
||||
populate_sysmgr_pinmux(); |
||||
populate_sysmgr_fpgaintf_module(); |
||||
} |
||||
|
||||
/*
|
||||
* Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. |
||||
* The value is not wrote to SYSMGR.FPGAINTF.MODULE but |
||||
* CONFIG_SYSMGR_ISWGRP_HANDOFF. |
||||
*/ |
||||
void populate_sysmgr_fpgaintf_module(void) |
||||
{ |
||||
u32 handoff_val = 0; |
||||
|
||||
/* Enable the signal for those HPS peripherals that use FPGA. */ |
||||
if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) |
||||
handoff_val |= SYSMGR_FPGAINTF_NAND; |
||||
if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) |
||||
handoff_val |= SYSMGR_FPGAINTF_SDMMC; |
||||
if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) |
||||
handoff_val |= SYSMGR_FPGAINTF_SPIM0; |
||||
if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) |
||||
handoff_val |= SYSMGR_FPGAINTF_SPIM1; |
||||
writel(handoff_val, &sysmgr_regs->fpgaintf_en_2); |
||||
|
||||
handoff_val = 0; |
||||
if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) |
||||
handoff_val |= SYSMGR_FPGAINTF_EMAC0; |
||||
if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) |
||||
handoff_val |= SYSMGR_FPGAINTF_EMAC1; |
||||
if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA) |
||||
handoff_val |= SYSMGR_FPGAINTF_EMAC2; |
||||
writel(handoff_val, &sysmgr_regs->fpgaintf_en_3); |
||||
} |
||||
|
||||
/*
|
||||
* Configure all the pin muxes |
||||
*/ |
||||
void populate_sysmgr_pinmux(void) |
||||
{ |
||||
const u32 *sys_mgr_table_u32; |
||||
unsigned int len, i; |
||||
|
||||
/* setup the pin sel */ |
||||
sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len); |
||||
for (i = 0; i < len; i = i + 2) { |
||||
writel(sys_mgr_table_u32[i + 1], |
||||
sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]); |
||||
} |
||||
|
||||
/* setup the pin ctrl */ |
||||
sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len); |
||||
for (i = 0; i < len; i = i + 2) { |
||||
writel(sys_mgr_table_u32[i + 1], |
||||
sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]); |
||||
} |
||||
|
||||
/* setup the fpga use */ |
||||
sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len); |
||||
for (i = 0; i < len; i = i + 2) { |
||||
writel(sys_mgr_table_u32[i + 1], |
||||
sys_mgr_table_u32[i] + |
||||
(u8 *)&sysmgr_regs->rgmii0usefpga); |
||||
} |
||||
|
||||
/* setup the IO delay */ |
||||
sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len); |
||||
for (i = 0; i < len; i = i + 2) { |
||||
writel(sys_mgr_table_u32[i + 1], |
||||
sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]); |
||||
} |
||||
} |
||||
@ -0,0 +1,56 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/handoff_s10.h> |
||||
|
||||
static void sysmgr_pinmux_handoff_read(void *handoff_address, |
||||
const u32 **table, |
||||
unsigned int *table_len) |
||||
{ |
||||
unsigned int handoff_entry = (swab32(readl(handoff_address + |
||||
S10_HANDOFF_OFFSET_LENGTH)) - |
||||
S10_HANDOFF_OFFSET_DATA) / |
||||
sizeof(unsigned int); |
||||
unsigned int handoff_chunk[handoff_entry], temp, i; |
||||
|
||||
if (swab32(readl(S10_HANDOFF_MUX)) == S10_HANDOFF_MAGIC_MUX) { |
||||
/* using handoff from Quartus tools if exists */ |
||||
for (i = 0; i < handoff_entry; i++) { |
||||
temp = readl(handoff_address + |
||||
S10_HANDOFF_OFFSET_DATA + (i * 4)); |
||||
handoff_chunk[i] = swab32(temp); |
||||
} |
||||
*table = handoff_chunk; |
||||
*table_len = ARRAY_SIZE(handoff_chunk); |
||||
} |
||||
} |
||||
|
||||
void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len) |
||||
{ |
||||
sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_MUX, table, |
||||
table_len); |
||||
} |
||||
|
||||
void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len) |
||||
{ |
||||
sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_IOCTL, table, |
||||
table_len); |
||||
} |
||||
|
||||
void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len) |
||||
{ |
||||
sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_FPGA, table, |
||||
table_len); |
||||
} |
||||
|
||||
void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len) |
||||
{ |
||||
sysmgr_pinmux_handoff_read((void *)S10_HANODFF_DELAY, table, |
||||
table_len); |
||||
} |
||||
@ -0,0 +1,59 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/clock_manager.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/handoff_s10.h> |
||||
#include <asm/arch/system_manager.h> |
||||
|
||||
static const struct socfpga_system_manager *sysmgr_regs = |
||||
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
||||
|
||||
const struct cm_config * const cm_get_default_config(void) |
||||
{ |
||||
struct cm_config *cm_handoff_cfg = (struct cm_config *) |
||||
(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA); |
||||
u32 *conversion = (u32 *)cm_handoff_cfg; |
||||
u32 i; |
||||
u32 handoff_clk = readl(S10_HANDOFF_CLOCK); |
||||
|
||||
if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) { |
||||
writel(swab32(handoff_clk), S10_HANDOFF_CLOCK); |
||||
for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++) |
||||
conversion[i] = swab32(conversion[i]); |
||||
return cm_handoff_cfg; |
||||
} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) { |
||||
return cm_handoff_cfg; |
||||
} |
||||
|
||||
return NULL; |
||||
} |
||||
|
||||
const unsigned int cm_get_osc_clk_hz(void) |
||||
{ |
||||
#ifdef CONFIG_SPL_BUILD |
||||
u32 clock = readl(S10_HANDOFF_CLOCK_OSC); |
||||
|
||||
writel(clock, &sysmgr_regs->boot_scratch_cold1); |
||||
#endif |
||||
return readl(&sysmgr_regs->boot_scratch_cold1); |
||||
} |
||||
|
||||
const unsigned int cm_get_intosc_clk_hz(void) |
||||
{ |
||||
return CLKMGR_INTOSC_HZ; |
||||
} |
||||
|
||||
const unsigned int cm_get_fpga_clk_hz(void) |
||||
{ |
||||
#ifdef CONFIG_SPL_BUILD |
||||
u32 clock = readl(S10_HANDOFF_CLOCK_FPGA); |
||||
|
||||
writel(clock, &sysmgr_regs->boot_scratch_cold2); |
||||
#endif |
||||
return readl(&sysmgr_regs->boot_scratch_cold2); |
||||
} |
||||
@ -1,5 +1,5 @@ |
||||
config ALTERA_SDRAM |
||||
bool "SoCFPGA DDR SDRAM driver" |
||||
depends on TARGET_SOCFPGA_GEN5 |
||||
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 |
||||
help |
||||
Enable DDR SDRAM controller for the SoCFPGA devices. |
||||
|
||||
@ -0,0 +1,741 @@ |
||||
/*
|
||||
* Copyright (C) 2017 Intel Corporation <www.intel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <fdtdec.h> |
||||
#include <malloc.h> |
||||
#include <wait_bit.h> |
||||
#include <watchdog.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/fpga_manager.h> |
||||
#include <asm/arch/misc.h> |
||||
#include <asm/arch/reset_manager.h> |
||||
#include <asm/arch/sdram.h> |
||||
#include <linux/kernel.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static void sdram_mmr_init(void); |
||||
static u64 sdram_size_calc(void); |
||||
|
||||
/* FAWBANK - Number of Bank of a given device involved in the FAW period. */ |
||||
#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1) |
||||
|
||||
#define ARRIA_DDR_CONFIG(A, B, C, R) \ |
||||
(((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) |
||||
#define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config) |
||||
#define DDR_REG_SEQ2CORE 0xFFD0507C |
||||
#define DDR_REG_CORE2SEQ 0xFFD05078 |
||||
#define DDR_READ_LATENCY_DELAY 40 |
||||
#define DDR_SIZE_2GB_HEX 0x80000000 |
||||
#define DDR_MAX_TRIES 0x00100000 |
||||
|
||||
#define IO48_MMR_DRAMSTS 0xFFCFA0EC |
||||
#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110 |
||||
#define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114 |
||||
#define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118 |
||||
|
||||
#define SEQ2CORE_MASK 0xF |
||||
#define CORE2SEQ_INT_REQ 0xF |
||||
#define SEQ2CORE_INT_RESP_BIT 3 |
||||
|
||||
static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = |
||||
(void *)SOCFPGA_SDR_ADDRESS; |
||||
static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = |
||||
(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; |
||||
static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram |
||||
*socfpga_noc_fw_ddr_mpu_fpga2sdram_base = |
||||
(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS; |
||||
static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base = |
||||
(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; |
||||
static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = |
||||
(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; |
||||
|
||||
/* The following are the supported configurations */ |
||||
static u32 ddr_config[] = { |
||||
/* Chip - Row - Bank - Column Style */ |
||||
/* All Types */ |
||||
ARRIA_DDR_CONFIG(0, 3, 10, 12), |
||||
ARRIA_DDR_CONFIG(0, 3, 10, 13), |
||||
ARRIA_DDR_CONFIG(0, 3, 10, 14), |
||||
ARRIA_DDR_CONFIG(0, 3, 10, 15), |
||||
ARRIA_DDR_CONFIG(0, 3, 10, 16), |
||||
ARRIA_DDR_CONFIG(0, 3, 10, 17), |
||||
/* LPDDR x16 */ |
||||
ARRIA_DDR_CONFIG(0, 3, 11, 14), |
||||
ARRIA_DDR_CONFIG(0, 3, 11, 15), |
||||
ARRIA_DDR_CONFIG(0, 3, 11, 16), |
||||
ARRIA_DDR_CONFIG(0, 3, 12, 15), |
||||
/* DDR4 Only */ |
||||
ARRIA_DDR_CONFIG(0, 4, 10, 14), |
||||
ARRIA_DDR_CONFIG(0, 4, 10, 15), |
||||
ARRIA_DDR_CONFIG(0, 4, 10, 16), |
||||
ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */ |
||||
/* Chip - Bank - Row - Column Style */ |
||||
ARRIA_DDR_CONFIG(1, 3, 10, 12), |
||||
ARRIA_DDR_CONFIG(1, 3, 10, 13), |
||||
ARRIA_DDR_CONFIG(1, 3, 10, 14), |
||||
ARRIA_DDR_CONFIG(1, 3, 10, 15), |
||||
ARRIA_DDR_CONFIG(1, 3, 10, 16), |
||||
ARRIA_DDR_CONFIG(1, 3, 10, 17), |
||||
ARRIA_DDR_CONFIG(1, 3, 11, 14), |
||||
ARRIA_DDR_CONFIG(1, 3, 11, 15), |
||||
ARRIA_DDR_CONFIG(1, 3, 11, 16), |
||||
ARRIA_DDR_CONFIG(1, 3, 12, 15), |
||||
/* DDR4 Only */ |
||||
ARRIA_DDR_CONFIG(1, 4, 10, 14), |
||||
ARRIA_DDR_CONFIG(1, 4, 10, 15), |
||||
ARRIA_DDR_CONFIG(1, 4, 10, 16), |
||||
ARRIA_DDR_CONFIG(1, 4, 10, 17), |
||||
}; |
||||
|
||||
static int match_ddr_conf(u32 ddr_conf) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) { |
||||
if (ddr_conf == ddr_config[i]) |
||||
return i; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
/* Check whether SDRAM is successfully Calibrated */ |
||||
static int is_sdram_cal_success(void) |
||||
{ |
||||
return readl(&socfpga_ecc_hmc_base->ddrcalstat); |
||||
} |
||||
|
||||
static unsigned char ddr_get_bit(u32 ereg, unsigned char bit) |
||||
{ |
||||
u32 reg = readl(ereg); |
||||
|
||||
return (reg & BIT(bit)) ? 1 : 0; |
||||
} |
||||
|
||||
static unsigned char ddr_wait_bit(u32 ereg, u32 bit, |
||||
u32 expected, u32 timeout_usec) |
||||
{ |
||||
u32 tmr; |
||||
|
||||
for (tmr = 0; tmr < timeout_usec; tmr += 100) { |
||||
udelay(100); |
||||
WATCHDOG_RESET(); |
||||
if (ddr_get_bit(ereg, bit) == expected) |
||||
return 0; |
||||
} |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
static int emif_clear(void) |
||||
{ |
||||
u32 i = DDR_MAX_TRIES; |
||||
u8 ret = 0; |
||||
|
||||
writel(0, DDR_REG_CORE2SEQ); |
||||
|
||||
do { |
||||
ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, |
||||
SEQ2CORE_MASK, 1, 50, 0); |
||||
} while (ret && (--i > 0)); |
||||
|
||||
return !i; |
||||
} |
||||
|
||||
static int emif_reset(void) |
||||
{ |
||||
u32 c2s, s2c; |
||||
|
||||
c2s = readl(DDR_REG_CORE2SEQ); |
||||
s2c = readl(DDR_REG_SEQ2CORE); |
||||
|
||||
debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", |
||||
c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0), |
||||
readl(IO48_MMR_NIOS2_RESERVE1), |
||||
readl(IO48_MMR_NIOS2_RESERVE2), |
||||
readl(IO48_MMR_DRAMSTS)); |
||||
|
||||
if ((s2c & SEQ2CORE_MASK) && emif_clear()) { |
||||
debug("failed emif_clear()\n"); |
||||
return -EPERM; |
||||
} |
||||
|
||||
writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); |
||||
|
||||
if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) { |
||||
debug("emif_reset failed to see interrupt acknowledge\n"); |
||||
return -EPERM; |
||||
} else { |
||||
debug("emif_reset interrupt acknowledged\n"); |
||||
} |
||||
|
||||
if (emif_clear()) { |
||||
debug("emif_clear() failed\n"); |
||||
return -EPERM; |
||||
} |
||||
debug("emif_reset interrupt cleared\n"); |
||||
|
||||
debug("nr0=%08x nr1=%08x nr2=%08x\n", |
||||
readl(IO48_MMR_NIOS2_RESERVE0), |
||||
readl(IO48_MMR_NIOS2_RESERVE1), |
||||
readl(IO48_MMR_NIOS2_RESERVE2)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ddr_setup(void) |
||||
{ |
||||
int i, j, ddr_setup_complete = 0; |
||||
|
||||
/* Try 3 times to do a calibration */ |
||||
for (i = 0; (i < 3) && !ddr_setup_complete; i++) { |
||||
WATCHDOG_RESET(); |
||||
|
||||
/* A delay to wait for calibration bit to set */ |
||||
for (j = 0; (j < 10) && !ddr_setup_complete; j++) { |
||||
mdelay(500); |
||||
ddr_setup_complete = is_sdram_cal_success(); |
||||
} |
||||
|
||||
if (!ddr_setup_complete) |
||||
if (emif_reset()) |
||||
puts("Error: Failed to reset EMIF\n"); |
||||
} |
||||
|
||||
/* After 3 times trying calibration */ |
||||
if (!ddr_setup_complete) { |
||||
puts("Error: Could Not Calibrate SDRAM\n"); |
||||
return -EPERM; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Function to startup the SDRAM*/ |
||||
static int sdram_startup(void) |
||||
{ |
||||
/* Release NOC ddr scheduler from reset */ |
||||
socfpga_reset_deassert_noc_ddr_scheduler(); |
||||
|
||||
/* Bringup the DDR (calibration and configuration) */ |
||||
return ddr_setup(); |
||||
} |
||||
|
||||
static u64 sdram_size_calc(void) |
||||
{ |
||||
u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); |
||||
|
||||
u64 size = BIT(((dramaddrw & |
||||
IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >> |
||||
IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) + |
||||
((dramaddrw & |
||||
IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> |
||||
IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) + |
||||
((dramaddrw & |
||||
IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> |
||||
IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + |
||||
((dramaddrw & |
||||
IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> |
||||
IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) + |
||||
(dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK)); |
||||
|
||||
size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) & |
||||
ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK)); |
||||
|
||||
debug("SDRAM size=%llu", size); |
||||
|
||||
return size; |
||||
} |
||||
|
||||
/* Function to initialize SDRAM MMR and NOC DDR scheduler*/ |
||||
static void sdram_mmr_init(void) |
||||
{ |
||||
u32 update_value, io48_value; |
||||
u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0); |
||||
u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1); |
||||
u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); |
||||
u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0); |
||||
u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1); |
||||
u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2); |
||||
u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3); |
||||
u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4); |
||||
u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9); |
||||
u32 ddrioctl; |
||||
|
||||
/*
|
||||
* Configure the DDR IO size [0xFFCFB008] |
||||
* niosreserve0: Used to indicate DDR width & |
||||
* bit[7:0] = Number of data bits (0x20 for 32bit) |
||||
* bit[8] = 1 if user-mode OCT is present |
||||
* bit[9] = 1 if warm reset compiled into EMIF Cal Code |
||||
* bit[10] = 1 if warm reset is on during generation in EMIF Cal |
||||
* niosreserve1: IP ADCDS version encoded as 16 bit value |
||||
* bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, |
||||
* 3=EAP, 4-6 are reserved) |
||||
* bit[5:3] = Service Pack # (e.g. 1) |
||||
* bit[9:6] = Minor Release # |
||||
* bit[14:10] = Major Release # |
||||
*/ |
||||
if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) { |
||||
update_value = readl(&socfpga_io48_mmr_base->niosreserve0); |
||||
writel(((update_value & 0xFF) >> 5), |
||||
&socfpga_ecc_hmc_base->ddrioctrl); |
||||
} |
||||
|
||||
ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl); |
||||
|
||||
/* Set the DDR Configuration [0xFFD12400] */ |
||||
io48_value = ARRIA_DDR_CONFIG( |
||||
((ctrlcfg1 & |
||||
IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >> |
||||
IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT), |
||||
((dramaddrw & |
||||
IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> |
||||
IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + |
||||
((dramaddrw & |
||||
IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> |
||||
IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT), |
||||
(dramaddrw & |
||||
IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK), |
||||
((dramaddrw & |
||||
IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> |
||||
IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT)); |
||||
|
||||
update_value = match_ddr_conf(io48_value); |
||||
if (update_value) |
||||
writel(update_value, |
||||
&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf); |
||||
|
||||
/*
|
||||
* Configure DDR timing [0xFFD1240C] |
||||
* RDTOMISS = tRTP + tRP + tRCD - BL/2 |
||||
* WRTOMISS = WL + tWR + tRP + tRCD and |
||||
* WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... |
||||
* First part of equation is in memory clock units so divide by 2 |
||||
* for HMC clock units. 1066MHz is close to 1ns so use 15 directly. |
||||
* WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD |
||||
*/ |
||||
u32 ctrlcfg0_cfg_ctrl_burst_len = |
||||
(ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >> |
||||
IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT; |
||||
|
||||
u32 caltim0_cfg_act_to_rdwr = caltim0 & |
||||
IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK; |
||||
|
||||
u32 caltim0_cfg_act_to_act = |
||||
(caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >> |
||||
IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT; |
||||
|
||||
u32 caltim0_cfg_act_to_act_db = |
||||
(caltim0 & |
||||
IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >> |
||||
IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT; |
||||
|
||||
u32 caltim1_cfg_rd_to_wr = |
||||
(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >> |
||||
IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT; |
||||
|
||||
u32 caltim1_cfg_rd_to_rd_dc = |
||||
(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >> |
||||
IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT; |
||||
|
||||
u32 caltim1_cfg_rd_to_wr_dc = |
||||
(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >> |
||||
IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT; |
||||
|
||||
u32 caltim2_cfg_rd_to_pch = |
||||
(caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >> |
||||
IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT; |
||||
|
||||
u32 caltim3_cfg_wr_to_rd = |
||||
(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >> |
||||
IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT; |
||||
|
||||
u32 caltim3_cfg_wr_to_rd_dc = |
||||
(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >> |
||||
IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT; |
||||
|
||||
u32 caltim4_cfg_pch_to_valid = |
||||
(caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >> |
||||
IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT; |
||||
|
||||
u32 caltim9_cfg_4_act_to_act = caltim9 & |
||||
IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK; |
||||
|
||||
update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid + |
||||
caltim0_cfg_act_to_rdwr - |
||||
(ctrlcfg0_cfg_ctrl_burst_len >> 2)); |
||||
|
||||
io48_value = ((((socfpga_io48_mmr_base->dramtiming0 & |
||||
ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 + |
||||
(ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) - |
||||
/* Up to here was in memory cycles so divide by 2 */ |
||||
caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr + |
||||
caltim4_cfg_pch_to_valid); |
||||
|
||||
writel(((caltim0_cfg_act_to_act << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) | |
||||
(update_value << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) | |
||||
(io48_value << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) | |
||||
((ctrlcfg0_cfg_ctrl_burst_len >> 2) << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) | |
||||
(caltim1_cfg_rd_to_wr << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) | |
||||
(caltim3_cfg_wr_to_rd << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) | |
||||
(((ddrioctl == 1) ? 1 : 0) << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)), |
||||
&socfpga_noc_ddr_scheduler_base-> |
||||
ddr_t_main_scheduler_ddrtiming); |
||||
|
||||
/* Configure DDR mode [0xFFD12410] [precharge = 0] */ |
||||
writel(((ddrioctl ? 0 : 1) << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB), |
||||
&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode); |
||||
|
||||
/* Configure the read latency [0xFFD12414] */ |
||||
writel(((socfpga_io48_mmr_base->dramtiming0 & |
||||
ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) + |
||||
DDR_READ_LATENCY_DELAY, |
||||
&socfpga_noc_ddr_scheduler_base-> |
||||
ddr_t_main_scheduler_readlatency); |
||||
|
||||
/*
|
||||
* Configuring timing values concerning activate commands |
||||
* [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR] |
||||
*/ |
||||
writel(((caltim0_cfg_act_to_act_db << |
||||
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) | |
||||
(caltim9_cfg_4_act_to_act << |
||||
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) | |
||||
(ARRIA10_SDR_ACTIVATE_FAWBANK << |
||||
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)), |
||||
&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate); |
||||
|
||||
/*
|
||||
* Configuring timing values concerning device to device data bus |
||||
* ownership change [0xFFD1243C] |
||||
*/ |
||||
writel(((caltim1_cfg_rd_to_rd_dc << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) | |
||||
(caltim1_cfg_rd_to_wr_dc << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) | |
||||
(caltim3_cfg_wr_to_rd_dc << |
||||
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)), |
||||
&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev); |
||||
|
||||
/* Enable or disable the SDRAM ECC */ |
||||
if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) { |
||||
setbits_le32(&socfpga_ecc_hmc_base->eccctrl, |
||||
(ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); |
||||
clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, |
||||
(ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK)); |
||||
setbits_le32(&socfpga_ecc_hmc_base->eccctrl2, |
||||
(ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); |
||||
} else { |
||||
clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, |
||||
(ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); |
||||
clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2, |
||||
(ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | |
||||
ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); |
||||
} |
||||
} |
||||
|
||||
struct firewall_entry { |
||||
const char *prop_name; |
||||
const u32 cfg_addr; |
||||
const u32 en_addr; |
||||
const u32 en_bit; |
||||
}; |
||||
#define FW_MPU_FPGA_ADDRESS \ |
||||
((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
|
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS) |
||||
|
||||
#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \ |
||||
(SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
|
||||
offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR)) |
||||
|
||||
#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \ |
||||
(SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
|
||||
offsetof(struct socfpga_noc_fw_ddr_l3, ADDR)) |
||||
|
||||
const struct firewall_entry firewall_table[] = { |
||||
{ |
||||
"mpu0", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"mpu1", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"mpu2", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"mpu3", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-0", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-1", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-2", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-3", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-4", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-5", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-6", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK |
||||
}, |
||||
{ |
||||
"l3-7", |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr), |
||||
SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram0-0", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram0region0addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram0-1", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram0region1addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram0-2", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram0region2addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram0-3", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram0region3addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram1-0", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram1region0addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram1-1", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram1region1addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram1-2", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram1region2addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram1-3", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram1region3addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram2-0", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram2region0addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram2-1", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram2region1addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram2-2", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram2region2addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK |
||||
}, |
||||
{ |
||||
"fpga2sdram2-3", |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET |
||||
(fpga2sdram2region3addr), |
||||
SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), |
||||
ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK |
||||
}, |
||||
|
||||
}; |
||||
|
||||
static int of_sdram_firewall_setup(const void *blob) |
||||
{ |
||||
int child, i, node, ret; |
||||
u32 start_end[2]; |
||||
char name[32]; |
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC); |
||||
if (node < 0) |
||||
return -ENXIO; |
||||
|
||||
child = fdt_first_subnode(blob, node); |
||||
if (child < 0) |
||||
return -ENXIO; |
||||
|
||||
/* set to default state */ |
||||
writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable); |
||||
writel(0, &socfpga_noc_fw_ddr_l3_base->enable); |
||||
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(firewall_table); i++) { |
||||
sprintf(name, "%s", firewall_table[i].prop_name); |
||||
ret = fdtdec_get_int_array(blob, child, name, |
||||
start_end, 2); |
||||
if (ret) { |
||||
sprintf(name, "altr,%s", firewall_table[i].prop_name); |
||||
ret = fdtdec_get_int_array(blob, child, name, |
||||
start_end, 2); |
||||
if (ret) |
||||
continue; |
||||
} |
||||
|
||||
writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) | |
||||
(start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB), |
||||
firewall_table[i].cfg_addr); |
||||
setbits_le32(firewall_table[i].en_addr, |
||||
firewall_table[i].en_bit); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int ddr_calibration_sequence(void) |
||||
{ |
||||
WATCHDOG_RESET(); |
||||
|
||||
/* Check to see if SDRAM cal was success */ |
||||
if (sdram_startup()) { |
||||
puts("DDRCAL: Failed\n"); |
||||
return -EPERM; |
||||
} |
||||
|
||||
puts("DDRCAL: Success\n"); |
||||
|
||||
WATCHDOG_RESET(); |
||||
|
||||
/* initialize the MMR register */ |
||||
sdram_mmr_init(); |
||||
|
||||
/* assigning the SDRAM size */ |
||||
u64 size = sdram_size_calc(); |
||||
|
||||
/*
|
||||
* If size is less than zero, this is invalid/weird value from |
||||
* calculation, use default Config size. |
||||
* Up to 2GB is supported, 2GB would be used if more than that. |
||||
*/ |
||||
if (size <= 0) |
||||
gd->ram_size = PHYS_SDRAM_1_SIZE; |
||||
else if (DDR_SIZE_2GB_HEX <= size) |
||||
gd->ram_size = DDR_SIZE_2GB_HEX; |
||||
else |
||||
gd->ram_size = (u32)size; |
||||
|
||||
/* setup the dram info within bd */ |
||||
dram_init_banksize(); |
||||
|
||||
if (of_sdram_firewall_setup(gd->fdt_blob)) |
||||
puts("FW: Error Configuring Firewall\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void dram_bank_mmu_setup(int bank) |
||||
{ |
||||
bd_t *bd = gd->bd; |
||||
int i; |
||||
|
||||
debug("%s: bank: %d\n", __func__, bank); |
||||
for (i = bd->bi_dram[bank].start >> 20; |
||||
i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; |
||||
i++) { |
||||
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
||||
set_section_dcache(i, DCACHE_WRITETHROUGH); |
||||
#else |
||||
set_section_dcache(i, DCACHE_WRITEBACK); |
||||
#endif |
||||
} |
||||
|
||||
/* same as above but just that we would want cacheable for ocram too */ |
||||
i = CONFIG_SYS_INIT_RAM_ADDR >> 20; |
||||
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
||||
set_section_dcache(i, DCACHE_WRITETHROUGH); |
||||
#else |
||||
set_section_dcache(i, DCACHE_WRITEBACK); |
||||
#endif |
||||
} |
||||
Loading…
Reference in new issue