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Merge branch 'master' of git://www.denx.de/git/u-boot

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master
Shinya Kuribayashi 18 years ago
parent bed8ce838a f188896c2f
commit 922ff465cc
24 changed files with 1575 additions and 12 deletions
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  1. 4
      MAINTAINERS
  2. 5
      MAKEALL
  3. 8
      Makefile
  4. 51
      board/ms7720se/Makefile
  5. 34
      board/ms7720se/config.mk
  6. 268
      board/ms7720se/lowlevel_init.S
  7. 60
      board/ms7720se/ms7720se.c
  8. 108
      board/ms7720se/u-boot.lds
  9. 49
      cpu/sh3/Makefile
  10. 112
      cpu/sh3/cache.c
  11. 31
      cpu/sh3/config.mk
  12. 84
      cpu/sh3/cpu.c
  13. 42
      cpu/sh3/interrupts.c
  14. 77
      cpu/sh3/start.S
  15. 103
      cpu/sh3/time.c
  16. 33
      cpu/sh3/watchdog.c
  17. 6
      drivers/pcmcia/marubun_pcmcia.c
  18. 36
      drivers/serial/serial_sh.c
  19. 42
      include/asm-sh/cpu_sh3.h
  20. 64
      include/asm-sh/cpu_sh7710.h
  21. 207
      include/asm-sh/cpu_sh7720.h
  22. 27
      include/asm-sh/io.h
  23. 134
      include/configs/ms7720se.h
  24. 2
      include/mpc512x.h

4
MAINTAINERS
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@ -684,6 +684,10 @@ Nobuhiro Iwmaatsu <iwamatsu@nigauri.org>
MS7750SE SH7750
MS7722SE SH7722
Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
MS7720SE SH7720
#########################################################################
# End of MAINTAINERS list #
#########################################################################

5
MAKEALL
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@ -686,8 +686,9 @@ LIST_sh4=" \
ms7722se \
"
LIST_sh3=""
LIST_sh3=" \
ms7720se \
"
LIST_sh=" \
${LIST_sh3} \

8
Makefile
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@ -2762,6 +2762,14 @@ atstk1004_config : unconfig
#########################################################################
#########################################################################
## sh3 (Renesas SuperH)
#########################################################################
ms7720se_config: unconfig
@ >include/config.h
@echo "#define CONFIG_MS7720SE 1" >> include/config.h
@./mkconfig -a $(@:_config=) sh sh3 ms7720se
#########################################################################
## sh4 (Renesas SuperH)
#########################################################################
ms7750se_config: unconfig

51
board/ms7720se/Makefile
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@ -0,0 +1,51 @@
#
# Copyright (C) 2007
# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
#
# Copyright (C) 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# Copyright (C) 2007
# Kenati Technologies, Inc.
#
# board/ms7720se/Makefile
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := ms7720se.o
SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

34
board/ms7720se/config.mk
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@ -0,0 +1,34 @@
#
# Copyright (C) 2007
# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
#
# Copyright (C) 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# Copyright (C) 2007
# Kenati Technologies, Inc.
#
# board/ms7720se/config.mk
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
TEXT_BASE = 0x8FFC0000

268
board/ms7720se/lowlevel_init.S
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@ -0,0 +1,268 @@
/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
.global lowlevel_init
.text
.align 2
lowlevel_init:
mov.l WTCSR_A,r1
mov.l WTCSR_D,r0
mov.w r0,@r1
mov.l WTCNT_A,r1
mov.l WTCNT_D,r0
mov.w r0,@r1
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.w r0,@r1
mov.l UCLKCR_A,r1
mov.l UCLKCR_D,r0
mov.w r0,@r1
mov.l CMNCR_A, r1
mov.l CMNCR_D, r0
mov.l r0, @r1
mov.l CS0BCR_A, r1
mov.l CS0BCR_D, r0
mov.l r0, @r1
mov.l CS2BCR_A, r1
mov.l CS2BCR_D, r0
mov.l r0, @r1
mov.l CS3BCR_A, r1
mov.l CS3BCR_D, r0
mov.l r0, @r1
mov.l CS4BCR_A, r1
mov.l CS4BCR_D, r0
mov.l r0, @r1
mov.l CS5ABCR_A, r1
mov.l CS5ABCR_D, r0
mov.l r0, @r1
mov.l CS5BBCR_A, r1
mov.l CS5BBCR_D, r0
mov.l r0, @r1
mov.l CS6ABCR_A, r1
mov.l CS6ABCR_D, r0
mov.l r0, @r1
mov.l CS6BBCR_A, r1
mov.l CS6BBCR_D, r0
mov.l r0, @r1
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
mov.l CS2WCR_A, r1
mov.l CS2WCR_D, r0
mov.l r0, @r1
mov.l CS3WCR_A, r1
mov.l CS3WCR_D, r0
mov.l r0, @r1
mov.l CS4WCR_A, r1
mov.l CS4WCR_D, r0
mov.l r0, @r1
mov.l CS5AWCR_A, r1
mov.l CS5AWCR_D, r0
mov.l r0, @r1
mov.l CS5BWCR_A, r1
mov.l CS5BWCR_D, r0
mov.l r0, @r1
mov.l CS6AWCR_A, r1
mov.l CS6AWCR_D, r0
mov.l r0, @r1
mov.l CS6BWCR_A, r1
mov.l CS6BWCR_D, r0
mov.l r0, @r1
mov.l SDCR_A, r1
mov.l SDCR_D1, r0
mov.l r0, @r1
mov.l RTCSR_A, r1
mov.l RTCSR_D, r0
mov.l r0, @r1
mov.l RTCNT_A, r1
mov.l RTCNT_D, r0
mov.l r0, @r1
mov.l RTCOR_A, r1
mov.l RTCOR_D, r0
mov.l r0, @r1
mov.l SDCR_A, r1
mov.l SDCR_D2, r0
mov.l r0, @r1
mov.l SDMR3_A, r1
mov.l SDMR3_D, r0
mov.w r0, @r1
mov.l PCCR_A, r1
mov.l PCCR_D, r0
mov.w r0, @r1
mov.l PDCR_A, r1
mov.l PDCR_D, r0
mov.w r0, @r1
mov.l PECR_A, r1
mov.l PECR_D, r0
mov.w r0, @r1
mov.l PGCR_A, r1
mov.l PGCR_D, r0
mov.w r0, @r1
mov.l PHCR_A, r1
mov.l PHCR_D, r0
mov.w r0, @r1
mov.l PPCR_A, r1
mov.l PPCR_D, r0
mov.w r0, @r1
mov.l PTCR_A, r1
mov.l PTCR_D, r0
mov.w r0, @r1
mov.l PVCR_A, r1
mov.l PVCR_D, r0
mov.w r0, @r1
mov.l PSELA_A, r1
mov.l PSELA_D, r0
mov.w r0, @r1
mov.l CCR_A, r1
mov.l CCR_D, r0
mov.l r0, @r1
mov.l LED_A, r1
mov.l LED_D, r0
mov.b r0, @r1
rts
nop
.align 4
FRQCR_A: .long 0xA415FF80 /* FRQCR Address */
WTCNT_A: .long 0xA415FF84
WTCSR_A: .long 0xA415FF86
UCLKCR_A: .long 0xA40A0008
FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */
WTCNT_D: .long 0x5A00
WTCSR_D: .long 0xA506
UCLKCR_D: .long 0xA5C0
#define BSC_BASE 0xA4FD0000
CMNCR_A: .long BSC_BASE
CS0BCR_A: .long BSC_BASE + 0x04
CS2BCR_A: .long BSC_BASE + 0x08
CS3BCR_A: .long BSC_BASE + 0x0C
CS4BCR_A: .long BSC_BASE + 0x10
CS5ABCR_A: .long BSC_BASE + 0x14
CS5BBCR_A: .long BSC_BASE + 0x18
CS6ABCR_A: .long BSC_BASE + 0x1C
CS6BBCR_A: .long BSC_BASE + 0x20
CS0WCR_A: .long BSC_BASE + 0x24
CS2WCR_A: .long BSC_BASE + 0x28
CS3WCR_A: .long BSC_BASE + 0x2C
CS4WCR_A: .long BSC_BASE + 0x30
CS5AWCR_A: .long BSC_BASE + 0x34
CS5BWCR_A: .long BSC_BASE + 0x38
CS6AWCR_A: .long BSC_BASE + 0x3C
CS6BWCR_A: .long BSC_BASE + 0x40
SDCR_A: .long BSC_BASE + 0x44
RTCSR_A: .long BSC_BASE + 0x48
RTCNT_A: .long BSC_BASE + 0x4C
RTCOR_A: .long BSC_BASE + 0x50
SDMR3_A: .long BSC_BASE + 0x58C0
CMNCR_D: .long 0x00000010
CS0BCR_D: .long 0x36DB0400
CS2BCR_D: .long 0x36DB0400
CS3BCR_D: .long 0x36DB4600
CS4BCR_D: .long 0x36DB0400
CS5ABCR_D: .long 0x36DB0400
CS5BBCR_D: .long 0x36DB0200
CS6ABCR_D: .long 0x36DB0400
CS6BBCR_D: .long 0x36DB0400
CS0WCR_D: .long 0x00000B01
CS2WCR_D: .long 0x00000500
CS3WCR_D: .long 0x00006D1B
CS4WCR_D: .long 0x00000500
CS5AWCR_D: .long 0x00000500
CS5BWCR_D: .long 0x00000500
CS6AWCR_D: .long 0x00000500
CS6BWCR_D: .long 0x00000500
SDCR_D1: .long 0x00000011
RTCSR_D: .long 0xA55A0010
RTCNT_D: .long 0xA55A001F
RTCOR_D: .long 0xA55A001F
SDMR3_D: .long 0x0000
SDCR_D2: .long 0x00000811
#define PFC_BASE 0xA4050100
PCCR_A: .long PFC_BASE + 0x04
PDCR_A: .long PFC_BASE + 0x06
PECR_A: .long PFC_BASE + 0x08
PGCR_A: .long PFC_BASE + 0x0C
PHCR_A: .long PFC_BASE + 0x0E
PPCR_A: .long PFC_BASE + 0x18
PTCR_A: .long PFC_BASE + 0x1E
PVCR_A: .long PFC_BASE + 0x22
PSELA_A: .long PFC_BASE + 0x24
PCCR_D: .long 0x0000
PDCR_D: .long 0x0000
PECR_D: .long 0x0000
PGCR_D: .long 0x0000
PHCR_D: .long 0x0000
PPCR_D: .long 0x00AA
PTCR_D: .long 0x0280
PVCR_D: .long 0x0000
PSELA_D: .long 0x0000
CCR_A: .long 0xFFFFFFEC
!CCR_D: .long 0x0000000D
CCR_D: .long 0x0000000B
LED_A: .long 0xB6800000
LED_D: .long 0xFF

60
board/ms7720se/ms7720se.c
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@ -0,0 +1,60 @@
/*
* Copyright (C) 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* Copyright (C) 2007
* Kenati Technologies, Inc.
*
* board/ms7720se/ms7720se.c
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#define LED_BASE 0xB0800000
int checkboard(void)
{
puts("BOARD: Hitachi UL MS7720SE\n");
return 0;
}
int board_init(void)
{
return 0;
}
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
return 0;
}
void led_set_state(unsigned short value)
{
outw(value & 0xFF, LED_BASE);
}

108
board/ms7720se/u-boot.lds
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/*
* Copyrigth (c) 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* Copyrigth (c) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
ENTRY(_start)
SECTIONS
{
/*
Base address of internal SDRAM is 0x0C000000.
Although size of SDRAM can be either 16 or 32 MBytes,
we assume 16 MBytes (ie ignore upper half if the full
32 MBytes is present).
NOTE: This address must match with the definition of
TEXT_BASE in config.mk (in this directory).
*/
. = 0x8C000000 + (64*1024*1024) - (256*1024);
PROVIDE (reloc_dst = .);
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
.text :
{
cpu/sh3/start.o (.text)
. = ALIGN(8192);
common/environment.o (.ppcenv)
. = ALIGN(8192);
common/environment.o (.ppcenvr)
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
} =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(.rodata)
. = ALIGN(4);
}
PROVIDE (_etext = .);
PROVIDE (_fdata = .);
.data :
{
*(.data)
. = ALIGN(4);
}
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
*(.got)
. = ALIGN(4);
}
PROVIDE (_egot = .);
PROVIDE (__u_boot_cmd_start = .);
.u_boot_cmd :
{
*(.u_boot_cmd)
. = ALIGN(4);
}
PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
.bss :
{
*(.bss)
. = ALIGN(4);
}
PROVIDE (bss_end = .);
PROVIDE (_end = .);
}

49
cpu/sh3/Makefile
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# (C) Copyright 2007
# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
OBJS = cpu.o interrupts.o watchdog.o time.o cache.o
all: .depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

112
cpu/sh3/cache.c
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/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* (C) Copyright 2007
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
/*
* Jump to P2 area.
* When handling TLB or caches, we need to do it from P2 area.
*/
#define jump_to_P2() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"or %1, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy) \
: "r" (0x20000000)); \
} while (0)
/*
* Back to P1 area.
*/
#define back_to_P1() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"nop;nop;nop;nop;nop;nop;nop\n\t" \
"mov.l 1f, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy)); \
} while (0)
#define CACHE_VALID 1
#define CACHE_UPDATED 2
static inline void cache_wback_all(void)
{
unsigned long addr, data, i, j;
jump_to_P2();
for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
addr = CACHE_OC_ADDRESS_ARRAY
| (j << CACHE_OC_WAY_SHIFT)
| (i << CACHE_OC_ENTRY_SHIFT);
data = inl(addr);
if (data & CACHE_UPDATED) {
data &= ~CACHE_UPDATED;
outl(data, addr);
}
}
}
back_to_P1();
}
#define CACHE_ENABLE 0
#define CACHE_DISABLE 1
int cache_control(unsigned int cmd)
{
unsigned long ccr;
jump_to_P2();
ccr = inl(CCR);
if (ccr & CCR_CACHE_ENABLE)
cache_wback_all();
if (cmd == CACHE_DISABLE)
outl(CCR_CACHE_STOP, CCR);
else
outl(CCR_CACHE_INIT, CCR);
back_to_P1();
return 0;
}

31
cpu/sh3/config.mk
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#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# (C) Copyright 2007
# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
PLATFORM_CPPFLAGS += -m3
PLATFORM_RELFLAGS += -ffixed-r13

84
cpu/sh3/cpu.c
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@ -0,0 +1,84 @@
/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
int checkcpu(void)
{
puts("CPU: SH3\n");
return 0;
}
int cpu_init(void)
{
return 0;
}
int cleanup_before_linux(void)
{
disable_interrupts();
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
disable_interrupts();
reset_cpu(0);
return 0;
}
void flush_cache(unsigned long addr, unsigned long size)
{
}
void icache_enable(void)
{
}
void icache_disable(void)
{
}
int icache_status(void)
{
return 0;
}
void dcache_enable(void)
{
}
void dcache_disable(void)
{
}
int dcache_status(void)
{
return 0;
}

42
cpu/sh3/interrupts.c
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/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
int interrupt_init(void)
{
return 0;
}
void enable_interrupts(void)
{
}
int disable_interrupts(void)
{
return 0;
}

77
cpu/sh3/start.S
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@ -0,0 +1,77 @@
/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
.text
.align 2
.global _start
_start:
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
bsr 1f
nop
1: sts pr, r5
mov.l ._reloc_dst, r4
add #(_start-1b), r5
mov.l ._reloc_dst_end, r6
2: mov.l @r5+, r1
mov.l r1, @r4
add #4, r4
cmp/hs r6, r4
bf 2b
mov.l ._bss_start, r4
mov.l ._bss_end, r5
mov #0, r1
3: mov.l r1, @r4 /* bss clear */
add #4, r4
cmp/hs r5, r4
bf 3b
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
mov.l ._sh_generic_init, r0
jsr @r0
nop
loop:
bra loop
.align 2
._lowlevel_init: .long (lowlevel_init - (100b + 4))
._reloc_dst: .long reloc_dst
._reloc_dst_end: .long reloc_dst_end
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_start - CFG_GBL_DATA_SIZE)
._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
._sh_generic_init: .long sh_generic_init

103
cpu/sh3/time.c
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@ -0,0 +1,103 @@
/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* (C) Copyright 2007
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#define TMU_MAX_COUNTER (~0UL)
static void tmu_timer_start(unsigned int timer)
{
if (timer > 2)
return;
outb(inb(TSTR) | (1 << timer), TSTR);
}
static void tmu_timer_stop(unsigned int timer)
{
u8 val = inb(TSTR);
if (timer > 2)
return;
outb(val & ~(1 << timer), TSTR);
}
int timer_init(void)
{
/* Divide clock by 4 */
outw(0, TCR0);
tmu_timer_stop(0);
tmu_timer_start(0);
return 0;
}
/*
In theory we should return a true 64bit value (ie something that doesn't
overflow). However, we don't. Therefore if TMU runs at fastest rate of
6.75 MHz this value will wrap after u-boot has been running for approx
10 minutes.
*/
unsigned long long get_ticks(void)
{
return (0 - inl(TCNT0));
}
unsigned long get_timer(unsigned long base)
{
return ((0 - inl(TCNT0)) - base);
}
void set_timer(unsigned long t)
{
outl(0 - t, TCNT0);
}
void reset_timer(void)
{
tmu_timer_stop(0);
set_timer(0);
tmu_timer_start(0);
}
void udelay(unsigned long usec)
{
unsigned int start = get_timer(0);
unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000));
while (get_timer(0) < end)
continue;
}
unsigned long get_tbclk(void)
{
return CFG_HZ;
}

33
cpu/sh3/watchdog.c
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@ -0,0 +1,33 @@
/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
int watchdog_init(void)
{
return 0;
}
void reset_cpu(unsigned long ignored)
{
while (1)
;
}

6
drivers/pcmcia/marubun_pcmcia.c
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@ -25,11 +25,13 @@
#include <pcmcia.h>
#include <asm/io.h>
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE)
#if defined(CONFIG_CMD_IDE)
#define CONFIG_PCMCIA
#endif

36
drivers/serial/serial_sh.c
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@ -30,24 +30,39 @@
#error "Default SCIF doesn't set....."
#endif
#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
/* Base register */
#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
#ifdef CONFIG_SH7720 /* SH7720 specific */
#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
#define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
#define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
#else
#define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
#define SCFSR (vu_short *)(SCIF_BASE + 0x10)
#define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
#endif
#if defined(CONFIG_SH4A)
#define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
#define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
#define SCLSR (vu_short *)(SCIF_BASE + 0x28)
#define SCRER (vu_short *)(SCIF_BASE + 0x2C)
#define LSR_ORER 1
#elif defined (CONFIG_SH4)
#define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
#define LSR_ORER 1
#elif defined (CONFIG_SH3)
#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
#ifdef CONFIG_SH7720 /* SH7720 specific */
# define SCLSR SCFSR /* SCSSR */
#else
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
#endif
#define LSR_ORER 0x0200
#endif
#define SCR_RE (1 << 4)
@ -67,10 +82,18 @@
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CPU_SH7720)
int divisor = gd->baudrate * 16;
*SCBRR = (CONFIG_SYS_CLK_FREQ * 2 + (divisor / 2)) /
(gd->baudrate * 32) - 1;
#else
int divisor = gd->baudrate * 32;
*SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) /
(gd->baudrate * 32) - 1;
#endif
}
int serial_init (void)
@ -133,7 +156,6 @@ int serial_tstc (void)
#define FSR_ERR_CLEAR 0x0063
#define RDRF_CLEAR 0x00fc
#define LSR_ORER 1
void handle_error( void ){
(void)*SCFSR ;

42
include/asm-sh/cpu_sh3.h
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@ -0,0 +1,42 @@
/*
* (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_CPU_SH3_H_
#define _ASM_CPU_SH3_H_
/* cache control */
#define CCR_CACHE_STOP 0x00000008
#define CCR_CACHE_ENABLE 0x00000005
#define CCR_CACHE_ICI 0x00000008
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_WAY_SHIFT 13
#define CACHE_OC_NUM_ENTRIES 256
#define CACHE_OC_ENTRY_SHIFT 4
#if defined(CONFIG_CPU_SH7710)
#include <asm/cpu_sh7710.h>
#elif defined(CONFIG_CPU_SH7720)
#include <asm/cpu_sh7720.h>
#else
#error "Unknown SH3 variant"
#endif
#endif /* _ASM_CPU_SH3_H_ */

64
include/asm-sh/cpu_sh7710.h
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@ -0,0 +1,64 @@
#ifndef _ASM_CPU_SH7710_H_
#define _ASM_CPU_SH7710_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000000D
/* MMU and Cache control */
#define MMUCR 0xFFFFFFE0
#define CCR 0xFFFFFFEC
/* PFC */
#define PACR 0xA4050100
#define PBCR 0xA4050102
#define PCCR 0xA4050104
#define PETCR 0xA4050106
/* Port Data Registers */
#define PADR 0xA4050120
#define PBDR 0xA4050122
#define PCDR 0xA4050124
/* BSC */
#define CMNCR 0xA4FD0000
#define CS0BCR 0xA4FD0004
#define CS2BCR 0xA4FD0008
#define CS3BCR 0xA4FD000C
#define CS4BCR 0xA4FD0010
#define CS5ABCR 0xA4FD0014
#define CS5BBCR 0xA4FD0018
#define CS6ABCR 0xA4FD001C
#define CS6BBCR 0xA4FD0020
#define CS0WCR 0xA4FD0024
#define CS2WCR 0xA4FD0028
#define CS3WCR 0xA4FD002C
#define CS4WCR 0xA4FD0030
#define CS5AWCR 0xA4FD0034
#define CS5BWCR 0xA4FD0038
#define CS6AWCR 0xA4FD003C
#define CS6BWCR 0xA4FD0040
/* SDRAM controller */
#define SDCR 0xA4FD0044
#define RTCSR 0xA4FD0048
#define RTCNT 0xA4FD004C
#define RTCOR 0xA4FD0050
/* SCIF */
#define SCSMR_0 0xA4400000
#define SCIF0_BASE SCSMR_0
#define SCSMR_0 0xA4410000
#define SCIF1_BASE SCSMR_1
/* Timer */
#define TSTR0 0xA412FE92
#define TSTR TSTR0
#define TCNT0 0xa412FE98
#define TCR0 0xa412FE9C
/* On chip oscillator circuits */
#define FRQCR 0xA415FF80
#define WTCNT 0xA415FF84
#define WTCSR 0xA415FF86
#endif /* _ASM_CPU_SH7710_H_ */

207
include/asm-sh/cpu_sh7720.h
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/*
* (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* SH7720 Internal I/O register
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_CPU_SH7720_H_
#define _ASM_CPU_SH7720_H_
#define CACHE_OC_NUM_WAYS 4
#define CCR_CACHE_INIT 0x0000000B
/* EXP */
#define TRA 0xFFFFFFD0
#define EXPEVT 0xFFFFFFD4
#define INTEVT 0xFFFFFFD8
/* MMU */
#define MMUCR 0xFFFFFFE0
#define PTEH 0xFFFFFFF0
#define PTEL 0xFFFFFFF4
#define TTB 0xFFFFFFF8
/* CACHE */
#define CCR 0xFFFFFFEC
/* INTC */
#define IPRF 0xA4080000
#define IPRG 0xA4080002
#define IPRH 0xA4080004
#define IPRI 0xA4080006
#define IPRJ 0xA4080008
#define IRR5 0xA4080020
#define IRR6 0xA4080022
#define IRR7 0xA4080024
#define IRR8 0xA4080026
#define IRR9 0xA4080028
#define IRR0 0xA4140004
#define IRR1 0xA4140006
#define IRR2 0xA4140008
#define IRR3 0xA414000A
#define IRR4 0xA414000C
#define ICR1 0xA4140010
#define ICR2 0xA4140012
#define PINTER 0xA4140014
#define IPRC 0xA4140016
#define IPRD 0xA4140018
#define IPRE 0xA414001A
#define ICR0 0xA414FEE0
#define IPRA 0xA414FEE2
#define IPRB 0xA414FEE4
/* BSC */
#define BSC_BASE 0xA4FD0000
#define CMNCR (BSC_BASE + 0x00)
#define CS0BCR (BSC_BASE + 0x04)
#define CS2BCR (BSC_BASE + 0x08)
#define CS3BCR (BSC_BASE + 0x0C)
#define CS4BCR (BSC_BASE + 0x10)
#define CS5ABCR (BSC_BASE + 0x14)
#define CS5BBCR (BSC_BASE + 0x18)
#define CS6ABCR (BSC_BASE + 0x1C)
#define CS6BBCR (BSC_BASE + 0x20)
#define CS0WCR (BSC_BASE + 0x24)
#define CS2WCR (BSC_BASE + 0x28)
#define CS3WCR (BSC_BASE + 0x2C)
#define CS4WCR (BSC_BASE + 0x30)
#define CS5AWCR (BSC_BASE + 0x34)
#define CS5BWCR (BSC_BASE + 0x38)
#define CS6AWCR (BSC_BASE + 0x3C)
#define CS6BWCR (BSC_BASE + 0x40)
#define SDCR (BSC_BASE + 0x44)
#define RTCSR (BSC_BASE + 0x48)
#define RTCNR (BSC_BASE + 0x4C)
#define RTCOR (BSC_BASE + 0x50)
#define SDMR2 (BSC_BASE + 0x4000)
#define SDMR3 (BSC_BASE + 0x5000)
/* DMAC */
/* CPG */
#define UCLKCR 0xA40A0008
#define FRQCR 0xA415FF80
/* LOW POWER MODE */
/* TMU */
#define TMU_BASE 0xA412FE90
#define TSTR (TMU_BASE + 0x02)
#define TCOR0 (TMU_BASE + 0x04)
#define TCNT0 (TMU_BASE + 0x08)
#define TCR0 (TMU_BASE + 0x0C)
#define TCOR1 (TMU_BASE + 0x10)
#define TCNT1 (TMU_BASE + 0x14)
#define TCR1 (TMU_BASE + 0x18)
#define TCOR2 (TMU_BASE + 0x1C)
#define TCNT2 (TMU_BASE + 0x20)
#define TCR2 (TMU_BASE + 0x24)
/* TPU */
#define TPU_BASE 0xA4480000
#define TPU_TSTR (TPU_BASE + 0x00)
#define TPU_TCR0 (TPU_BASE + 0x10)
#define TPU_TMDR0 (TPU_BASE + 0x14)
#define TPU_TIOR0 (TPU_BASE + 0x18)
#define TPU_TIER0 (TPU_BASE + 0x1C)
#define TPU_TSR0 (TPU_BASE + 0x20)
#define TPU_TCNT0 (TPU_BASE + 0x24)
#define TPU_TGRA0 (TPU_BASE + 0x28)
#define TPU_TGRB0 (TPU_BASE + 0x2C)
#define TPU_TGRC0 (TPU_BASE + 0x30)
#define TPU_TGRD0 (TPU_BASE + 0x34)
#define TPU_TCR1 (TPU_BASE + 0x50)
#define TPU_TMDR1 (TPU_BASE + 0x54)
#define TPU_TIOR1 (TPU_BASE + 0x58)
#define TPU_TIER1 (TPU_BASE + 0x5C)
#define TPU_TSR1 (TPU_BASE + 0x60)
#define TPU_TCNT1 (TPU_BASE + 0x64)
#define TPU_TGRA1 (TPU_BASE + 0x68)
#define TPU_TGRB1 (TPU_BASE + 0x6C)
#define TPU_TGRC1 (TPU_BASE + 0x70)
#define TPU_TGRD1 (TPU_BASE + 0x74)
#define TPU_TCR2 (TPU_BASE + 0x90)
#define TPU_TMDR2 (TPU_BASE + 0x94)
#define TPU_TIOR2 (TPU_BASE + 0x98)
#define TPU_TIER2 (TPU_BASE + 0x9C)
#define TPU_TSR2 (TPU_BASE + 0xB0)
#define TPU_TCNT2 (TPU_BASE + 0xB4)
#define TPU_TGRA2 (TPU_BASE + 0xB8)
#define TPU_TGRB2 (TPU_BASE + 0xBC)
#define TPU_TGRC2 (TPU_BASE + 0xC0)
#define TPU_TGRD2 (TPU_BASE + 0xC4)
#define TPU_TCR3 (TPU_BASE + 0xD0)
#define TPU_TMDR3 (TPU_BASE + 0xD4)
#define TPU_TIOR3 (TPU_BASE + 0xD8)
#define TPU_TIER3 (TPU_BASE + 0xDC)
#define TPU_TSR3 (TPU_BASE + 0xE0)
#define TPU_TCNT3 (TPU_BASE + 0xE4)
#define TPU_TGRA3 (TPU_BASE + 0xE8)
#define TPU_TGRB3 (TPU_BASE + 0xEC)
#define TPU_TGRC3 (TPU_BASE + 0xF0)
#define TPU_TGRD3 (TPU_BASE + 0xF4)
/* CMT */
/* SIOF */
/* SCIF */
#define SCIF0_BASE 0xA4430000
/* SIM */
/* IrDA */
/* IIC */
/* LCDC */
/* USBF */
/* MMCIF */
/* PFC */
#define PFC_BASE 0xA4050100
#define PACR (PFC_BASE + 0x00)
#define PBCR (PFC_BASE + 0x02)
#define PCCR (PFC_BASE + 0x04)
#define PDCR (PFC_BASE + 0x06)
#define PECR (PFC_BASE + 0x08)
#define PFCR (PFC_BASE + 0x0A)
#define PGCR (PFC_BASE + 0x0C)
#define PHCR (PFC_BASE + 0x0E)
#define PJCR (PFC_BASE + 0x10)
#define PKCR (PFC_BASE + 0x12)
#define PLCR (PFC_BASE + 0x14)
#define PMCR (PFC_BASE + 0x16)
#define PPCR (PFC_BASE + 0x18)
#define PRCR (PFC_BASE + 0x1A)
#define PSCR (PFC_BASE + 0x1C)
#define PTCR (PFC_BASE + 0x1E)
#define PUCR (PFC_BASE + 0x20)
#define PVCR (PFC_BASE + 0x22)
#define PSELA (PFC_BASE + 0x24)
#define PSELB (PFC_BASE + 0x26)
#define PSELC (PFC_BASE + 0x28)
#define PSELD (PFC_BASE + 0x2A)
/* I/O Port */
/* H-UDI */
#endif /* _ASM_CPU_SH7720_H_ */

27
include/asm-sh/io.h
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@ -227,5 +227,32 @@ out:
static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
#endif /* __KERNEL__ */
#endif /* __ASM_SH_IO_H */

134
include/configs/ms7720se.h
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@ -0,0 +1,134 @@
/*
* Configuation settings for the Hitachi Solution Engine 7720
*
* Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MS7720SE_H
#define __MS7720SE_H
#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH3 1
#define CONFIG_CPU_SH7720 1
#define CONFIG_MS7720SE 1
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CFG_CMD_PCMCIA 0x01
#define CFG_CMD_IDE 0x02
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_IDE|CFG_CMD_PCMCIA) & \
~(CFG_CMD_FPGA))
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_BOOTFILE /boot/zImage
#define CONFIG_LOADADDR 0x8E000000
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define MS7720SE_SDRAM_BASE 0x8C000000
#define MS7720SE_FLASH_BASE_1 0xA0000000
#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
#define CFG_PBSIZE 256 /* Buffer size for Console output */
#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
/* Buffer size for Boot Arguments passed to kernel */
#define CFG_BARGSIZE 512
/* List of legal baudrate settings for this board */
#define CFG_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CFG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CFG_MEMTEST_START MS7720SE_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
#define CFG_SDRAM_BASE MS7720SE_SDRAM_BASE
#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
#define CFG_MONITOR_BASE MS7720SE_FLASH_BASE_1
#define CFG_MONITOR_LEN (128 * 1024)
#define CFG_MALLOC_LEN (256 * 1024)
#define CFG_GBL_DATA_SIZE 256
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_BASE MS7720SE_FLASH_BASE_1
#define CFG_MAX_FLASH_SECT 150
#define CFG_MAX_FLASH_BANKS 1
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE (64 * 1024)
#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_FLASH_ERASE_TOUT 120000
#define CFG_FLASH_WRITE_TOUT 500
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
/* PCMCIA */
#define CONFIG_IDE_PCMCIA 1
#define CONFIG_MARUBUN_PCCARD 1
#define CONFIG_PCMCIA_SLOT_A 1
#define CFG_IDE_MAXDEVICE 1
#define CFG_MARUBUN_MRSHPC 0xb83fffe0
#define CFG_MARUBUN_MW1 0xb8400000
#define CFG_MARUBUN_MW2 0xb8500000
#define CFG_MARUBUN_IO 0xb8600000
#define CFG_PIO_MODE 1
#define CFG_IDE_MAXBUS 1
#define CONFIG_DOS_PARTITION 1
#define CFG_ATA_BASE_ADDR CFG_MARUBUN_IO /* base address */
#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
#define CFG_ATA_REG_OFFSET 0 /* reg offset */
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
#endif /* __MS7720SE_H */

2
include/mpc512x.h
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@ -185,7 +185,7 @@
/* SCFR1 System Clock Frequency Register 1
*/
#define SCFR1_IPS_DIV 0x2
#define SCFR1_IPS_DIV 0x4
#define SCFR1_IPS_DIV_MASK 0x03800000
#define SCFR1_IPS_DIV_SHIFT 23

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