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@ -392,10 +392,23 @@ |
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#endif /* CONFIG_SPC1920_HPI_TEST */ |
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/*
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* Ramtron FM18L08 FRAM 32KB on CS4 |
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*/ |
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#define CFG_SPC1920_FRAM_BASE 0x80100000 |
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#define CFG_PRELIM_OR4_AM 0xffff8000 |
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#define CFG_OR4_PRELIM (CFG_PRELIM_OR4_AM | \ |
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OR_ACS_DIV2 | \
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OR_BI | \
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OR_SCY_4_CLK | \
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OR_TRLX) |
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#define CFG_BR4_PRELIM ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); |
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/*
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* PLD CS5 |
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*/ |
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#define CFG_SPC1920_PLD_BASE 0x80000000 |
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#define CFG_PRELIM_OR5_AM 0xfff00000 |
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#define CFG_PRELIM_OR5_AM 0xffff8000 |
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#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \ |
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OR_CSNT_SAM | \
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