This patch modifies the omap24xx driver so that it will also work with OMAP4. Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>master
Steve Sakoman
15 years ago
committed by
Sandeep Paulraj
parent
bec3dc7599
commit
938717cee1
@ -0,0 +1,74 @@ |
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/*
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* (C) Copyright 2004-2010 |
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* Texas Instruments, <www.ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _OMAP4_I2C_H_ |
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#define _OMAP4_I2C_H_ |
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#define I2C_BUS_MAX 3 |
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#define I2C_DEFAULT_BASE I2C_BASE1 |
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struct i2c { |
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unsigned short revnb_lo; /* 0x00 */ |
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unsigned short res1; |
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unsigned short revnb_hi; /* 0x04 */ |
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unsigned short res2[13]; |
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unsigned short sysc; /* 0x20 */ |
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unsigned short res3; |
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unsigned short irqstatus_raw; /* 0x24 */ |
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unsigned short res4; |
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unsigned short stat; /* 0x28 */ |
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unsigned short res5; |
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unsigned short ie; /* 0x2C */ |
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unsigned short res6; |
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unsigned short irqenable_clr; /* 0x30 */ |
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unsigned short res7; |
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unsigned short iv; /* 0x34 */ |
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unsigned short res8[45]; |
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unsigned short syss; /* 0x90 */ |
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unsigned short res9; |
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unsigned short buf; /* 0x94 */ |
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unsigned short res10; |
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unsigned short cnt; /* 0x98 */ |
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unsigned short res11; |
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unsigned short data; /* 0x9C */ |
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unsigned short res13; |
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unsigned short res14; /* 0xA0 */ |
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unsigned short res15; |
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unsigned short con; /* 0xA4 */ |
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unsigned short res16; |
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unsigned short oa; /* 0xA8 */ |
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unsigned short res17; |
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unsigned short sa; /* 0xAC */ |
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unsigned short res18; |
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unsigned short psc; /* 0xB0 */ |
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unsigned short res19; |
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unsigned short scll; /* 0xB4 */ |
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unsigned short res20; |
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unsigned short sclh; /* 0xB8 */ |
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unsigned short res21; |
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unsigned short systest; /* 0xBC */ |
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unsigned short res22; |
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unsigned short bufstat; /* 0xC0 */ |
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unsigned short res23; |
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}; |
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#endif /* _OMAP4_I2C_H_ */ |
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@ -0,0 +1,166 @@ |
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/*
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* (C) Copyright 2004-2010 |
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* Texas Instruments, <www.ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _OMAP24XX_I2C_H_ |
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#define _OMAP24XX_I2C_H_ |
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/* I2C masks */ |
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/* I2C Interrupt Enable Register (I2C_IE): */ |
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#define I2C_IE_GC_IE (1 << 5) |
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#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ |
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#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ |
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#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ |
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#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ |
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#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ |
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/* I2C Status Register (I2C_STAT): */ |
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#define I2C_STAT_SBD (1 << 15) /* Single byte data */ |
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#define I2C_STAT_BB (1 << 12) /* Bus busy */ |
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#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ |
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#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ |
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#define I2C_STAT_AAS (1 << 9) /* Address as slave */ |
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#define I2C_STAT_GC (1 << 5) |
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#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ |
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#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ |
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#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ |
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#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ |
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#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ |
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/* I2C Interrupt Code Register (I2C_INTCODE): */ |
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#define I2C_INTCODE_MASK 7 |
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#define I2C_INTCODE_NONE 0 |
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#define I2C_INTCODE_AL 1 /* Arbitration lost */ |
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#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ |
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#define I2C_INTCODE_ARDY 3 /* Register access ready */ |
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#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ |
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#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ |
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/* I2C Buffer Configuration Register (I2C_BUF): */ |
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#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ |
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#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ |
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/* I2C Configuration Register (I2C_CON): */ |
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#define I2C_CON_EN (1 << 15) /* I2C module enable */ |
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#define I2C_CON_BE (1 << 14) /* Big endian mode */ |
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#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ |
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#define I2C_CON_MST (1 << 10) /* Master/slave mode */ |
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#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ |
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/* (master mode only) */ |
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#define I2C_CON_XA (1 << 8) /* Expand address */ |
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#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ |
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#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ |
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/* I2C System Test Register (I2C_SYSTEST): */ |
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#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ |
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#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ |
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#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ |
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#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ |
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#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ |
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#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ |
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#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ |
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#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ |
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#define I2C_SCLL_SCLL 0 |
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#define I2C_SCLL_SCLL_M 0xFF |
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#define I2C_SCLL_HSSCLL 8 |
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#define I2C_SCLH_HSSCLL_M 0xFF |
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#define I2C_SCLH_SCLH 0 |
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#define I2C_SCLH_SCLH_M 0xFF |
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#define I2C_SCLH_HSSCLH 8 |
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#define I2C_SCLH_HSSCLH_M 0xFF |
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#define OMAP_I2C_STANDARD 100000 |
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#define OMAP_I2C_FAST_MODE 400000 |
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#define OMAP_I2C_HIGH_SPEED 3400000 |
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#define SYSTEM_CLOCK_12 12000000 |
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#define SYSTEM_CLOCK_13 13000000 |
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#define SYSTEM_CLOCK_192 19200000 |
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#define SYSTEM_CLOCK_96 96000000 |
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/* Use the reference value of 96MHz if not explicitly set by the board */ |
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#ifndef I2C_IP_CLK |
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#define I2C_IP_CLK SYSTEM_CLOCK_96 |
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#endif |
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/*
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* The reference minimum clock for high speed is 19.2MHz. |
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* The linux 2.6.30 kernel uses this value. |
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* The reference minimum clock for fast mode is 9.6MHz |
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* The reference minimum clock for standard mode is 4MHz |
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* In TRM, the value of 12MHz is used. |
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*/ |
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#ifndef I2C_INTERNAL_SAMPLING_CLK |
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#define I2C_INTERNAL_SAMPLING_CLK 19200000 |
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#endif |
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/*
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* The equation for the low and high time is |
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* tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed |
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* thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed |
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* |
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* If the duty cycle is 50% |
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* |
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* tlow = scll + scll_trim = sampling clock / (2 * speed) |
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* thigh = sclh + sclh_trim = sampling clock / (2 * speed) |
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* |
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* In TRM |
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* scll_trim = 7 |
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* sclh_trim = 5 |
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* |
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* The linux 2.6.30 kernel uses |
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* scll_trim = 6 |
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* sclh_trim = 6 |
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* |
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* These are the trim values for standard and fast speed |
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*/ |
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#ifndef I2C_FASTSPEED_SCLL_TRIM |
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#define I2C_FASTSPEED_SCLL_TRIM 6 |
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#endif |
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#ifndef I2C_FASTSPEED_SCLH_TRIM |
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#define I2C_FASTSPEED_SCLH_TRIM 6 |
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#endif |
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/* These are the trim values for high speed */ |
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#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM |
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#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM |
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#endif |
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#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM |
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#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM |
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#endif |
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#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM |
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#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM |
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#endif |
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#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM |
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#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM |
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#endif |
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#define I2C_PSC_MAX 0x0f |
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#define I2C_PSC_MIN 0x00 |
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#endif /* _OMAP24XX_I2C_H_ */ |
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