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ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RAT

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The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits
instead of 4.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
master
James Yang 15 years ago committed by Kumar Gala
parent 2903ad33a7
commit 93cedc7164
1 changed files with 2 additions and 2 deletions
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  1. 4
      cpu/mpc85xx/speed.c

4
cpu/mpc85xx/speed.c
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@ -80,8 +80,8 @@ void get_sys_info (sys_info_t * sysInfo)
freqCC_PLL[2] = sysclk;
freqCC_PLL[3] = sysclk;
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;

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