Tom Rini
10 years ago
commit
98d2d5e8c4
@ -0,0 +1,12 @@ |
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if TARGET_BEAGLE_X15 |
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config SYS_BOARD |
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default "beagle_x15" |
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config SYS_VENDOR |
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default "ti" |
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config SYS_CONFIG_NAME |
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default "beagle_x15" |
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endif |
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@ -0,0 +1,8 @@ |
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#
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# (C) Copyright 2014
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# Texas Instruments, <www.ti.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := board.o
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@ -0,0 +1,395 @@ |
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
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* |
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* Author: Felipe Balbi <balbi@ti.com> |
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* |
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* Based on board/ti/dra7xx/evm.c |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <palmas.h> |
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#include <sata.h> |
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#include <usb.h> |
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#include <asm/omap_common.h> |
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#include <asm/emif.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/mmc_host_def.h> |
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#include <asm/arch/sata.h> |
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#include <asm/arch/gpio.h> |
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#include <environment.h> |
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#include "mux_data.h" |
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#ifdef CONFIG_DRIVER_TI_CPSW |
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#include <cpsw.h> |
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#endif |
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DECLARE_GLOBAL_DATA_PTR; |
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const struct omap_sysinfo sysinfo = { |
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"Board: BeagleBoard x15\n" |
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}; |
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static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { |
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.dmm_lisa_map_3 = 0x80740300, |
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.is_ma_present = 0x1 |
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}; |
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) |
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{ |
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*dmm_lisa_regs = &beagle_x15_lisa_regs; |
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} |
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static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { |
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.sdram_config_init = 0x61851b32, |
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.sdram_config = 0x61851b32, |
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.sdram_config2 = 0x00000000, |
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.ref_ctrl = 0x00001035, |
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.sdram_tim1 = 0xceef266b, |
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.sdram_tim2 = 0x328f7fda, |
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.sdram_tim3 = 0x027f88a8, |
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.read_idle_ctrl = 0x00050001, |
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.zq_config = 0x0007190b, |
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.temp_alert_config = 0x00000000, |
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.emif_ddr_phy_ctlr_1_init = 0x0e24400a, |
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.emif_ddr_phy_ctlr_1 = 0x0e24400a, |
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100, |
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.emif_ddr_ext_phy_ctrl_2 = 0x00740074, |
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.emif_ddr_ext_phy_ctrl_3 = 0x00780078, |
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.emif_ddr_ext_phy_ctrl_4 = 0x007c007c, |
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.emif_ddr_ext_phy_ctrl_5 = 0x007b007b, |
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.emif_rd_wr_lvl_rmp_win = 0x00000000, |
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000, |
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.emif_rd_wr_lvl_ctl = 0x00000000, |
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.emif_rd_wr_exec_thresh = 0x00000305 |
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}; |
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static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { |
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0x00800080, |
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0x00360036, |
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0x00340034, |
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0x00360036, |
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0x00350035, |
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0x00350035, |
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0x01ff01ff, |
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0x01ff01ff, |
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0x01ff01ff, |
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0x01ff01ff, |
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0x01ff01ff, |
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0x00430043, |
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0x003e003e, |
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0x004a004a, |
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0x00470047, |
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0x00400040, |
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0x00000000, |
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0x00600020, |
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0x40010080, |
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0x08102040, |
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0x00400040, |
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0x00400040, |
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0x00400040, |
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0x00400040, |
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0x00400040 |
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}; |
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static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { |
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.sdram_config_init = 0x61851b32, |
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.sdram_config = 0x61851b32, |
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.sdram_config2 = 0x00000000, |
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.ref_ctrl = 0x00001035, |
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.sdram_tim1 = 0xceef266b, |
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.sdram_tim2 = 0x328f7fda, |
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.sdram_tim3 = 0x027f88a8, |
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.read_idle_ctrl = 0x00050001, |
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.zq_config = 0x0007190b, |
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.temp_alert_config = 0x00000000, |
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.emif_ddr_phy_ctlr_1_init = 0x0e24400a, |
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.emif_ddr_phy_ctlr_1 = 0x0e24400a, |
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100, |
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.emif_ddr_ext_phy_ctrl_2 = 0x00820082, |
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.emif_ddr_ext_phy_ctrl_3 = 0x008b008b, |
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.emif_ddr_ext_phy_ctrl_4 = 0x00800080, |
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.emif_ddr_ext_phy_ctrl_5 = 0x007e007e, |
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.emif_rd_wr_lvl_rmp_win = 0x00000000, |
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000, |
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.emif_rd_wr_lvl_ctl = 0x00000000, |
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.emif_rd_wr_exec_thresh = 0x00000305 |
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}; |
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static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { |
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0x00800080, |
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0x00370037, |
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0x00390039, |
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0x00360036, |
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0x00370037, |
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0x00350035, |
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0x01ff01ff, |
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0x01ff01ff, |
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0x01ff01ff, |
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0x01ff01ff, |
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0x01ff01ff, |
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0x00540054, |
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0x00540054, |
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0x004e004e, |
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0x004c004c, |
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0x00400040, |
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0x00000000, |
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0x00600020, |
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0x40010080, |
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0x08102040, |
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0x00400040, |
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0x00400040, |
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0x00400040, |
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0x00400040, |
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0x00400040 |
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}; |
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) |
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{ |
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switch (emif_nr) { |
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case 1: |
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*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; |
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break; |
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case 2: |
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*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; |
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break; |
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} |
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} |
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void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) |
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{ |
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switch (emif_nr) { |
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case 1: |
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*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; |
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*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); |
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break; |
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case 2: |
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*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; |
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*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); |
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break; |
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} |
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} |
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struct vcores_data beagle_x15_volts = { |
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.mpu.value = VDD_MPU_DRA752, |
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.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, |
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.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
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.mpu.addr = TPS659038_REG_ADDR_SMPS12, |
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.mpu.pmic = &tps659038, |
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.eve.value = VDD_EVE_DRA752, |
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.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, |
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.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
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.eve.addr = TPS659038_REG_ADDR_SMPS45, |
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.eve.pmic = &tps659038, |
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.gpu.value = VDD_GPU_DRA752, |
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.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, |
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.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
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.gpu.addr = TPS659038_REG_ADDR_SMPS45, |
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.gpu.pmic = &tps659038, |
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.core.value = VDD_CORE_DRA752, |
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.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, |
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.core.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
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.core.addr = TPS659038_REG_ADDR_SMPS6, |
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.core.pmic = &tps659038, |
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.iva.value = VDD_IVA_DRA752, |
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.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, |
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.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
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.iva.addr = TPS659038_REG_ADDR_SMPS45, |
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.iva.pmic = &tps659038, |
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}; |
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void hw_data_init(void) |
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{ |
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*prcm = &dra7xx_prcm; |
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*dplls_data = &dra7xx_dplls; |
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*omap_vcores = &beagle_x15_volts; |
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*ctrl = &dra7xx_ctrl; |
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} |
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int board_init(void) |
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{ |
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gpmc_init(); |
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gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); |
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return 0; |
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} |
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int board_late_init(void) |
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{ |
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init_sata(0); |
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/*
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* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds |
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* This is the POWERHOLD-in-Low behavior. |
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*/ |
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palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); |
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return 0; |
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} |
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static void do_set_mux32(u32 base, |
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struct pad_conf_entry const *array, int size) |
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{ |
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int i; |
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struct pad_conf_entry *pad = (struct pad_conf_entry *)array; |
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for (i = 0; i < size; i++, pad++) |
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writel(pad->val, base + pad->offset); |
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} |
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void set_muxconf_regs_essential(void) |
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{ |
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do_set_mux32((*ctrl)->control_padconf_core_base, |
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core_padconf_array_essential, |
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sizeof(core_padconf_array_essential) / |
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sizeof(struct pad_conf_entry)); |
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} |
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) |
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int board_mmc_init(bd_t *bis) |
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{ |
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omap_mmc_init(0, 0, 0, -1, -1); |
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omap_mmc_init(1, 0, 0, -1, -1); |
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return 0; |
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} |
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#endif |
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) |
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int spl_start_uboot(void) |
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{ |
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/* break into full u-boot on 'c' */ |
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if (serial_tstc() && serial_getc() == 'c') |
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return 1; |
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#ifdef CONFIG_SPL_ENV_SUPPORT |
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env_init(); |
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env_relocate_spec(); |
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if (getenv_yesno("boot_os") != 1) |
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return 1; |
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#endif |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_DRIVER_TI_CPSW |
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/* Delay value to add to calibrated value */ |
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#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) |
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#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) |
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#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) |
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#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) |
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#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) |
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#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) |
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#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) |
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#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) |
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#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) |
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#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) |
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static void cpsw_control(int enabled) |
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{ |
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/* VTP can be added here */ |
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} |
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static struct cpsw_slave_data cpsw_slaves[] = { |
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{ |
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.slave_reg_ofs = 0x208, |
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.sliver_reg_ofs = 0xd80, |
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.phy_addr = 1, |
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}, |
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{ |
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.slave_reg_ofs = 0x308, |
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.sliver_reg_ofs = 0xdc0, |
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.phy_addr = 2, |
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}, |
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}; |
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static struct cpsw_platform_data cpsw_data = { |
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.mdio_base = CPSW_MDIO_BASE, |
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.cpsw_base = CPSW_BASE, |
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.mdio_div = 0xff, |
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.channels = 8, |
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.cpdma_reg_ofs = 0x800, |
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.slaves = 1, |
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.slave_data = cpsw_slaves, |
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.ale_reg_ofs = 0xd00, |
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.ale_entries = 1024, |
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.host_port_reg_ofs = 0x108, |
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.hw_stats_reg_ofs = 0x900, |
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.bd_ram_ofs = 0x2000, |
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.mac_control = (1 << 5), |
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.control = cpsw_control, |
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.host_port_num = 0, |
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.version = CPSW_CTRL_VERSION_2, |
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}; |
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int board_eth_init(bd_t *bis) |
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{ |
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int ret; |
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uint8_t mac_addr[6]; |
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uint32_t mac_hi, mac_lo; |
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uint32_t ctrl_val; |
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/* try reading mac address from efuse */ |
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mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); |
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mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); |
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mac_addr[0] = (mac_hi & 0xFF0000) >> 16; |
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mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
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mac_addr[2] = mac_hi & 0xFF; |
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mac_addr[3] = (mac_lo & 0xFF0000) >> 16; |
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mac_addr[4] = (mac_lo & 0xFF00) >> 8; |
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mac_addr[5] = mac_lo & 0xFF; |
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if (!getenv("ethaddr")) { |
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printf("<ethaddr> not set. Validating first E-fuse MAC\n"); |
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if (is_valid_ether_addr(mac_addr)) |
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eth_setenv_enetaddr("ethaddr", mac_addr); |
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} |
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mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); |
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mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); |
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mac_addr[0] = (mac_hi & 0xFF0000) >> 16; |
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mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
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mac_addr[2] = mac_hi & 0xFF; |
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mac_addr[3] = (mac_lo & 0xFF0000) >> 16; |
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mac_addr[4] = (mac_lo & 0xFF00) >> 8; |
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mac_addr[5] = mac_lo & 0xFF; |
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if (!getenv("eth1addr")) { |
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if (is_valid_ether_addr(mac_addr)) |
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eth_setenv_enetaddr("eth1addr", mac_addr); |
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} |
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ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); |
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ctrl_val |= 0x22; |
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writel(ctrl_val, (*ctrl)->control_core_control_io1); |
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ret = cpsw_register(&cpsw_data); |
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if (ret < 0) |
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printf("Error %d registering CPSW switch\n", ret); |
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return ret; |
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} |
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#endif |
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#ifdef CONFIG_USB_XHCI_OMAP |
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int board_usb_init(int index, enum usb_init_type init) |
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{ |
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setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, |
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OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M); |
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return 0; |
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} |
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#endif |
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@ -0,0 +1,55 @@ |
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
|
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* |
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* Author: Felipe Balbi <balbi@ti.com> |
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* |
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* Based on board/ti/dra7xx/evm.c |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _MUX_DATA_BEAGLE_X15_H_ |
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#define _MUX_DATA_BEAGLE_X15_H_ |
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|
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#include <asm/arch/mux_dra7xx.h> |
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|
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const struct pad_conf_entry core_padconf_array_essential[] = { |
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{MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ |
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{MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ |
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{MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ |
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{MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ |
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{MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ |
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{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ |
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{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ |
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{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ |
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{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ |
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{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ |
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{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ |
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{GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ |
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{GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ |
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{GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ |
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{GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ |
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{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ |
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{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ |
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{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ |
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{UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ |
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{UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ |
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{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ |
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{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ |
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{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ |
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{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ |
||||
{RGMII0_TXC, (M0) }, |
||||
{RGMII0_TXCTL, (M0) }, |
||||
{RGMII0_TXD3, (M0) }, |
||||
{RGMII0_TXD2, (M0) }, |
||||
{RGMII0_TXD1, (M0) }, |
||||
{RGMII0_TXD0, (M0) }, |
||||
{RGMII0_RXC, (IEN | M0) }, |
||||
{RGMII0_RXCTL, (IEN | M0) }, |
||||
{RGMII0_RXD3, (IEN | M0) }, |
||||
{RGMII0_RXD2, (IEN | M0) }, |
||||
{RGMII0_RXD1, (IEN | M0) }, |
||||
{RGMII0_RXD0, (IEN | M0) }, |
||||
{USB1_DRVVBUS, (M0 | FSC) }, |
||||
{SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */ |
||||
}; |
||||
#endif /* _MUX_DATA_BEAGLE_X15_H_ */ |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" |
||||
+S:CONFIG_ARM=y |
||||
+S:CONFIG_OMAP54XX=y |
||||
+S:CONFIG_TARGET_BEAGLE_X15=y |
||||
@ -0,0 +1,88 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Texas Instruments Incorporated. |
||||
* Felipe Balbi <balbi@ti.com> |
||||
* |
||||
* Configuration settings for the TI Beagle x15 board. |
||||
* See ti_omap5_common.h for omap5 common settings. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_BEAGLE_X15_H |
||||
#define __CONFIG_BEAGLE_X15_H |
||||
|
||||
#define CONFIG_AM57XX |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 2 |
||||
|
||||
#define CONFIG_ENV_SIZE (64 << 10) |
||||
#define CONFIG_ENV_IS_IN_FAT |
||||
#define FAT_ENV_INTERFACE "mmc" |
||||
#define FAT_ENV_DEVICE_AND_PART "0:1" |
||||
#define FAT_ENV_FILE "uboot.env" |
||||
|
||||
#define CONFIG_CMD_SAVEENV |
||||
|
||||
#define CONSOLEDEV "ttyO2" |
||||
#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ |
||||
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ |
||||
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_SYS_OMAP_ABE_SYSCK |
||||
|
||||
/* Define the default GPT table for eMMC */ |
||||
#define PARTS_DEFAULT \ |
||||
"uuid_disk=${uuid_gpt_disk};" \
|
||||
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" |
||||
|
||||
#include <configs/ti_omap5_common.h> |
||||
|
||||
/* Enhance our eMMC support / experience. */ |
||||
#define CONFIG_CMD_GPT |
||||
#define CONFIG_EFI_PARTITION |
||||
#define CONFIG_PARTITION_UUIDS |
||||
#define CONFIG_CMD_PART |
||||
|
||||
/* CPSW Ethernet */ |
||||
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ |
||||
#define CONFIG_BOOTP_DNS2 |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_NET_RETRY_COUNT 10 |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ |
||||
#define CONFIG_MII /* Required in net/eth.c */ |
||||
#define CONFIG_PHY_GIGE /* per-board part of CPSW */ |
||||
#define CONFIG_PHYLIB |
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT |
||||
|
||||
/* USB xHCI HOST */ |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_USB_HOST |
||||
#define CONFIG_USB_XHCI |
||||
#define CONFIG_USB_XHCI_OMAP |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
||||
|
||||
#define CONFIG_OMAP_USB_PHY |
||||
#define CONFIG_OMAP_USB3PHY1_HOST |
||||
|
||||
/* SATA */ |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
#define CONFIG_CMD_SCSI |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_SCSI_AHCI |
||||
#define CONFIG_SCSI_AHCI_PLAT |
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 |
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1 |
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
||||
CONFIG_SYS_SCSI_MAX_LUN) |
||||
|
||||
#endif /* __CONFIG_BEAGLE_X5_H */ |
||||
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Reference in new issue