Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>master
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/* |
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* Copyright 2016 Beckhoff Automation |
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* Copyright 2011 Freescale Semiconductor, Inc. |
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* Copyright 2011 Linaro Ltd. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ or X11 |
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*/ |
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|
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/dts-v1/; |
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#include "imx53.dtsi" |
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|
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#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 |
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#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 |
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#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 |
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#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 |
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|
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/ { |
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model = "Beckhoff CX9020-0100 i.MX53"; |
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compatible = "fsl,imx53-qsb", "fsl,imx53"; |
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chosen { |
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stdout-path = &uart2; |
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}; |
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}; |
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&iomuxc { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_hog>; |
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|
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imx53-qsb { |
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pinctrl_hog: hoggrp { |
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fsl,pins = < |
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MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 |
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MX53_PAD_GPIO_8__GPIO1_8 0x80000000 |
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MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 |
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MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 |
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MX53_PAD_GPIO_1__GPIO1_1 0x80000000 |
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MX53_PAD_GPIO_4__GPIO1_4 0x80000000 |
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MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 |
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MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 |
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MX53_PAD_GPIO_16__GPIO7_11 0x80000000 |
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|
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MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 |
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MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x80000000 |
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MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x80000000 |
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MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 |
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MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x80000000 |
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MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x80000000 |
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MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x80000000 |
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MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x80000000 |
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MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x80000000 |
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MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 |
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MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x80000000 |
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MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x80000000 |
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MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x80000000 |
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MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x80000000 |
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MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x80000000 |
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MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x80000000 |
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MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x80000000 |
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MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 |
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MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 |
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MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 |
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MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 |
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MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 |
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MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 |
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MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 |
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MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 |
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MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0xa4 |
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MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0xa4 |
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MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0xa4 |
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MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0xa4 |
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MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0xa4 |
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MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0xa4 |
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MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0xa4 |
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MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0xa4 |
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MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 |
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MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 |
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MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 |
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MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 |
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MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 |
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MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 |
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MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 |
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MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 |
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MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0xa4 |
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MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0xa4 |
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MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0xa4 |
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MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0xa4 |
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MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0xa4 |
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MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0xa4 |
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MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0xa4 |
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MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0xa4 |
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MX53_PAD_NANDF_CLE__GPIO6_7 0x00000001 |
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MX53_PAD_NANDF_WP_B__GPIO6_9 0x00000001 |
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MX53_PAD_NANDF_ALE__GPIO6_8 0x00000001 |
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MX53_PAD_EIM_D23__GPIO3_23 0x80000000 |
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MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 |
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MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 |
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MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 |
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MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 |
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MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 |
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MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 |
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MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 |
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MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 |
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MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 |
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MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 |
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MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 |
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MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 |
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MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 |
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MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 |
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MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 |
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MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 |
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MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 |
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 |
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 |
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 |
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 |
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 |
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 |
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 |
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 |
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 |
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MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec |
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MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec |
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MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 |
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MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 |
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MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 |
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MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 |
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MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 |
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MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 |
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MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 |
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MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 |
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MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 |
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MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 |
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MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 |
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MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 |
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MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 |
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MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 |
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MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 |
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MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 |
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MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 |
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MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 |
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MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 |
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MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 |
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MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 |
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MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 |
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MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 |
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MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 |
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MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 |
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MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 |
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MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 |
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MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 |
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MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 |
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MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 |
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MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 |
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>; |
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}; |
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pinctrl_uart2: uart2grp { |
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fsl,pins = < |
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MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 |
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MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 |
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MX53_PAD_EIM_D28__UART2_RTS 0x1e4 |
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MX53_PAD_EIM_D29__UART2_CTS 0x1e4 |
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>; |
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}; |
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}; |
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}; |
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&uart2 { |
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pinctrl-names = "default"; |
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uart-has-rtscts; |
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fsl,dte-mode; |
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pinctrl-0 = <&pinctrl_uart2>; |
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status = "okay"; |
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}; |
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&fec { |
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pinctrl-names = "default"; |
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phy-mode = "rmii"; |
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phy-reset-gpios = <&gpio7 6 0>; |
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status = "okay"; |
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}; |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,110 @@ |
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/* |
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* Copyright 2016 Beckhoff Automation |
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* Copyright 2011 Freescale Semiconductor, Inc. |
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* Copyright 2011 Linaro Ltd. |
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* |
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* The code contained herein is licensed under the GNU General Public |
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* License. You may obtain a copy of the GNU General Public License |
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* Version 2 or later at the following locations: |
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* |
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* http://www.opensource.org/licenses/gpl-license.html |
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* http://www.gnu.org/copyleft/gpl.html |
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*/ |
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#include "skeleton.dtsi" |
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#include "imx53-pinfunc.h" |
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#include <dt-bindings/clock/imx5-clock.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/input/input.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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/ { |
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aliases { |
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serial1 = &uart2; |
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}; |
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soc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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ranges; |
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aips@50000000 { /* AIPS1 */ |
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compatible = "fsl,aips-bus", "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x50000000 0x10000000>; |
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ranges; |
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iomuxc: iomuxc@53fa8000 { |
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compatible = "fsl,imx53-iomuxc"; |
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reg = <0x53fa8000 0x4000>; |
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}; |
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gpr: iomuxc-gpr@53fa8000 { |
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compatible = "fsl,imx53-iomuxc-gpr", "syscon"; |
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reg = <0x53fa8000 0xc>; |
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}; |
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uart2: serial@53fc0000 { |
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compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart"; |
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reg = <0x53fc0000 0x4000>; |
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interrupts = <32>; |
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clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
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<&clks IMX5_CLK_UART2_PER_GATE>; |
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clock-names = "ipg", "per"; |
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dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; |
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dma-names = "rx", "tx"; |
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status = "disabled"; |
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}; |
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clks: ccm@53fd4000{ |
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compatible = "fsl,imx53-ccm"; |
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reg = <0x53fd4000 0x4000>; |
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interrupts = <0 71 0x04 0 72 0x04>; |
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#clock-cells = <1>; |
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}; |
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gpio7: gpio@53fe4000 { |
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
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reg = <0x53fe4000 0x4000>; |
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interrupts = <107 108>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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aips@60000000 { /* AIPS2 */ |
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compatible = "fsl,aips-bus", "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x60000000 0x10000000>; |
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ranges; |
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sdma: sdma@63fb0000 { |
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compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
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reg = <0x63fb0000 0x4000>; |
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interrupts = <6>; |
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clocks = <&clks IMX5_CLK_SDMA_GATE>, |
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<&clks IMX5_CLK_SDMA_GATE>; |
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clock-names = "ipg", "ahb"; |
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#dma-cells = <3>; |
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fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
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}; |
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fec: ethernet@63fec000 { |
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compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
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reg = <0x63fec000 0x4000>; |
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interrupts = <87>; |
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clocks = <&clks IMX5_CLK_FEC_GATE>, |
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<&clks IMX5_CLK_FEC_GATE>, |
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<&clks IMX5_CLK_FEC_GATE>; |
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clock-names = "ipg", "ahb", "ptp"; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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}; |
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if TARGET_MX53CX9020 |
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config SYS_BOARD |
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default "mx53cx9020" |
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config SYS_VENDOR |
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default "beckhoff" |
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config SYS_CONFIG_NAME |
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default "mx53cx9020" |
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endif |
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MX53 CX9020 |
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M: Patrick Bruenn <p.bruenn@beckhoff.com> |
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S: Maintained |
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F: board/beckhoff/mx53cx9020/ |
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F: include/configs/mx53cx9020.h |
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F: configs/mx53cx9020_defconfig |
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#
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# Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
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# Patrick Bruenn <p.bruenn@beckhoff.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += mx53cx9020.o
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obj-$(CONFIG_VIDEO) += mx53cx9020_video.o
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/* |
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* Copyright (C) 2015 Beckhoff Automation GmbH |
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* Patrick Bruenn <p.bruenn@beckhoff.com> |
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* |
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* Based on <u-boot>/board/freescale/mx53loco/imximage.cfg |
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* Copyright (C) 2011 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/* image version */ |
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IMAGE_VERSION 2 |
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/* |
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* Boot Device : one of |
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* spi, sd (the board has no nand neither onenand) |
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*/ |
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BOOT_FROM sd |
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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DATA 4 0x53fa8554 0x00300000 |
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DATA 4 0x53fa8558 0x00300040 |
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DATA 4 0x53fa8560 0x00300000 |
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DATA 4 0x53fa8564 0x00300040 |
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DATA 4 0x53fa8568 0x00300040 |
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DATA 4 0x53fa8570 0x00300000 |
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DATA 4 0x53fa8574 0x00300000 |
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DATA 4 0x53fa8578 0x00300000 |
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DATA 4 0x53fa857c 0x00300040 |
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DATA 4 0x53fa8580 0x00300040 |
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DATA 4 0x53fa8584 0x00300000 |
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DATA 4 0x53fa8588 0x00300000 |
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DATA 4 0x53fa8590 0x00300040 |
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DATA 4 0x53fa8594 0x00300000 |
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DATA 4 0x53fa86f0 0x00300000 |
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DATA 4 0x53fa86f4 0x00000000 |
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DATA 4 0x53fa86fc 0x00000000 |
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DATA 4 0x53fa8714 0x00000000 |
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DATA 4 0x53fa8718 0x00300000 |
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DATA 4 0x53fa871c 0x00300000 |
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DATA 4 0x53fa8720 0x00300000 |
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DATA 4 0x53fa8724 0x00000000 |
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DATA 4 0x53fa8728 0x00300000 |
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DATA 4 0x53fa872c 0x00300000 |
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DATA 4 0x63fd9088 0x35343535 |
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DATA 4 0x63fd9090 0x4d444c44 |
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DATA 4 0x63fd907c 0x01370138 |
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DATA 4 0x63fd9080 0x013b013c |
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DATA 4 0x63fd9018 0x00011740 |
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DATA 4 0x63fd9000 0x83190000 |
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DATA 4 0x63fd900c 0x40425333 |
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DATA 4 0x63fd9010 0xb68e8a63 |
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DATA 4 0x63fd9014 0x01ff00db |
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DATA 4 0x63fd902c 0x000026d2 |
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DATA 4 0x63fd9030 0x009f0e21 |
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DATA 4 0x63fd9008 0x12273030 |
||||
DATA 4 0x63fd9004 0x0002002d |
||||
DATA 4 0x63fd901c 0x00008032 |
||||
DATA 4 0x63fd901c 0x00008033 |
||||
DATA 4 0x63fd901c 0x00028031 |
||||
DATA 4 0x63fd901c 0x052080b0 |
||||
DATA 4 0x63fd901c 0x04008040 |
||||
DATA 4 0x63fd9000 0xc3190000 |
||||
DATA 4 0x63fd901c 0x0000803a |
||||
DATA 4 0x63fd901c 0x0000803b |
||||
DATA 4 0x63fd901c 0x00028039 |
||||
DATA 4 0x63fd901c 0x05208138 |
||||
DATA 4 0x63fd901c 0x04008048 |
||||
DATA 4 0x63fd9020 0x00005800 |
||||
DATA 4 0x63fd9040 0x05380003 |
||||
DATA 4 0x63fd9058 0x00022227 |
||||
DATA 4 0x63fd901c 0x00000000 |
@ -0,0 +1,367 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG |
||||
* Patrick Bruenn <p.bruenn@beckhoff.com> |
||||
* |
||||
* Based on <u-boot>/board/freescale/mx53loco/mx53loco.c |
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/iomux-mx53.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/imx-common/mx5_video.h> |
||||
#include <ACEX1K.h> |
||||
#include <netdev.h> |
||||
#include <i2c.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <asm/gpio.h> |
||||
#include <linux/fb.h> |
||||
#include <ipu_pixfmt.h> |
||||
#include <fs.h> |
||||
#include <dm/platdata.h> |
||||
#include <dm/platform_data/serial_mxc.h> |
||||
|
||||
enum LED_GPIOS { |
||||
GPIO_SD1_CD = IMX_GPIO_NR(1, 1), |
||||
GPIO_SD2_CD = IMX_GPIO_NR(1, 4), |
||||
GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16), |
||||
GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17), |
||||
GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18), |
||||
GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19), |
||||
GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20), |
||||
GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21), |
||||
GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22), |
||||
GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23), |
||||
GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24), |
||||
GPIO_SUPS_INT = IMX_GPIO_NR(3, 31), |
||||
GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8), |
||||
GPIO_C3_STATUS = IMX_GPIO_NR(6, 7), |
||||
GPIO_C3_DONE = IMX_GPIO_NR(6, 9), |
||||
}; |
||||
|
||||
#define CCAT_BASE_ADDR ((void *)0xf0000000) |
||||
#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32)) |
||||
#define CCAT_SIZE 1191788 |
||||
#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12) |
||||
static const char CCAT_SIGNATURE[] = "CCAT"; |
||||
|
||||
static const u32 CCAT_MODE_CONFIG = 0x0024DC81; |
||||
static const u32 CCAT_MODE_RUN = 0x0033DC8F; |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static uint32_t mx53_dram_size[2]; |
||||
|
||||
phys_size_t get_effective_memsize(void) |
||||
{ |
||||
/*
|
||||
* WARNING: We must override get_effective_memsize() function here |
||||
* to report only the size of the first DRAM bank. This is to make |
||||
* U-Boot relocator place U-Boot into valid memory, that is, at the |
||||
* end of the first DRAM bank. If we did not override this function |
||||
* like so, U-Boot would be placed at the address of the first DRAM |
||||
* bank + total DRAM size - sizeof(uboot), which in the setup where |
||||
* each DRAM bank contains 512MiB of DRAM would result in placing |
||||
* U-Boot into invalid memory area close to the end of the first |
||||
* DRAM bank. |
||||
*/ |
||||
return mx53_dram_size[0]; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); |
||||
mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); |
||||
|
||||
gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = mx53_dram_size[0]; |
||||
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
||||
gd->bd->bi_dram[1].size = mx53_dram_size[1]; |
||||
} |
||||
|
||||
u32 get_board_rev(void) |
||||
{ |
||||
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; |
||||
struct fuse_bank *bank = &iim->bank[0]; |
||||
struct fuse_bank0_regs *fuse = |
||||
(struct fuse_bank0_regs *)bank->fuse_regs; |
||||
|
||||
int rev = readl(&fuse->gp[6]); |
||||
|
||||
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; |
||||
} |
||||
|
||||
/*
|
||||
* Set CCAT mode |
||||
* @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN |
||||
*/ |
||||
void weim_cs0_settings(u32 mode) |
||||
{ |
||||
struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; |
||||
|
||||
writel(0x0, &weim_regs->cs0gcr1); |
||||
writel(mode, &weim_regs->cs0gcr1); |
||||
writel(0x00001002, &weim_regs->cs0gcr2); |
||||
|
||||
writel(0x04000000, &weim_regs->cs0rcr1); |
||||
writel(0x00000000, &weim_regs->cs0rcr2); |
||||
|
||||
writel(0x04000000, &weim_regs->cs0wcr1); |
||||
writel(0x00000000, &weim_regs->cs0wcr2); |
||||
} |
||||
|
||||
static void setup_gpio_eim(void) |
||||
{ |
||||
gpio_direction_input(GPIO_C3_STATUS); |
||||
gpio_direction_input(GPIO_C3_DONE); |
||||
gpio_direction_output(GPIO_C3_CONFIG, 1); |
||||
|
||||
weim_cs0_settings(CCAT_MODE_RUN); |
||||
} |
||||
|
||||
static void setup_gpio_sups(void) |
||||
{ |
||||
gpio_direction_input(GPIO_SUPS_INT); |
||||
|
||||
static const int BLINK_INTERVALL = 50000; |
||||
int status = 1; |
||||
while (gpio_get_value(GPIO_SUPS_INT)) { |
||||
/* signal "CX SUPS power fail" */ |
||||
gpio_set_value(GPIO_LED_PWR_R, |
||||
(++status / BLINK_INTERVALL) % 2); |
||||
} |
||||
|
||||
/* signal "CX power up" */ |
||||
gpio_set_value(GPIO_LED_PWR_R, 1); |
||||
} |
||||
|
||||
static void setup_gpio_leds(void) |
||||
{ |
||||
gpio_direction_output(GPIO_LED_SD2_R, 0); |
||||
gpio_direction_output(GPIO_LED_SD2_B, 0); |
||||
gpio_direction_output(GPIO_LED_SD2_G, 0); |
||||
gpio_direction_output(GPIO_LED_SD1_R, 0); |
||||
gpio_direction_output(GPIO_LED_SD1_B, 0); |
||||
gpio_direction_output(GPIO_LED_SD1_G, 0); |
||||
gpio_direction_output(GPIO_LED_PWR_R, 0); |
||||
gpio_direction_output(GPIO_LED_PWR_B, 0); |
||||
gpio_direction_output(GPIO_LED_PWR_G, 0); |
||||
} |
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX5 |
||||
int board_ehci_hcd_init(int port) |
||||
{ |
||||
/* request VBUS power enable pin, GPIO7_8 */ |
||||
gpio_direction_output(IMX_GPIO_NR(7, 8), 1); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
struct fsl_esdhc_cfg esdhc_cfg[2] = { |
||||
{MMC_SDHC1_BASE_ADDR}, |
||||
{MMC_SDHC2_BASE_ADDR}, |
||||
}; |
||||
|
||||
int board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
int ret; |
||||
|
||||
gpio_direction_input(GPIO_SD1_CD); |
||||
gpio_direction_input(GPIO_SD2_CD); |
||||
|
||||
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) |
||||
ret = !gpio_get_value(GPIO_SD1_CD); |
||||
else |
||||
ret = !gpio_get_value(GPIO_SD2_CD); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
u32 index; |
||||
int ret; |
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
||||
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { |
||||
switch (index) { |
||||
case 0: |
||||
break; |
||||
case 1: |
||||
break; |
||||
default: |
||||
printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n", |
||||
CONFIG_SYS_FSL_ESDHC_NUM); |
||||
return -EINVAL; |
||||
} |
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); |
||||
if (ret) |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
static int power_init(void) |
||||
{ |
||||
/* nothing to do on CX9020 */ |
||||
return 0; |
||||
} |
||||
|
||||
static void clock_1GHz(void) |
||||
{ |
||||
int ret; |
||||
u32 ref_clk = MXC_HCLK; |
||||
/*
|
||||
* After increasing voltage to 1.25V, we can switch |
||||
* CPU clock to 1GHz and DDR to 400MHz safely |
||||
*/ |
||||
ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); |
||||
if (ret) |
||||
printf("CPU: Switch CPU clock to 1GHZ failed\n"); |
||||
|
||||
ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); |
||||
ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); |
||||
if (ret) |
||||
printf("CPU: Switch DDR clock to 400MHz failed\n"); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
setup_gpio_leds(); |
||||
setup_gpio_sups(); |
||||
setup_gpio_eim(); |
||||
setup_iomux_lcd(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Do not overwrite the console |
||||
* Use always serial for U-Boot console |
||||
*/ |
||||
int overwrite_console(void) |
||||
{ |
||||
return 1; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||
|
||||
mxc_set_sata_internal_clock(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: Beckhoff CX9020\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ccat_config_fn(int assert_config, int flush, int cookie) |
||||
{ |
||||
/* prepare FPGA for programming */ |
||||
weim_cs0_settings(CCAT_MODE_CONFIG); |
||||
gpio_set_value(GPIO_C3_CONFIG, 0); |
||||
udelay(1); |
||||
gpio_set_value(GPIO_C3_CONFIG, 1); |
||||
udelay(230); |
||||
|
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
static int ccat_status_fn(int cookie) |
||||
{ |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie) |
||||
{ |
||||
const uint8_t *const buffer = buf; |
||||
|
||||
/* program CCAT */ |
||||
int i; |
||||
for (i = 0; i < buf_len; ++i) |
||||
writeb(buffer[i], CCAT_BASE_ADDR); |
||||
|
||||
writeb(0xff, CCAT_BASE_ADDR); |
||||
writeb(0xff, CCAT_BASE_ADDR); |
||||
|
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
static int ccat_done_fn(int cookie) |
||||
{ |
||||
/* programming complete? */ |
||||
return gpio_get_value(GPIO_C3_DONE); |
||||
} |
||||
|
||||
static int ccat_post_fn(int cookie) |
||||
{ |
||||
/* switch to FPGA run mode */ |
||||
weim_cs0_settings(CCAT_MODE_RUN); |
||||
invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR); |
||||
|
||||
if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) { |
||||
printf("Verifing CCAT firmware failed, signature not found\n"); |
||||
return FPGA_FAIL; |
||||
} |
||||
|
||||
/* signal "CX booting OS" */ |
||||
gpio_set_value(GPIO_LED_PWR_R, 1); |
||||
gpio_set_value(GPIO_LED_PWR_G, 1); |
||||
gpio_set_value(GPIO_LED_PWR_B, 0); |
||||
return FPGA_SUCCESS; |
||||
} |
||||
|
||||
static Altera_CYC2_Passive_Serial_fns ccat_fns = { |
||||
.config = ccat_config_fn, |
||||
.status = ccat_status_fn, |
||||
.done = ccat_done_fn, |
||||
.write = ccat_write_fn, |
||||
.abort = ccat_post_fn, |
||||
.post = ccat_post_fn, |
||||
}; |
||||
|
||||
static Altera_desc ccat_fpga = { |
||||
.family = Altera_CYC2, |
||||
.iface = passive_serial, |
||||
.size = CCAT_SIZE, |
||||
.iface_fns = &ccat_fns, |
||||
.base = CCAT_BASE_ADDR, |
||||
}; |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
if (!power_init()) |
||||
clock_1GHz(); |
||||
|
||||
fpga_init(); |
||||
fpga_add(fpga_altera, &ccat_fpga); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,49 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG |
||||
* Patrick Bruenn <p.bruenn@beckhoff.com> |
||||
* |
||||
* Based on <u-boot>/board/freescale/mx53loco/mx53loco_video.c |
||||
* Copyright (C) 2012 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/list.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/arch/iomux-mx53.h> |
||||
#include <linux/fb.h> |
||||
#include <ipu_pixfmt.h> |
||||
|
||||
#define CX9020_DVI_PWD IMX_GPIO_NR(6, 1) |
||||
|
||||
static struct fb_videomode const vga_640x480 = { |
||||
.name = "VESA_VGA_640x480", |
||||
.refresh = 60, |
||||
.xres = 640, |
||||
.yres = 480, |
||||
.pixclock = 39721, /* picosecond (25.175 MHz) */ |
||||
.left_margin = 40, |
||||
.right_margin = 60, |
||||
.upper_margin = 10, |
||||
.lower_margin = 10, |
||||
.hsync_len = 20, |
||||
.vsync_len = 10, |
||||
.sync = 0, |
||||
.vmode = FB_VMODE_NONINTERLACED |
||||
}; |
||||
|
||||
void setup_iomux_lcd(void) |
||||
{ |
||||
/* Turn on DVI_PWD */ |
||||
imx_iomux_v3_setup_pad(MX53_PAD_CSI0_DAT15__GPIO6_1); |
||||
gpio_direction_output(CX9020_DVI_PWD, 1); |
||||
} |
||||
|
||||
int board_video_skip(void) |
||||
{ |
||||
const int ret = ipuv3_fb_init(&vga_640x480, 0, IPU_PIX_FMT_RGB24); |
||||
if (ret) |
||||
printf("VESA VG 640x480 cannot be configured: %d\n", ret); |
||||
return ret; |
||||
} |
@ -0,0 +1,35 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX5=y |
||||
CONFIG_TARGET_MX53CX9020=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020" |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg" |
||||
CONFIG_BOOTDELAY=1 |
||||
CONFIG_HUSH_PARSER=y |
||||
# CONFIG_DM_MMC_OPS is not set |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MMC=y |
||||
#CONFIG_CMD_USB=y |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_VIDEO=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_MXC_UART=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_FPGA_ALTERA=y |
||||
CONFIG_FPGA_CYCLON2=y |
||||
CONFIG_CMD_FPGA=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX5=y |
||||
# CONFIG_VIDEO_SW_CURSOR is not set |
||||
CONFIG_CFB_CONSOLE=y |
||||
CONFIG_VGA_AS_SINGLE_DEVICE=y |
||||
CONFIG_SYS_CONSOLE_BG_COL=0x00 |
||||
CONFIG_SYS_CONSOLE_FG_COL=0xa0 |
@ -1,3 +1,4 @@ |
||||
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o
|
||||
obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
|
||||
|
@ -0,0 +1,44 @@ |
||||
|
||||
/*
|
||||
* Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <dm/device.h> |
||||
#include <dm/pinctrl.h> |
||||
|
||||
#include "pinctrl-imx.h" |
||||
|
||||
static struct imx_pinctrl_soc_info imx5_pinctrl_soc_info; |
||||
|
||||
static int imx5_pinctrl_probe(struct udevice *dev) |
||||
{ |
||||
struct imx_pinctrl_soc_info *info = |
||||
(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); |
||||
|
||||
return imx_pinctrl_probe(dev, info); |
||||
} |
||||
|
||||
static const struct udevice_id imx5_pinctrl_match[] = { |
||||
{ |
||||
.compatible = "fsl,imx53-iomuxc", |
||||
.data = (ulong)&imx5_pinctrl_soc_info |
||||
}, |
||||
{ |
||||
.compatible = "fsl,imx53-iomuxc-gpr", |
||||
.data = (ulong)&imx5_pinctrl_soc_info |
||||
}, |
||||
{ /* sentinel */ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(imx5_pinctrl) = { |
||||
.name = "imx5-pinctrl", |
||||
.id = UCLASS_PINCTRL, |
||||
.of_match = of_match_ptr(imx5_pinctrl_match), |
||||
.probe = imx5_pinctrl_probe, |
||||
.remove = imx_pinctrl_remove, |
||||
.priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), |
||||
.ops = &imx_pinctrl_ops, |
||||
.flags = DM_FLAG_PRE_RELOC, |
||||
}; |
@ -0,0 +1,198 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG |
||||
* Patrick Bruenn <p.bruenn@beckhoff.com> |
||||
* |
||||
* Configuration settings for Beckhoff CX9020. |
||||
* |
||||
* Based on Freescale's Linux i.MX mx53loco.h file: |
||||
* Copyright (C) 2010-2011 Freescale Semiconductor. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
|
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
|
||||
#define CONFIG_SYS_FSL_CLK |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
#define CONFIG_MXC_GPIO |
||||
#define CONFIG_REVISION_TAG |
||||
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE |
||||
|
||||
#define CONFIG_FPGA_COUNT 1 |
||||
|
||||
/* MMC Configs */ |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 2 |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
|
||||
/* bootz: zImage/initrd.img support */ |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* Eth Configs */ |
||||
#define CONFIG_MII |
||||
#define IMX_FEC_BASE FEC_BASE_ADDR |
||||
#define CONFIG_ETHPRIME "FEC0" |
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1F |
||||
|
||||
/* USB Configs */ |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_MX5 |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_USB_HOST_ETHER |
||||
#define CONFIG_USB_ETHER_ASIX |
||||
#define CONFIG_USB_ETHER_MCS7830 |
||||
#define CONFIG_USB_ETHER_SMSC95XX |
||||
#define CONFIG_MXC_USB_PORT 1 |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* Command definition */ |
||||
#define CONFIG_SUPPORT_RAW_INITRD |
||||
|
||||
#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ |
||||
#define CONFIG_SYS_TEXT_BASE 0x77800000 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"fdt_addr=0x71ff0000\0" \
|
||||
"rdaddr=0x72000000\0" \
|
||||
"console=ttymxc1,115200\0" \
|
||||
"uenv=/boot/uEnv.txt\0" \
|
||||
"optargs=\0" \
|
||||
"cmdline=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcrootfstype=ext4 rootwait fixrtc\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \
|
||||
"rootfstype=${mmcrootfstype} " \
|
||||
"${cmdline}\0" \
|
||||
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
|
||||
"loadrd=load mmc ${bootpart} ${rdaddr} ${bootdir}/${rdfile};" \
|
||||
"setenv rdsize ${filesize}\0" \
|
||||
"loadfdt=echo loading ${fdt_path} ...;" \
|
||||
"load mmc ${bootpart} ${fdt_addr} ${fdt_path}\0" \
|
||||
"mmcboot=mmc dev ${mmcdev}; " \
|
||||
"if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"echo Checking for: ${uenv} ...;" \
|
||||
"setenv bootpart ${mmcdev}:${mmcpart};" \
|
||||
"if test -e mmc ${bootpart} ${uenv}; then " \
|
||||
"load mmc ${bootpart} ${loadaddr} ${uenv};" \
|
||||
"env import -t ${loadaddr} ${filesize};" \
|
||||
"echo Loaded environment from ${uenv};" \
|
||||
"if test -n ${dtb}; then " \
|
||||
"setenv fdt_file ${dtb};" \
|
||||
"echo Using: dtb=${fdt_file} ...;" \
|
||||
"fi;" \
|
||||
"echo Checking for uname_r in ${uenv}...;" \
|
||||
"if test -n ${uname_r}; then " \
|
||||
"echo Running uname_boot ...;" \
|
||||
"run uname_boot;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
"fi;\0" \
|
||||
"uname_boot="\
|
||||
"setenv bootdir /boot; " \
|
||||
"setenv bootfile vmlinuz-${uname_r}; " \
|
||||
"setenv ccatfile /boot/ccat.rbf; " \
|
||||
"echo loading CCAT firmware from ${ccatfile}; " \
|
||||
"load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \
|
||||
"fpga load 0 ${loadaddr} ${filesize}; " \
|
||||
"if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
|
||||
"echo loading ${bootdir}/${bootfile} ...; " \
|
||||
"run loadimage;" \
|
||||
"setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \
|
||||
"if test -e mmc ${bootpart} ${fdt_path}; then " \
|
||||
"run loadfdt;" \
|
||||
"else " \
|
||||
"echo; echo unable to find ${fdt_file} ...;" \
|
||||
"echo booting legacy ...;"\
|
||||
"run mmcargs;" \
|
||||
"echo debug: [${bootargs}] ... ;" \
|
||||
"echo debug: [bootz ${loadaddr}] ... ;" \
|
||||
"bootz ${loadaddr}; " \
|
||||
"fi;" \
|
||||
"run mmcargs;" \
|
||||
"echo debug: [${bootargs}] ... ;" \
|
||||
"echo debug: [bootz ${loadaddr} - ${fdt_addr}] ... ;" \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"fi;\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"run mmcboot;" |
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x70000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x70010000 |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 2 |
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR |
||||
#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) |
||||
#define PHYS_SDRAM_2 CSD1_BASE_ADDR |
||||
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) |
||||
#define PHYS_SDRAM_SIZE (gd->ram_size) |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) |
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) |
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
|
||||
/* Framebuffer and LCD */ |
||||
#define CONFIG_PREBOOT |
||||
#define CONFIG_VIDEO_IPUV3 |
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
||||
#define CONFIG_VIDEO_BMP_RLE8 |
||||
#define CONFIG_SPLASH_SCREEN |
||||
#define CONFIG_BMP_16BPP |
||||
#define CONFIG_VIDEO_LOGO |
||||
#define CONFIG_IPUV3_CLK 200000000 |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,219 @@ |
||||
/*
|
||||
* Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX5_H |
||||
#define __DT_BINDINGS_CLOCK_IMX5_H |
||||
|
||||
#define IMX5_CLK_DUMMY 0 |
||||
#define IMX5_CLK_CKIL 1 |
||||
#define IMX5_CLK_OSC 2 |
||||
#define IMX5_CLK_CKIH1 3 |
||||
#define IMX5_CLK_CKIH2 4 |
||||
#define IMX5_CLK_AHB 5 |
||||
#define IMX5_CLK_IPG 6 |
||||
#define IMX5_CLK_AXI_A 7 |
||||
#define IMX5_CLK_AXI_B 8 |
||||
#define IMX5_CLK_UART_PRED 9 |
||||
#define IMX5_CLK_UART_ROOT 10 |
||||
#define IMX5_CLK_ESDHC_A_PRED 11 |
||||
#define IMX5_CLK_ESDHC_B_PRED 12 |
||||
#define IMX5_CLK_ESDHC_C_SEL 13 |
||||
#define IMX5_CLK_ESDHC_D_SEL 14 |
||||
#define IMX5_CLK_EMI_SEL 15 |
||||
#define IMX5_CLK_EMI_SLOW_PODF 16 |
||||
#define IMX5_CLK_NFC_PODF 17 |
||||
#define IMX5_CLK_ECSPI_PRED 18 |
||||
#define IMX5_CLK_ECSPI_PODF 19 |
||||
#define IMX5_CLK_USBOH3_PRED 20 |
||||
#define IMX5_CLK_USBOH3_PODF 21 |
||||
#define IMX5_CLK_USB_PHY_PRED 22 |
||||
#define IMX5_CLK_USB_PHY_PODF 23 |
||||
#define IMX5_CLK_CPU_PODF 24 |
||||
#define IMX5_CLK_DI_PRED 25 |
||||
#define IMX5_CLK_TVE_SEL 27 |
||||
#define IMX5_CLK_UART1_IPG_GATE 28 |
||||
#define IMX5_CLK_UART1_PER_GATE 29 |
||||
#define IMX5_CLK_UART2_IPG_GATE 30 |
||||
#define IMX5_CLK_UART2_PER_GATE 31 |
||||
#define IMX5_CLK_UART3_IPG_GATE 32 |
||||
#define IMX5_CLK_UART3_PER_GATE 33 |
||||
#define IMX5_CLK_I2C1_GATE 34 |
||||
#define IMX5_CLK_I2C2_GATE 35 |
||||
#define IMX5_CLK_GPT_IPG_GATE 36 |
||||
#define IMX5_CLK_PWM1_IPG_GATE 37 |
||||
#define IMX5_CLK_PWM1_HF_GATE 38 |
||||
#define IMX5_CLK_PWM2_IPG_GATE 39 |
||||
#define IMX5_CLK_PWM2_HF_GATE 40 |
||||
#define IMX5_CLK_GPT_HF_GATE 41 |
||||
#define IMX5_CLK_FEC_GATE 42 |
||||
#define IMX5_CLK_USBOH3_PER_GATE 43 |
||||
#define IMX5_CLK_ESDHC1_IPG_GATE 44 |
||||
#define IMX5_CLK_ESDHC2_IPG_GATE 45 |
||||
#define IMX5_CLK_ESDHC3_IPG_GATE 46 |
||||
#define IMX5_CLK_ESDHC4_IPG_GATE 47 |
||||
#define IMX5_CLK_SSI1_IPG_GATE 48 |
||||
#define IMX5_CLK_SSI2_IPG_GATE 49 |
||||
#define IMX5_CLK_SSI3_IPG_GATE 50 |
||||
#define IMX5_CLK_ECSPI1_IPG_GATE 51 |
||||
#define IMX5_CLK_ECSPI1_PER_GATE 52 |
||||
#define IMX5_CLK_ECSPI2_IPG_GATE 53 |
||||
#define IMX5_CLK_ECSPI2_PER_GATE 54 |
||||
#define IMX5_CLK_CSPI_IPG_GATE 55 |
||||
#define IMX5_CLK_SDMA_GATE 56 |
||||
#define IMX5_CLK_EMI_SLOW_GATE 57 |
||||
#define IMX5_CLK_IPU_SEL 58 |
||||
#define IMX5_CLK_IPU_GATE 59 |
||||
#define IMX5_CLK_NFC_GATE 60 |
||||
#define IMX5_CLK_IPU_DI1_GATE 61 |
||||
#define IMX5_CLK_VPU_SEL 62 |
||||
#define IMX5_CLK_VPU_GATE 63 |
||||
#define IMX5_CLK_VPU_REFERENCE_GATE 64 |
||||
#define IMX5_CLK_UART4_IPG_GATE 65 |
||||
#define IMX5_CLK_UART4_PER_GATE 66 |
||||
#define IMX5_CLK_UART5_IPG_GATE 67 |
||||
#define IMX5_CLK_UART5_PER_GATE 68 |
||||
#define IMX5_CLK_TVE_GATE 69 |
||||
#define IMX5_CLK_TVE_PRED 70 |
||||
#define IMX5_CLK_ESDHC1_PER_GATE 71 |
||||
#define IMX5_CLK_ESDHC2_PER_GATE 72 |
||||
#define IMX5_CLK_ESDHC3_PER_GATE 73 |
||||
#define IMX5_CLK_ESDHC4_PER_GATE 74 |
||||
#define IMX5_CLK_USB_PHY_GATE 75 |
||||
#define IMX5_CLK_HSI2C_GATE 76 |
||||
#define IMX5_CLK_MIPI_HSC1_GATE 77 |
||||
#define IMX5_CLK_MIPI_HSC2_GATE 78 |
||||
#define IMX5_CLK_MIPI_ESC_GATE 79 |
||||
#define IMX5_CLK_MIPI_HSP_GATE 80 |
||||
#define IMX5_CLK_LDB_DI1_DIV_3_5 81 |
||||
#define IMX5_CLK_LDB_DI1_DIV 82 |
||||
#define IMX5_CLK_LDB_DI0_DIV_3_5 83 |
||||
#define IMX5_CLK_LDB_DI0_DIV 84 |
||||
#define IMX5_CLK_LDB_DI1_GATE 85 |
||||
#define IMX5_CLK_CAN2_SERIAL_GATE 86 |
||||
#define IMX5_CLK_CAN2_IPG_GATE 87 |
||||
#define IMX5_CLK_I2C3_GATE 88 |
||||
#define IMX5_CLK_LP_APM 89 |
||||
#define IMX5_CLK_PERIPH_APM 90 |
||||
#define IMX5_CLK_MAIN_BUS 91 |
||||
#define IMX5_CLK_AHB_MAX 92 |
||||
#define IMX5_CLK_AIPS_TZ1 93 |
||||
#define IMX5_CLK_AIPS_TZ2 94 |
||||
#define IMX5_CLK_TMAX1 95 |
||||
#define IMX5_CLK_TMAX2 96 |
||||
#define IMX5_CLK_TMAX3 97 |
||||
#define IMX5_CLK_SPBA 98 |
||||
#define IMX5_CLK_UART_SEL 99 |
||||
#define IMX5_CLK_ESDHC_A_SEL 100 |
||||
#define IMX5_CLK_ESDHC_B_SEL 101 |
||||
#define IMX5_CLK_ESDHC_A_PODF 102 |
||||
#define IMX5_CLK_ESDHC_B_PODF 103 |
||||
#define IMX5_CLK_ECSPI_SEL 104 |
||||
#define IMX5_CLK_USBOH3_SEL 105 |
||||
#define IMX5_CLK_USB_PHY_SEL 106 |
||||
#define IMX5_CLK_IIM_GATE 107 |
||||
#define IMX5_CLK_USBOH3_GATE 108 |
||||
#define IMX5_CLK_EMI_FAST_GATE 109 |
||||
#define IMX5_CLK_IPU_DI0_GATE 110 |
||||
#define IMX5_CLK_GPC_DVFS 111 |
||||
#define IMX5_CLK_PLL1_SW 112 |
||||
#define IMX5_CLK_PLL2_SW 113 |
||||
#define IMX5_CLK_PLL3_SW 114 |
||||
#define IMX5_CLK_IPU_DI0_SEL 115 |
||||
#define IMX5_CLK_IPU_DI1_SEL 116 |
||||
#define IMX5_CLK_TVE_EXT_SEL 117 |
||||
#define IMX5_CLK_MX51_MIPI 118 |
||||
#define IMX5_CLK_PLL4_SW 119 |
||||
#define IMX5_CLK_LDB_DI1_SEL 120 |
||||
#define IMX5_CLK_DI_PLL4_PODF 121 |
||||
#define IMX5_CLK_LDB_DI0_SEL 122 |
||||
#define IMX5_CLK_LDB_DI0_GATE 123 |
||||
#define IMX5_CLK_USB_PHY1_GATE 124 |
||||
#define IMX5_CLK_USB_PHY2_GATE 125 |
||||
#define IMX5_CLK_PER_LP_APM 126 |
||||
#define IMX5_CLK_PER_PRED1 127 |
||||
#define IMX5_CLK_PER_PRED2 128 |
||||
#define IMX5_CLK_PER_PODF 129 |
||||
#define IMX5_CLK_PER_ROOT 130 |
||||
#define IMX5_CLK_SSI_APM 131 |
||||
#define IMX5_CLK_SSI1_ROOT_SEL 132 |
||||
#define IMX5_CLK_SSI2_ROOT_SEL 133 |
||||
#define IMX5_CLK_SSI3_ROOT_SEL 134 |
||||
#define IMX5_CLK_SSI_EXT1_SEL 135 |
||||
#define IMX5_CLK_SSI_EXT2_SEL 136 |
||||
#define IMX5_CLK_SSI_EXT1_COM_SEL 137 |
||||
#define IMX5_CLK_SSI_EXT2_COM_SEL 138 |
||||
#define IMX5_CLK_SSI1_ROOT_PRED 139 |
||||
#define IMX5_CLK_SSI1_ROOT_PODF 140 |
||||
#define IMX5_CLK_SSI2_ROOT_PRED 141 |
||||
#define IMX5_CLK_SSI2_ROOT_PODF 142 |
||||
#define IMX5_CLK_SSI_EXT1_PRED 143 |
||||
#define IMX5_CLK_SSI_EXT1_PODF 144 |
||||
#define IMX5_CLK_SSI_EXT2_PRED 145 |
||||
#define IMX5_CLK_SSI_EXT2_PODF 146 |
||||
#define IMX5_CLK_SSI1_ROOT_GATE 147 |
||||
#define IMX5_CLK_SSI2_ROOT_GATE 148 |
||||
#define IMX5_CLK_SSI3_ROOT_GATE 149 |
||||
#define IMX5_CLK_SSI_EXT1_GATE 150 |
||||
#define IMX5_CLK_SSI_EXT2_GATE 151 |
||||
#define IMX5_CLK_EPIT1_IPG_GATE 152 |
||||
#define IMX5_CLK_EPIT1_HF_GATE 153 |
||||
#define IMX5_CLK_EPIT2_IPG_GATE 154 |
||||
#define IMX5_CLK_EPIT2_HF_GATE 155 |
||||
#define IMX5_CLK_CAN_SEL 156 |
||||
#define IMX5_CLK_CAN1_SERIAL_GATE 157 |
||||
#define IMX5_CLK_CAN1_IPG_GATE 158 |
||||
#define IMX5_CLK_OWIRE_GATE 159 |
||||
#define IMX5_CLK_GPU3D_SEL 160 |
||||
#define IMX5_CLK_GPU2D_SEL 161 |
||||
#define IMX5_CLK_GPU3D_GATE 162 |
||||
#define IMX5_CLK_GPU2D_GATE 163 |
||||
#define IMX5_CLK_GARB_GATE 164 |
||||
#define IMX5_CLK_CKO1_SEL 165 |
||||
#define IMX5_CLK_CKO1_PODF 166 |
||||
#define IMX5_CLK_CKO1 167 |
||||
#define IMX5_CLK_CKO2_SEL 168 |
||||
#define IMX5_CLK_CKO2_PODF 169 |
||||
#define IMX5_CLK_CKO2 170 |
||||
#define IMX5_CLK_SRTC_GATE 171 |
||||
#define IMX5_CLK_PATA_GATE 172 |
||||
#define IMX5_CLK_SATA_GATE 173 |
||||
#define IMX5_CLK_SPDIF_XTAL_SEL 174 |
||||
#define IMX5_CLK_SPDIF0_SEL 175 |
||||
#define IMX5_CLK_SPDIF1_SEL 176 |
||||
#define IMX5_CLK_SPDIF0_PRED 177 |
||||
#define IMX5_CLK_SPDIF0_PODF 178 |
||||
#define IMX5_CLK_SPDIF1_PRED 179 |
||||
#define IMX5_CLK_SPDIF1_PODF 180 |
||||
#define IMX5_CLK_SPDIF0_COM_SEL 181 |
||||
#define IMX5_CLK_SPDIF1_COM_SEL 182 |
||||
#define IMX5_CLK_SPDIF0_GATE 183 |
||||
#define IMX5_CLK_SPDIF1_GATE 184 |
||||
#define IMX5_CLK_SPDIF_IPG_GATE 185 |
||||
#define IMX5_CLK_OCRAM 186 |
||||
#define IMX5_CLK_SAHARA_IPG_GATE 187 |
||||
#define IMX5_CLK_SATA_REF 188 |
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#define IMX5_CLK_STEP_SEL 189 |
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#define IMX5_CLK_CPU_PODF_SEL 190 |
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#define IMX5_CLK_ARM 191 |
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#define IMX5_CLK_FIRI_PRED 192 |
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#define IMX5_CLK_FIRI_SEL 193 |
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#define IMX5_CLK_FIRI_PODF 194 |
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#define IMX5_CLK_FIRI_SERIAL_GATE 195 |
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#define IMX5_CLK_FIRI_IPG_GATE 196 |
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#define IMX5_CLK_CSI0_MCLK1_PRED 197 |
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#define IMX5_CLK_CSI0_MCLK1_SEL 198 |
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#define IMX5_CLK_CSI0_MCLK1_PODF 199 |
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#define IMX5_CLK_CSI0_MCLK1_GATE 200 |
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#define IMX5_CLK_IEEE1588_PRED 201 |
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#define IMX5_CLK_IEEE1588_SEL 202 |
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#define IMX5_CLK_IEEE1588_PODF 203 |
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#define IMX5_CLK_IEEE1588_GATE 204 |
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#define IMX5_CLK_END 205 |
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|
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#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ |
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Reference in new issue