Import the Renesas R8A7794 DTS and headers from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
Marek Vasut
6 years ago
committed by
Marek Vasut
parent
92aa099592
commit
9a26fc5a73
@ -0,0 +1,414 @@ |
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/* |
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* Device Tree Source for the Alt board |
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* |
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* Copyright (C) 2014 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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/dts-v1/; |
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#include "r8a7794.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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|
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/ { |
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model = "Alt"; |
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compatible = "renesas,alt", "renesas,r8a7794"; |
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|
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aliases { |
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serial0 = &scif2; |
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i2c10 = &gpioi2c4; |
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i2c12 = &i2cexio4; |
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}; |
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|
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chosen { |
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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memory@40000000 { |
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device_type = "memory"; |
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reg = <0 0x40000000 0 0x40000000>; |
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}; |
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d3_3v: regulator-d3-3v { |
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compatible = "regulator-fixed"; |
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regulator-name = "D3.3V"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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vcc_sdhi0: regulator-vcc-sdhi0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "SDHI0 Vcc"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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vccq_sdhi0: regulator-vccq-sdhi0 { |
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compatible = "regulator-gpio"; |
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regulator-name = "SDHI0 VccQ"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; |
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gpios-states = <1>; |
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states = <3300000 1 |
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1800000 0>; |
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}; |
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vcc_sdhi1: regulator-vcc-sdhi1 { |
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compatible = "regulator-fixed"; |
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regulator-name = "SDHI1 Vcc"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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vccq_sdhi1: regulator-vccq-sdhi1 { |
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compatible = "regulator-gpio"; |
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regulator-name = "SDHI1 VccQ"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; |
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gpios-states = <1>; |
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states = <3300000 1 |
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1800000 0>; |
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}; |
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lbsc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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vga-encoder { |
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compatible = "adi,adv7123"; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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adv7123_in: endpoint { |
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remote-endpoint = <&du_out_rgb1>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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adv7123_out: endpoint { |
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remote-endpoint = <&vga_in>; |
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}; |
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}; |
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}; |
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}; |
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vga { |
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compatible = "vga-connector"; |
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port { |
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vga_in: endpoint { |
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remote-endpoint = <&adv7123_out>; |
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}; |
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}; |
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}; |
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x2_clk: x2-clock { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <74250000>; |
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}; |
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x13_clk: x13-clock { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <148500000>; |
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}; |
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gpioi2c4: i2c-10 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "i2c-gpio"; |
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status = "disabled"; |
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gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */ |
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&gpio4 8 GPIO_ACTIVE_HIGH /* scl */ |
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>; |
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i2c-gpio,delay-us = <5>; |
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}; |
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/* |
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* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). |
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* A fallback to GPIO is provided. |
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*/ |
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i2cexio4: i2c-14 { |
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compatible = "i2c-demux-pinctrl"; |
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i2c-parent = <&i2c4>, <&gpioi2c4>; |
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i2c-bus-name = "i2c-exio4"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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&du { |
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pinctrl-0 = <&du_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, |
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<&x13_clk>, <&x2_clk>; |
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clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; |
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ports { |
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port@1 { |
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endpoint { |
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remote-endpoint = <&adv7123_in>; |
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}; |
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}; |
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}; |
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}; |
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&extal_clk { |
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clock-frequency = <20000000>; |
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}; |
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&pfc { |
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pinctrl-0 = <&scif_clk_pins>; |
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pinctrl-names = "default"; |
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du_pins: du { |
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groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; |
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function = "du1"; |
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}; |
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scif2_pins: scif2 { |
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groups = "scif2_data"; |
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function = "scif2"; |
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}; |
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scif_clk_pins: scif_clk { |
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groups = "scif_clk"; |
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function = "scif_clk"; |
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}; |
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ether_pins: ether { |
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groups = "eth_link", "eth_mdio", "eth_rmii"; |
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function = "eth"; |
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}; |
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phy1_pins: phy1 { |
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groups = "intc_irq8"; |
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function = "intc"; |
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}; |
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i2c1_pins: i2c1 { |
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groups = "i2c1"; |
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function = "i2c1"; |
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}; |
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i2c4_pins: i2c4 { |
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groups = "i2c4"; |
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function = "i2c4"; |
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}; |
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vin0_pins: vin0 { |
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groups = "vin0_data8", "vin0_clk"; |
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function = "vin0"; |
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}; |
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mmcif0_pins: mmcif0 { |
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groups = "mmc_data8", "mmc_ctrl"; |
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function = "mmc"; |
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}; |
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sdhi0_pins: sd0 { |
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groups = "sdhi0_data4", "sdhi0_ctrl"; |
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function = "sdhi0"; |
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power-source = <3300>; |
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}; |
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sdhi0_pins_uhs: sd0_uhs { |
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groups = "sdhi0_data4", "sdhi0_ctrl"; |
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function = "sdhi0"; |
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power-source = <1800>; |
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}; |
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sdhi1_pins: sd1 { |
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groups = "sdhi1_data4", "sdhi1_ctrl"; |
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function = "sdhi1"; |
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power-source = <3300>; |
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}; |
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sdhi1_pins_uhs: sd1_uhs { |
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groups = "sdhi1_data4", "sdhi1_ctrl"; |
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function = "sdhi1"; |
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power-source = <1800>; |
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}; |
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}; |
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&cmt0 { |
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status = "okay"; |
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}; |
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&pfc { |
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qspi_pins: qspi { |
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groups = "qspi_ctrl", "qspi_data4"; |
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function = "qspi"; |
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}; |
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}; |
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ðer { |
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pinctrl-0 = <ðer_pins &phy1_pins>; |
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pinctrl-names = "default"; |
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phy-handle = <&phy1>; |
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renesas,ether-link-active-low; |
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status = "okay"; |
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phy1: ethernet-phy@1 { |
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reg = <1>; |
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interrupt-parent = <&irqc0>; |
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>; |
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micrel,led-mode = <1>; |
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}; |
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}; |
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&mmcif0 { |
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pinctrl-0 = <&mmcif0_pins>; |
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pinctrl-names = "default"; |
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vmmc-supply = <&d3_3v>; |
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vqmmc-supply = <&d3_3v>; |
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bus-width = <8>; |
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non-removable; |
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status = "okay"; |
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}; |
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&sdhi0 { |
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pinctrl-0 = <&sdhi0_pins>; |
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pinctrl-1 = <&sdhi0_pins_uhs>; |
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pinctrl-names = "default", "state_uhs"; |
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vmmc-supply = <&vcc_sdhi0>; |
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vqmmc-supply = <&vccq_sdhi0>; |
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cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; |
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wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; |
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sd-uhs-sdr50; |
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sd-uhs-sdr104; |
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status = "okay"; |
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}; |
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&sdhi1 { |
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pinctrl-0 = <&sdhi1_pins>; |
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pinctrl-1 = <&sdhi1_pins_uhs>; |
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pinctrl-names = "default", "state_uhs"; |
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vmmc-supply = <&vcc_sdhi1>; |
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vqmmc-supply = <&vccq_sdhi1>; |
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cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; |
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wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; |
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sd-uhs-sdr50; |
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status = "okay"; |
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}; |
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&i2c1 { |
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pinctrl-0 = <&i2c1_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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clock-frequency = <400000>; |
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composite-in@20 { |
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compatible = "adi,adv7180"; |
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reg = <0x20>; |
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remote = <&vin0>; |
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port { |
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adv7180: endpoint { |
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bus-width = <8>; |
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remote-endpoint = <&vin0ep>; |
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}; |
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}; |
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}; |
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}; |
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&i2c4 { |
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pinctrl-0 = <&i2c4_pins>; |
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pinctrl-names = "i2c-exio4"; |
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}; |
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&vin0 { |
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status = "okay"; |
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pinctrl-0 = <&vin0_pins>; |
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pinctrl-names = "default"; |
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port { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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vin0ep: endpoint { |
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remote-endpoint = <&adv7180>; |
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bus-width = <8>; |
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}; |
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}; |
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}; |
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&scif2 { |
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pinctrl-0 = <&scif2_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&scif_clk { |
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clock-frequency = <14745600>; |
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}; |
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&qspi { |
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pinctrl-0 = <&qspi_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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flash@0 { |
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compatible = "spansion,s25fl512s", "jedec,spi-nor"; |
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reg = <0>; |
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spi-max-frequency = <30000000>; |
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spi-tx-bus-width = <4>; |
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spi-rx-bus-width = <4>; |
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spi-cpol; |
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spi-cpha; |
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m25p,fast-read; |
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partitions { |
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compatible = "fixed-partitions"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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partition@0 { |
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label = "loader"; |
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reg = <0x00000000 0x00040000>; |
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read-only; |
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}; |
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partition@40000 { |
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label = "system"; |
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reg = <0x00040000 0x00040000>; |
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read-only; |
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}; |
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partition@80000 { |
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label = "user"; |
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reg = <0x00080000 0x03f80000>; |
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}; |
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}; |
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}; |
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}; |
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@ -0,0 +1,460 @@ |
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/* |
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* Device Tree Source for the SILK board |
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* |
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* Copyright (C) 2014 Renesas Electronics Corporation |
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* Copyright (C) 2014-2015 Renesas Solutions Corp. |
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* Copyright (C) 2014-2015 Cogent Embedded, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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/* |
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* SSI-AK4643 |
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* |
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* SW1: 2-1: AK4643 |
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* 2-3: ADV7511 |
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* |
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* This command is required before playback/capture: |
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* |
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* amixer set "LINEOUT Mixer DACL" on |
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*/ |
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/dts-v1/; |
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#include "r8a7794.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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/ { |
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model = "SILK"; |
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compatible = "renesas,silk", "renesas,r8a7794"; |
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aliases { |
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serial0 = &scif2; |
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}; |
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chosen { |
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory@40000000 { |
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device_type = "memory"; |
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reg = <0 0x40000000 0 0x40000000>; |
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}; |
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d3_3v: regulator-d3-3v { |
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compatible = "regulator-fixed"; |
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regulator-name = "D3.3V"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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vcc_sdhi1: regulator-vcc-sdhi1 { |
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compatible = "regulator-fixed"; |
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regulator-name = "SDHI1 Vcc"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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vccq_sdhi1: regulator-vccq-sdhi1 { |
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compatible = "regulator-gpio"; |
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regulator-name = "SDHI1 VccQ"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; |
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gpios-states = <1>; |
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states = <3300000 1 |
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1800000 0>; |
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}; |
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vga-encoder { |
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compatible = "adi,adv7123"; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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adv7123_in: endpoint { |
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remote-endpoint = <&du_out_rgb1>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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adv7123_out: endpoint { |
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remote-endpoint = <&vga_in>; |
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}; |
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}; |
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}; |
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}; |
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hdmi-out { |
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compatible = "hdmi-connector"; |
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type = "a"; |
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port { |
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hdmi_con: endpoint { |
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remote-endpoint = <&adv7511_out>; |
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}; |
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}; |
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}; |
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vga { |
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compatible = "vga-connector"; |
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|
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port { |
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vga_in: endpoint { |
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remote-endpoint = <&adv7123_out>; |
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}; |
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}; |
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}; |
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x2_clk: x2-clock { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <148500000>; |
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}; |
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|
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x3_clk: x3-clock { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <74250000>; |
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}; |
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x9_clk: audio_clock { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <12288000>; |
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}; |
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sound { |
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compatible = "simple-audio-card"; |
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|
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simple-audio-card,format = "left_j"; |
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simple-audio-card,bitclock-master = <&soundcodec>; |
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simple-audio-card,frame-master = <&soundcodec>; |
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simple-audio-card,cpu { |
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sound-dai = <&rcar_sound>; |
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}; |
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soundcodec: simple-audio-card,codec { |
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sound-dai = <&ak4643>; |
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clocks = <&x9_clk>; |
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}; |
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}; |
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}; |
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|
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&extal_clk { |
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clock-frequency = <20000000>; |
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}; |
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&pfc { |
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pinctrl-0 = <&scif_clk_pins>; |
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pinctrl-names = "default"; |
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scif2_pins: scif2 { |
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groups = "scif2_data"; |
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function = "scif2"; |
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}; |
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scif_clk_pins: scif_clk { |
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groups = "scif_clk"; |
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function = "scif_clk"; |
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}; |
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ether_pins: ether { |
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groups = "eth_link", "eth_mdio", "eth_rmii"; |
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function = "eth"; |
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}; |
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phy1_pins: phy1 { |
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groups = "intc_irq8"; |
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function = "intc"; |
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}; |
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i2c1_pins: i2c1 { |
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groups = "i2c1"; |
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function = "i2c1"; |
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}; |
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|
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mmcif0_pins: mmcif0 { |
||||
groups = "mmc_data8", "mmc_ctrl"; |
||||
function = "mmc"; |
||||
}; |
||||
|
||||
sdhi1_pins: sd1 { |
||||
groups = "sdhi1_data4", "sdhi1_ctrl"; |
||||
function = "sdhi1"; |
||||
}; |
||||
|
||||
qspi_pins: qspi { |
||||
groups = "qspi_ctrl", "qspi_data4"; |
||||
function = "qspi"; |
||||
}; |
||||
|
||||
vin0_pins: vin0 { |
||||
groups = "vin0_data8", "vin0_clk"; |
||||
function = "vin0"; |
||||
}; |
||||
|
||||
usb0_pins: usb0 { |
||||
groups = "usb0"; |
||||
function = "usb0"; |
||||
}; |
||||
|
||||
usb1_pins: usb1 { |
||||
groups = "usb1"; |
||||
function = "usb1"; |
||||
}; |
||||
|
||||
du0_pins: du0 { |
||||
groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; |
||||
function = "du0"; |
||||
}; |
||||
|
||||
du1_pins: du1 { |
||||
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; |
||||
function = "du1"; |
||||
}; |
||||
|
||||
ssi_pins: sound { |
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; |
||||
function = "ssi"; |
||||
}; |
||||
|
||||
audio_clk_pins: audio_clk { |
||||
groups = "audio_clkc"; |
||||
function = "audio_clk"; |
||||
}; |
||||
}; |
||||
|
||||
&scif2 { |
||||
pinctrl-0 = <&scif2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif_clk { |
||||
clock-frequency = <14745600>; |
||||
}; |
||||
|
||||
ðer { |
||||
pinctrl-0 = <ðer_pins &phy1_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
phy-handle = <&phy1>; |
||||
renesas,ether-link-active-low; |
||||
status = "okay"; |
||||
|
||||
phy1: ethernet-phy@1 { |
||||
reg = <1>; |
||||
interrupt-parent = <&irqc0>; |
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>; |
||||
micrel,led-mode = <1>; |
||||
}; |
||||
}; |
||||
|
||||
&i2c1 { |
||||
pinctrl-0 = <&i2c1_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
clock-frequency = <400000>; |
||||
|
||||
ak4643: codec@12 { |
||||
compatible = "asahi-kasei,ak4643"; |
||||
#sound-dai-cells = <0>; |
||||
reg = <0x12>; |
||||
}; |
||||
|
||||
composite-in@20 { |
||||
compatible = "adi,adv7180"; |
||||
reg = <0x20>; |
||||
remote = <&vin0>; |
||||
|
||||
port { |
||||
adv7180: endpoint { |
||||
bus-width = <8>; |
||||
remote-endpoint = <&vin0ep>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
hdmi@39 { |
||||
compatible = "adi,adv7511w"; |
||||
reg = <0x39>; |
||||
interrupt-parent = <&gpio5>; |
||||
interrupts = <23 IRQ_TYPE_LEVEL_LOW>; |
||||
|
||||
adi,input-depth = <8>; |
||||
adi,input-colorspace = "rgb"; |
||||
adi,input-clock = "1x"; |
||||
adi,input-style = <1>; |
||||
adi,input-justification = "evenly"; |
||||
|
||||
ports { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
port@0 { |
||||
reg = <0>; |
||||
adv7511_in: endpoint { |
||||
remote-endpoint = <&du_out_rgb0>; |
||||
}; |
||||
}; |
||||
|
||||
port@1 { |
||||
reg = <1>; |
||||
adv7511_out: endpoint { |
||||
remote-endpoint = <&hdmi_con>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&mmcif0 { |
||||
pinctrl-0 = <&mmcif0_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
vmmc-supply = <&d3_3v>; |
||||
vqmmc-supply = <&d3_3v>; |
||||
bus-width = <8>; |
||||
non-removable; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi1 { |
||||
pinctrl-0 = <&sdhi1_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi1>; |
||||
vqmmc-supply = <&vccq_sdhi1>; |
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&qspi { |
||||
pinctrl-0 = <&qspi_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
|
||||
flash@0 { |
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor"; |
||||
reg = <0>; |
||||
spi-max-frequency = <30000000>; |
||||
spi-tx-bus-width = <4>; |
||||
spi-rx-bus-width = <4>; |
||||
spi-cpol; |
||||
spi-cpha; |
||||
m25p,fast-read; |
||||
|
||||
partitions { |
||||
compatible = "fixed-partitions"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
partition@0 { |
||||
label = "loader"; |
||||
reg = <0x00000000 0x00040000>; |
||||
read-only; |
||||
}; |
||||
partition@40000 { |
||||
label = "user"; |
||||
reg = <0x00040000 0x00400000>; |
||||
read-only; |
||||
}; |
||||
partition@440000 { |
||||
label = "flash"; |
||||
reg = <0x00440000 0x03bc0000>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
/* composite video input */ |
||||
&vin0 { |
||||
status = "okay"; |
||||
pinctrl-0 = <&vin0_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
port { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
vin0ep: endpoint { |
||||
remote-endpoint = <&adv7180>; |
||||
bus-width = <8>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&pci0 { |
||||
status = "okay"; |
||||
pinctrl-0 = <&usb0_pins>; |
||||
pinctrl-names = "default"; |
||||
}; |
||||
|
||||
&pci1 { |
||||
status = "okay"; |
||||
pinctrl-0 = <&usb1_pins>; |
||||
pinctrl-names = "default"; |
||||
}; |
||||
|
||||
&usbphy { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&du { |
||||
pinctrl-0 = <&du0_pins &du1_pins>; |
||||
pinctrl-names = "default"; |
||||
status = "okay"; |
||||
|
||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, |
||||
<&x2_clk>, <&x3_clk>; |
||||
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; |
||||
|
||||
ports { |
||||
port@0 { |
||||
endpoint { |
||||
remote-endpoint = <&adv7511_in>; |
||||
}; |
||||
}; |
||||
port@1 { |
||||
endpoint { |
||||
remote-endpoint = <&adv7123_in>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&rcar_sound { |
||||
pinctrl-0 = <&ssi_pins &audio_clk_pins>; |
||||
pinctrl-names = "default"; |
||||
status = "okay"; |
||||
|
||||
/* Single DAI */ |
||||
#sound-dai-cells = <0>; |
||||
|
||||
rcar_sound,dai { |
||||
dai0 { |
||||
playback = <&ssi0>; |
||||
capture = <&ssi1>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&ssi1 { |
||||
shared-pin; |
||||
}; |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,141 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation |
||||
* Copyright 2013 Ideas On Board SPRL |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ |
||||
#define __DT_BINDINGS_CLOCK_R8A7794_H__ |
||||
|
||||
/* CPG */ |
||||
#define R8A7794_CLK_MAIN 0 |
||||
#define R8A7794_CLK_PLL0 1 |
||||
#define R8A7794_CLK_PLL1 2 |
||||
#define R8A7794_CLK_PLL3 3 |
||||
#define R8A7794_CLK_LB 4 |
||||
#define R8A7794_CLK_QSPI 5 |
||||
#define R8A7794_CLK_SDH 6 |
||||
#define R8A7794_CLK_SD0 7 |
||||
#define R8A7794_CLK_RCAN 8 |
||||
|
||||
/* MSTP0 */ |
||||
#define R8A7794_CLK_MSIOF0 0 |
||||
|
||||
/* MSTP1 */ |
||||
#define R8A7794_CLK_VCP0 1 |
||||
#define R8A7794_CLK_VPC0 3 |
||||
#define R8A7794_CLK_TMU1 11 |
||||
#define R8A7794_CLK_3DG 12 |
||||
#define R8A7794_CLK_2DDMAC 15 |
||||
#define R8A7794_CLK_FDP1_0 19 |
||||
#define R8A7794_CLK_TMU3 21 |
||||
#define R8A7794_CLK_TMU2 22 |
||||
#define R8A7794_CLK_CMT0 24 |
||||
#define R8A7794_CLK_TMU0 25 |
||||
#define R8A7794_CLK_VSP1_DU0 28 |
||||
#define R8A7794_CLK_VSP1_S 31 |
||||
|
||||
/* MSTP2 */ |
||||
#define R8A7794_CLK_SCIFA2 2 |
||||
#define R8A7794_CLK_SCIFA1 3 |
||||
#define R8A7794_CLK_SCIFA0 4 |
||||
#define R8A7794_CLK_MSIOF2 5 |
||||
#define R8A7794_CLK_SCIFB0 6 |
||||
#define R8A7794_CLK_SCIFB1 7 |
||||
#define R8A7794_CLK_MSIOF1 8 |
||||
#define R8A7794_CLK_SCIFB2 16 |
||||
#define R8A7794_CLK_SYS_DMAC1 18 |
||||
#define R8A7794_CLK_SYS_DMAC0 19 |
||||
|
||||
/* MSTP3 */ |
||||
#define R8A7794_CLK_SDHI2 11 |
||||
#define R8A7794_CLK_SDHI1 12 |
||||
#define R8A7794_CLK_SDHI0 14 |
||||
#define R8A7794_CLK_MMCIF0 15 |
||||
#define R8A7794_CLK_IIC0 18 |
||||
#define R8A7794_CLK_IIC1 23 |
||||
#define R8A7794_CLK_CMT1 29 |
||||
#define R8A7794_CLK_USBDMAC0 30 |
||||
#define R8A7794_CLK_USBDMAC1 31 |
||||
|
||||
/* MSTP4 */ |
||||
#define R8A7794_CLK_IRQC 7 |
||||
#define R8A7794_CLK_INTC_SYS 8 |
||||
|
||||
/* MSTP5 */ |
||||
#define R8A7794_CLK_AUDIO_DMAC0 2 |
||||
#define R8A7794_CLK_PWM 23 |
||||
|
||||
/* MSTP7 */ |
||||
#define R8A7794_CLK_EHCI 3 |
||||
#define R8A7794_CLK_HSUSB 4 |
||||
#define R8A7794_CLK_HSCIF2 13 |
||||
#define R8A7794_CLK_SCIF5 14 |
||||
#define R8A7794_CLK_SCIF4 15 |
||||
#define R8A7794_CLK_HSCIF1 16 |
||||
#define R8A7794_CLK_HSCIF0 17 |
||||
#define R8A7794_CLK_SCIF3 18 |
||||
#define R8A7794_CLK_SCIF2 19 |
||||
#define R8A7794_CLK_SCIF1 20 |
||||
#define R8A7794_CLK_SCIF0 21 |
||||
#define R8A7794_CLK_DU1 23 |
||||
#define R8A7794_CLK_DU0 24 |
||||
|
||||
/* MSTP8 */ |
||||
#define R8A7794_CLK_VIN1 10 |
||||
#define R8A7794_CLK_VIN0 11 |
||||
#define R8A7794_CLK_ETHERAVB 12 |
||||
#define R8A7794_CLK_ETHER 13 |
||||
|
||||
/* MSTP9 */ |
||||
#define R8A7794_CLK_GPIO6 5 |
||||
#define R8A7794_CLK_GPIO5 7 |
||||
#define R8A7794_CLK_GPIO4 8 |
||||
#define R8A7794_CLK_GPIO3 9 |
||||
#define R8A7794_CLK_GPIO2 10 |
||||
#define R8A7794_CLK_GPIO1 11 |
||||
#define R8A7794_CLK_GPIO0 12 |
||||
#define R8A7794_CLK_RCAN1 15 |
||||
#define R8A7794_CLK_RCAN0 16 |
||||
#define R8A7794_CLK_QSPI_MOD 17 |
||||
#define R8A7794_CLK_I2C5 25 |
||||
#define R8A7794_CLK_I2C4 27 |
||||
#define R8A7794_CLK_I2C3 28 |
||||
#define R8A7794_CLK_I2C2 29 |
||||
#define R8A7794_CLK_I2C1 30 |
||||
#define R8A7794_CLK_I2C0 31 |
||||
|
||||
/* MSTP10 */ |
||||
#define R8A7794_CLK_SSI_ALL 5 |
||||
#define R8A7794_CLK_SSI9 6 |
||||
#define R8A7794_CLK_SSI8 7 |
||||
#define R8A7794_CLK_SSI7 8 |
||||
#define R8A7794_CLK_SSI6 9 |
||||
#define R8A7794_CLK_SSI5 10 |
||||
#define R8A7794_CLK_SSI4 11 |
||||
#define R8A7794_CLK_SSI3 12 |
||||
#define R8A7794_CLK_SSI2 13 |
||||
#define R8A7794_CLK_SSI1 14 |
||||
#define R8A7794_CLK_SSI0 15 |
||||
#define R8A7794_CLK_SCU_ALL 17 |
||||
#define R8A7794_CLK_SCU_DVC1 18 |
||||
#define R8A7794_CLK_SCU_DVC0 19 |
||||
#define R8A7794_CLK_SCU_CTU1_MIX1 20 |
||||
#define R8A7794_CLK_SCU_CTU0_MIX0 21 |
||||
#define R8A7794_CLK_SCU_SRC6 25 |
||||
#define R8A7794_CLK_SCU_SRC5 26 |
||||
#define R8A7794_CLK_SCU_SRC4 27 |
||||
#define R8A7794_CLK_SCU_SRC3 28 |
||||
#define R8A7794_CLK_SCU_SRC2 29 |
||||
#define R8A7794_CLK_SCU_SRC1 30 |
||||
|
||||
/* MSTP11 */ |
||||
#define R8A7794_CLK_SCIFA3 6 |
||||
#define R8A7794_CLK_SCIFA4 7 |
||||
#define R8A7794_CLK_SCIFA5 8 |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ |
||||
@ -0,0 +1,47 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ |
||||
#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ |
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h> |
||||
|
||||
/* r8a7794 CPG Core Clocks */ |
||||
#define R8A7794_CLK_Z2 0 |
||||
#define R8A7794_CLK_ZG 1 |
||||
#define R8A7794_CLK_ZTR 2 |
||||
#define R8A7794_CLK_ZTRD2 3 |
||||
#define R8A7794_CLK_ZT 4 |
||||
#define R8A7794_CLK_ZX 5 |
||||
#define R8A7794_CLK_ZS 6 |
||||
#define R8A7794_CLK_HP 7 |
||||
#define R8A7794_CLK_I 8 |
||||
#define R8A7794_CLK_B 9 |
||||
#define R8A7794_CLK_LB 10 |
||||
#define R8A7794_CLK_P 11 |
||||
#define R8A7794_CLK_CL 12 |
||||
#define R8A7794_CLK_CP 13 |
||||
#define R8A7794_CLK_M2 14 |
||||
#define R8A7794_CLK_ADSP 15 |
||||
#define R8A7794_CLK_ZB3 16 |
||||
#define R8A7794_CLK_ZB3D2 17 |
||||
#define R8A7794_CLK_DDR 18 |
||||
#define R8A7794_CLK_SDH 19 |
||||
#define R8A7794_CLK_SD0 20 |
||||
#define R8A7794_CLK_SD2 21 |
||||
#define R8A7794_CLK_SD3 22 |
||||
#define R8A7794_CLK_MMC0 23 |
||||
#define R8A7794_CLK_MP 24 |
||||
#define R8A7794_CLK_QSPI 25 |
||||
#define R8A7794_CLK_CPEX 26 |
||||
#define R8A7794_CLK_RCAN 27 |
||||
#define R8A7794_CLK_R 28 |
||||
#define R8A7794_CLK_OSC 29 |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */ |
||||
@ -0,0 +1,26 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Glider bvba |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; version 2 of the License. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__ |
||||
#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__ |
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits |
||||
* representing the power areas in the various Interrupt Registers |
||||
* (e.g. SYSCISR, Interrupt Status Register) |
||||
*/ |
||||
|
||||
#define R8A7794_PD_CA7_CPU0 5 |
||||
#define R8A7794_PD_CA7_CPU1 6 |
||||
#define R8A7794_PD_SH_4A 16 |
||||
#define R8A7794_PD_SGX 20 |
||||
#define R8A7794_PD_CA7_SCU 21 |
||||
|
||||
/* Always-on power area */ |
||||
#define R8A7794_PD_ALWAYS_ON 32 |
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */ |
||||
Loading…
Reference in new issue