Tom Rini
9 years ago
commit
9a6535e05f
@ -1,20 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#include "micro-support-card.h" |
||||
|
||||
void uniphier_smp_kick_all_cpus(void); |
||||
|
||||
int board_init(void) |
||||
{ |
||||
led_puts("Uboo"); |
||||
#ifdef CONFIG_ARM64 |
||||
uniphier_smp_kick_all_cpus(); |
||||
#endif |
||||
return 0; |
||||
} |
||||
@ -1,15 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#include "micro-support-card.h" |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
support_card_late_init(); |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,22 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "../init.h" |
||||
#include "../sc64-regs.h" |
||||
#include "pll.h" |
||||
|
||||
int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags); |
||||
unsigned int dram_freq = bd->dram_freq; |
||||
|
||||
uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2); |
||||
uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2); |
||||
uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,56 @@ |
||||
/*
|
||||
* Copyright (C) 2013-2014 Panasonic Corporation |
||||
* Copyright (C) 2015-2016 Socionext Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/err.h> |
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sc-regs.h" |
||||
|
||||
#undef DPLL_SSC_RATE_1PER |
||||
|
||||
int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
unsigned int dram_freq = bd->dram_freq; |
||||
u32 tmp; |
||||
|
||||
/*
|
||||
* Set Frequency |
||||
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) |
||||
* to FOUT (DPLLCTRL.bit[29:20]) |
||||
*/ |
||||
tmp = readl(SC_DPLLCTRL); |
||||
tmp &= ~0x000f0000; |
||||
switch (dram_freq) { |
||||
case 1333: |
||||
tmp |= 0x000d0000; |
||||
break; |
||||
case 1600: |
||||
tmp |= 0x000c0000; |
||||
break; |
||||
default: |
||||
pr_err("Unsupported frequency"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
#if defined(DPLL_SSC_RATE_1PER) |
||||
tmp &= ~SC_DPLLCTRL_SSC_RATE; |
||||
#else |
||||
tmp |= SC_DPLLCTRL_SSC_RATE; |
||||
#endif |
||||
writel(tmp, SC_DPLLCTRL); |
||||
|
||||
tmp = readl(SC_DPLLCTRL2); |
||||
tmp |= SC_DPLLCTRL2_NRSTDS; |
||||
writel(tmp, SC_DPLLCTRL2); |
||||
|
||||
/* Wait 500 usec until dpll gets stable */ |
||||
udelay(500); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* Copyright (C) 2013-2014 Panasonic Corporation |
||||
* Copyright (C) 2015-2016 Socionext Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/err.h> |
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sc-regs.h" |
||||
|
||||
#undef DPLL_SSC_RATE_1PER |
||||
|
||||
int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
unsigned int dram_freq = bd->dram_freq; |
||||
u32 tmp; |
||||
|
||||
/*
|
||||
* Set Frequency |
||||
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) |
||||
* to FOUT ( DPLLCTRL.bit[29:20] ) |
||||
*/ |
||||
tmp = readl(SC_DPLLCTRL); |
||||
tmp &= ~(0x000f0000); |
||||
switch (dram_freq) { |
||||
case 1333: |
||||
tmp |= 0x000d0000; |
||||
break; |
||||
case 1600: |
||||
tmp |= 0x000c0000; |
||||
break; |
||||
default: |
||||
pr_err("Unsupported frequency"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
/*
|
||||
* Set Moduration rate |
||||
* Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) |
||||
*/ |
||||
#if defined(DPLL_SSC_RATE_1PER) |
||||
tmp &= ~0x00008000; |
||||
#else |
||||
tmp |= 0x00008000; |
||||
#endif |
||||
writel(tmp, SC_DPLLCTRL); |
||||
|
||||
tmp = readl(SC_DPLLCTRL2); |
||||
tmp |= SC_DPLLCTRL2_NRSTDS; |
||||
writel(tmp, SC_DPLLCTRL2); |
||||
|
||||
/* Wait until dpll gets stable */ |
||||
udelay(500); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,62 @@ |
||||
/*
|
||||
* Copyright (C) 2013-2014 Panasonic Corporation |
||||
* Copyright (C) 2015-2016 Socionext Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sc-regs.h" |
||||
|
||||
int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
u32 tmp; |
||||
/*
|
||||
* Set DPLL SSC parameters for DPLLCTRL3 |
||||
* [23] DIVN_TEST 0x1 |
||||
* [22:16] DIVN 0x50 |
||||
* [10] FREFSEL_TEST 0x1 |
||||
* [9:8] FREFSEL 0x2 |
||||
* [4] ICPD_TEST 0x1 |
||||
* [3:0] ICPD 0xb |
||||
*/ |
||||
tmp = readl(SC_DPLLCTRL3); |
||||
tmp &= ~0x00ff0717; |
||||
tmp |= 0x00d0061b; |
||||
writel(tmp, SC_DPLLCTRL3); |
||||
|
||||
/*
|
||||
* Set DPLL SSC parameters for DPLLCTRL |
||||
* <-1%> <-2%> |
||||
* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) |
||||
* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) |
||||
*/ |
||||
tmp = readl(SC_DPLLCTRL); |
||||
tmp &= ~0x3ff07fff; |
||||
#ifdef DPLL_SSC_RATE_1PER |
||||
tmp |= 0x084018bf; |
||||
#else |
||||
tmp |= 0x084031a6; |
||||
#endif |
||||
writel(tmp, SC_DPLLCTRL); |
||||
|
||||
/*
|
||||
* Set DPLL SSC parameters for DPLLCTRL2 |
||||
* [31:29] SSC_STEP 0 |
||||
* [27] SSC_REG_REF 1 |
||||
* [26:20] SSC_M 79 (0x4f) |
||||
* [19:0] SSC_K 964689 (0xeb851) |
||||
*/ |
||||
tmp = readl(SC_DPLLCTRL2); |
||||
tmp &= ~0xefffffff; |
||||
tmp |= 0x0cfeb851; |
||||
writel(tmp, SC_DPLLCTRL2); |
||||
|
||||
/* Wait 500 usec until dpll gets stable */ |
||||
udelay(500); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,21 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2014 Panasonic Corporation |
||||
* Copyright (C) 2015-2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../sc-regs.h" |
||||
#include "pll.h" |
||||
|
||||
void uniphier_ld4_dpll_ssc_en(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
tmp = readl(SC_DPLLCTRL); |
||||
tmp |= SC_DPLLCTRL_SSC_EN; |
||||
writel(tmp, SC_DPLLCTRL); |
||||
} |
||||
@ -0,0 +1,123 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/bitops.h> |
||||
#include <linux/io.h> |
||||
#include <linux/sizes.h> |
||||
|
||||
#include "pll.h" |
||||
|
||||
/* PLL type: SSC */ |
||||
#define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0) |
||||
#define SC_PLLCTRL_SSC_EN BIT(31) |
||||
#define SC_PLLCTRL2_NRSTDS BIT(28) |
||||
#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) |
||||
|
||||
/* PLL type: VPLL27 */ |
||||
#define SC_VPLL27CTRL_WP BIT(0) |
||||
#define SC_VPLL27CTRL3_K_LD BIT(28) |
||||
|
||||
/* PLL type: DSPLL */ |
||||
#define SC_DSPLLCTRL2_K_LD BIT(28) |
||||
|
||||
int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, |
||||
unsigned int ssc_rate, unsigned int divn) |
||||
{ |
||||
void __iomem *base; |
||||
u32 tmp; |
||||
|
||||
base = ioremap(reg_base, SZ_16); |
||||
if (!base) |
||||
return -ENOMEM; |
||||
|
||||
if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { |
||||
tmp = readl(base); /* SSCPLLCTRL */ |
||||
tmp &= ~SC_PLLCTRL_SSC_DK_MASK; |
||||
tmp |= (487 * freq * ssc_rate / divn / 512) & |
||||
SC_PLLCTRL_SSC_DK_MASK; |
||||
writel(tmp, base); |
||||
|
||||
tmp = readl(base + 4); |
||||
tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; |
||||
tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK; |
||||
|
||||
udelay(50); |
||||
} |
||||
|
||||
tmp = readl(base + 4); /* SSCPLLCTRL2 */ |
||||
tmp |= SC_PLLCTRL2_NRSTDS; |
||||
writel(tmp, base + 4); |
||||
|
||||
iounmap(base); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) |
||||
{ |
||||
void __iomem *base; |
||||
u32 tmp; |
||||
|
||||
base = ioremap(reg_base, SZ_16); |
||||
if (!base) |
||||
return -ENOMEM; |
||||
|
||||
mdelay(1); |
||||
|
||||
tmp = readl(base); /* SSCPLLCTRL */ |
||||
tmp |= SC_PLLCTRL_SSC_EN; |
||||
writel(tmp, base); |
||||
|
||||
iounmap(base); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int uniphier_ld20_vpll27_init(unsigned long reg_base) |
||||
{ |
||||
void __iomem *base; |
||||
u32 tmp; |
||||
|
||||
base = ioremap(reg_base, SZ_16); |
||||
if (!base) |
||||
return -ENOMEM; |
||||
|
||||
tmp = readl(base); /* VPLL27CTRL */ |
||||
tmp |= SC_VPLL27CTRL_WP; /* write protect off */ |
||||
writel(tmp, base); |
||||
|
||||
tmp = readl(base + 8); /* VPLL27CTRL3 */ |
||||
tmp |= SC_VPLL27CTRL3_K_LD; |
||||
writel(tmp, base + 8); |
||||
|
||||
tmp = readl(base); /* VPLL27CTRL */ |
||||
tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */ |
||||
writel(tmp, base); |
||||
|
||||
iounmap(base); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int uniphier_ld20_dspll_init(unsigned long reg_base) |
||||
{ |
||||
void __iomem *base; |
||||
u32 tmp; |
||||
|
||||
base = ioremap(reg_base, SZ_16); |
||||
if (!base) |
||||
return -ENOMEM; |
||||
|
||||
tmp = readl(base + 8); /* DSPLLCTRL2 */ |
||||
tmp |= SC_DSPLLCTRL2_K_LD; |
||||
writel(tmp, base + 8); |
||||
|
||||
iounmap(base); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,40 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sc64-regs.h" |
||||
#include "pll.h" |
||||
|
||||
int uniphier_ld20_pll_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags); |
||||
|
||||
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); |
||||
/* do nothing for SPLL */ |
||||
uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); |
||||
uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); |
||||
uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); |
||||
uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); |
||||
|
||||
mdelay(1); |
||||
|
||||
if (dpll_ssc_rate > 0) { |
||||
uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); |
||||
uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); |
||||
uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); |
||||
} |
||||
|
||||
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); |
||||
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); |
||||
|
||||
uniphier_ld20_dspll_init(SC_VPLL8KCTRL); |
||||
uniphier_ld20_dspll_init(SC_A2PLLCTRL); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,14 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "../init.h" |
||||
#include "pll.h" |
||||
|
||||
void uniphier_sld3_pll_init(void) |
||||
{ |
||||
uniphier_ld4_dpll_ssc_en(); |
||||
} |
||||
@ -0,0 +1,21 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef MACH_PLL_H |
||||
#define MACH_PLL_H |
||||
|
||||
#define UNIPHIER_PLL_FREQ_DEFAULT (0) |
||||
|
||||
void uniphier_ld4_dpll_ssc_en(void); |
||||
|
||||
int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, |
||||
unsigned int ssc_rate, unsigned int divn); |
||||
int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base); |
||||
int uniphier_ld20_vpll27_init(unsigned long reg_base); |
||||
int uniphier_ld20_dspll_init(unsigned long reg_base); |
||||
|
||||
#endif /* MACH_PLL_H */ |
||||
@ -1,41 +1,55 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _DDRPHY_LD20_REGS_H |
||||
#define _DDRPHY_LD20_REGS_H |
||||
|
||||
#define PHY_SCL_DATA_0 0x00000104 |
||||
#define PHY_SCL_DATA_1 0x00000108 |
||||
#define PHY_SCL_LATENCY 0x0000010C |
||||
#define PHY_SCL_START 0x00000100 |
||||
#define PHY_SCL_CONFIG_1 0x00000118 |
||||
#define PHY_SCL_CONFIG_2 0x0000011C |
||||
#define PHY_PAD_CTRL 0x00000120 |
||||
#define PHY_DLL_RECALIB 0x00000124 |
||||
#define PHY_DLL_ADRCTRL 0x00000128 |
||||
#define PHY_LANE_SEL 0x0000012C |
||||
#define PHY_DLL_TRIM_1 0x00000130 |
||||
#define PHY_DLL_TRIM_2 0x00000134 |
||||
#define PHY_DLL_TRIM_3 0x00000138 |
||||
#define PHY_SCL_MAIN_CLK_DELTA 0x00000140 |
||||
#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C |
||||
#define PHY_WRLVL_DYN_ODT 0x00000150 |
||||
#define PHY_WRLVL_ON_OFF 0x00000154 |
||||
#define PHY_UNQ_ANALOG_DLL_1 0x0000015C |
||||
#define PHY_DLL_INCR_TRIM_1 0x00000164 |
||||
#define PHY_DLL_INCR_TRIM_3 0x00000168 |
||||
#define PHY_SCL_CONFIG_3 0x0000016C |
||||
#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170 |
||||
#define PHY_SCL_START_ADDR 0x00000188 |
||||
#define PHY_DSCL_CNT 0x0000019C |
||||
#define PHY_DLL_TRIM_CLK 0x000001A4 |
||||
#define PHY_DYNAMIC_BIT_LVL 0x000001AC |
||||
#define PHY_SCL_WINDOW_TRIM 0x000001B4 |
||||
#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8 |
||||
#define PHY_SCL_CONFIG_4 0x000001BC |
||||
#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0 |
||||
#define PHY_VREF_TRAINING 0x000001C8 |
||||
#define PHY_SCL_GATE_TIMING 0x000001E0 |
||||
#define PHY_REG_SHIFT 2 |
||||
|
||||
#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT)) |
||||
#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT)) |
||||
#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT)) |
||||
#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT)) |
||||
#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT)) |
||||
#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT)) |
||||
#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT)) |
||||
#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT)) |
||||
#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT)) |
||||
#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT)) |
||||
#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT)) |
||||
#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT)) |
||||
#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT)) |
||||
#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT)) |
||||
#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT)) |
||||
#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT)) |
||||
#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT)) |
||||
#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT)) |
||||
|
||||
/* MASK */ |
||||
#define MSK_OP_DQ_DM_DQS_BITWISE_TRIM 0x0000007F |
||||
#define MSK_IP_DQ_DQS_BITWISE_TRIM 0x0000007F |
||||
#define MSK_OVERRIDE 0x00000080 |
||||
|
||||
#define PHY_BITLVL_DLY_WIDTH 6 |
||||
|
||||
#endif /* _DDRPHY_LD20_REGS_H */ |
||||
|
||||
@ -1,13 +0,0 @@ |
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o
|
||||
@ -1,7 +0,0 @@ |
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o
|
||||
@ -1,32 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
/* Comment format: PAD Name -> Function Name */ |
||||
sg_set_pinsel(0, 0, 8, 4); /* XECS1 -> XECS1 */ |
||||
sg_set_pinsel(1, 0, 8, 4); /* ERXW -> ERXW */ |
||||
sg_set_pinsel(2, 0, 8, 4); /* XERWE1 -> XERWE1 */ |
||||
sg_set_pinsel(6, 2, 8, 4); /* XNFRE -> XERWE0 */ |
||||
sg_set_pinsel(7, 2, 8, 4); /* XNFWE -> ES0 */ |
||||
sg_set_pinsel(8, 2, 8, 4); /* NFALE -> ES1 */ |
||||
sg_set_pinsel(9, 2, 8, 4); /* NFCLE -> ES2 */ |
||||
sg_set_pinsel(10, 2, 8, 4); /* NFD0 -> ED0 */ |
||||
sg_set_pinsel(11, 2, 8, 4); /* NFD1 -> ED1 */ |
||||
sg_set_pinsel(12, 2, 8, 4); /* NFD2 -> ED2 */ |
||||
sg_set_pinsel(13, 2, 8, 4); /* NFD3 -> ED3 */ |
||||
sg_set_pinsel(14, 2, 8, 4); /* NFD4 -> ED4 */ |
||||
sg_set_pinsel(15, 2, 8, 4); /* NFD5 -> ED5 */ |
||||
sg_set_pinsel(16, 2, 8, 4); /* NFD6 -> ED6 */ |
||||
sg_set_pinsel(17, 2, 8, 4); /* NFD7 -> ED7 */ |
||||
sg_set_iectrl_range(0, 2); |
||||
sg_set_iectrl_range(6, 17); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,28 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
/* Comment format: PAD Name -> Function Name */ |
||||
|
||||
#ifdef CONFIG_UNIPHIER_SERIAL |
||||
sg_set_pinsel(63, 0, 4, 4); /* RXD0 */ |
||||
sg_set_pinsel(64, 1, 4, 4); /* TXD0 */ |
||||
|
||||
sg_set_pinsel(65, 0, 4, 4); /* RXD1 */ |
||||
sg_set_pinsel(66, 1, 4, 4); /* TXD1 */ |
||||
|
||||
sg_set_pinsel(96, 2, 4, 4); /* RXD2 */ |
||||
sg_set_pinsel(102, 2, 4, 4); /* TXD2 */ |
||||
#endif |
||||
|
||||
sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */ |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,32 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/err.h> |
||||
#include <dm/device.h> |
||||
#include <dm/pinctrl.h> |
||||
#include <dm/uclass.h> |
||||
|
||||
#include "init.h" |
||||
|
||||
int uniphier_pin_init(const char *pinconfig_name) |
||||
{ |
||||
struct udevice *pctldev, *config, *next; |
||||
int ret; |
||||
|
||||
ret = uclass_first_device(UCLASS_PINCTRL, &pctldev); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
device_foreach_child_safe(config, next, pctldev) { |
||||
if (strcmp(config->name, pinconfig_name)) |
||||
continue; |
||||
|
||||
return pinctrl_generic_set_state(pctldev, config); |
||||
} |
||||
|
||||
return -ENODEV; |
||||
} |
||||
@ -1,13 +0,0 @@ |
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pinctrl-sld3.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pinctrl-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pinctrl-pro4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o
|
||||
@ -1,51 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
void uniphier_ld20_pin_init(void) |
||||
{ |
||||
/* Comment format: PAD Name -> Function Name */ |
||||
|
||||
#ifdef CONFIG_NAND_DENALI |
||||
sg_set_pinsel(3, 0, 8, 4); /* XNFWP -> XNFWP */ |
||||
sg_set_pinsel(4, 0, 8, 4); /* XNFCE0 -> XNFCE0 */ |
||||
sg_set_pinsel(5, 0, 8, 4); /* NFRYBY0 -> NFRYBY0 */ |
||||
sg_set_pinsel(6, 0, 8, 4); /* XNFRE -> XNFRE */ |
||||
sg_set_pinsel(7, 0, 8, 4); /* XNFWE -> XNFWE */ |
||||
sg_set_pinsel(8, 0, 8, 4); /* NFALE -> NFALE */ |
||||
sg_set_pinsel(9, 0, 8, 4); /* NFCLE -> NFCLE */ |
||||
sg_set_pinsel(10, 0, 8, 4); /* NFD0 -> NFD0 */ |
||||
sg_set_pinsel(11, 0, 8, 4); /* NFD1 -> NFD1 */ |
||||
sg_set_pinsel(12, 0, 8, 4); /* NFD2 -> NFD2 */ |
||||
sg_set_pinsel(13, 0, 8, 4); /* NFD3 -> NFD3 */ |
||||
sg_set_pinsel(14, 0, 8, 4); /* NFD4 -> NFD4 */ |
||||
sg_set_pinsel(15, 0, 8, 4); /* NFD5 -> NFD5 */ |
||||
sg_set_pinsel(16, 0, 8, 4); /* NFD6 -> NFD6 */ |
||||
sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */ |
||||
sg_set_iectrl_range(3, 17); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_XHCI_UNIPHIER |
||||
sg_set_pinsel(46, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ |
||||
sg_set_pinsel(47, 0, 8, 4); /* USB0OD -> USB0OD */ |
||||
sg_set_pinsel(48, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ |
||||
sg_set_pinsel(49, 0, 8, 4); /* USB1OD -> USB1OD */ |
||||
sg_set_pinsel(50, 0, 8, 4); /* USB2VBUS -> USB2VBUS */ |
||||
sg_set_pinsel(51, 0, 8, 4); /* USB2OD -> USB2OD */ |
||||
sg_set_pinsel(52, 0, 8, 4); /* USB3VBUS -> USB3VBUS */ |
||||
sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */ |
||||
sg_set_iectrl_range(46, 53); |
||||
#endif |
||||
|
||||
sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ |
||||
sg_set_iectrl(149); |
||||
sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ |
||||
sg_set_iectrl(153); |
||||
} |
||||
@ -1,41 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
void uniphier_ld4_pin_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* Comment format: PAD Name -> Function Name */ |
||||
|
||||
#ifdef CONFIG_NAND_DENALI |
||||
sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */ |
||||
sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */ |
||||
sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */ |
||||
sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */ |
||||
sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */ |
||||
sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */ |
||||
sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */ |
||||
sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */ |
||||
sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */ |
||||
sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */ |
||||
sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */ |
||||
sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */ |
||||
sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */ |
||||
sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */ |
||||
sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */ |
||||
sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */ |
||||
sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */ |
||||
#endif |
||||
|
||||
tmp = readl(SG_IECTRL); |
||||
tmp |= 0x41; |
||||
writel(tmp, SG_IECTRL); |
||||
} |
||||
@ -1,46 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
void uniphier_ld6b_pin_init(void) |
||||
{ |
||||
/* Comment format: PAD Name -> Function Name */ |
||||
|
||||
#ifdef CONFIG_NAND_DENALI |
||||
sg_set_pinsel(30, 0, 8, 4); /* XNFRE -> XNFRE */ |
||||
sg_set_pinsel(31, 0, 8, 4); /* XNFWE -> XNFWE */ |
||||
sg_set_pinsel(32, 0, 8, 4); /* NFALE -> NFALE */ |
||||
sg_set_pinsel(33, 0, 8, 4); /* NFCLE -> NFCLE */ |
||||
sg_set_pinsel(34, 0, 8, 4); /* XNFWP -> XNFWP */ |
||||
sg_set_pinsel(35, 0, 8, 4); /* XNFCE0 -> XNFCE0 */ |
||||
sg_set_pinsel(36, 0, 8, 4); /* NRYBY0 -> NRYBY0 */ |
||||
sg_set_pinsel(37, 0, 8, 4); /* XNFCE1 -> NRYBY1 */ |
||||
sg_set_pinsel(38, 0, 8, 4); /* NRYBY1 -> XNFCE1 */ |
||||
sg_set_pinsel(39, 0, 8, 4); /* NFD0 -> NFD0 */ |
||||
sg_set_pinsel(40, 0, 8, 4); /* NFD1 -> NFD1 */ |
||||
sg_set_pinsel(41, 0, 8, 4); /* NFD2 -> NFD2 */ |
||||
sg_set_pinsel(42, 0, 8, 4); /* NFD3 -> NFD3 */ |
||||
sg_set_pinsel(43, 0, 8, 4); /* NFD4 -> NFD4 */ |
||||
sg_set_pinsel(44, 0, 8, 4); /* NFD5 -> NFD5 */ |
||||
sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */ |
||||
sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_XHCI_UNIPHIER |
||||
sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ |
||||
sg_set_pinsel(57, 0, 8, 4); /* USB0OD -> USB0OD */ |
||||
sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ |
||||
sg_set_pinsel(59, 0, 8, 4); /* USB1OD -> USB1OD */ |
||||
sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */ |
||||
sg_set_pinsel(61, 0, 8, 4); /* USB2OD -> USB2OD */ |
||||
sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */ |
||||
sg_set_pinsel(63, 0, 8, 4); /* USB3OD -> USB3OD */ |
||||
#endif |
||||
} |
||||
@ -1,44 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
void uniphier_pro4_pin_init(void) |
||||
{ |
||||
/* Comment format: PAD Name -> Function Name */ |
||||
|
||||
#ifdef CONFIG_NAND_DENALI |
||||
sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */ |
||||
sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */ |
||||
sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */ |
||||
sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */ |
||||
sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */ |
||||
sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */ |
||||
sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */ |
||||
sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */ |
||||
sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */ |
||||
sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */ |
||||
sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */ |
||||
sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */ |
||||
sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */ |
||||
sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ |
||||
sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ |
||||
/* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */ |
||||
/* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_XHCI_UNIPHIER |
||||
sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ |
||||
sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */ |
||||
sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ |
||||
sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */ |
||||
#endif |
||||
|
||||
writel(1, SG_LOADPINCTRL); |
||||
} |
||||
@ -1,44 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
void uniphier_pro5_pin_init(void) |
||||
{ |
||||
/* Comment format: PAD Name -> Function Name */ |
||||
|
||||
#ifdef CONFIG_NAND_DENALI |
||||
sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */ |
||||
sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */ |
||||
sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */ |
||||
sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */ |
||||
sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */ |
||||
sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ |
||||
sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ |
||||
sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */ |
||||
sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */ |
||||
sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */ |
||||
sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */ |
||||
sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */ |
||||
sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */ |
||||
sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */ |
||||
sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */ |
||||
sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */ |
||||
sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_XHCI_UNIPHIER |
||||
sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ |
||||
sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */ |
||||
sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ |
||||
sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */ |
||||
#endif |
||||
|
||||
writel(1, SG_LOADPINCTRL); |
||||
} |
||||
@ -1,46 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
void uniphier_pxs2_pin_init(void) |
||||
{ |
||||
/* Comment format: PAD Name -> Function Name */ |
||||
|
||||
#ifdef CONFIG_NAND_DENALI |
||||
sg_set_pinsel(30, 8, 8, 4); /* XNFRE -> XNFRE */ |
||||
sg_set_pinsel(31, 8, 8, 4); /* XNFWE -> XNFWE */ |
||||
sg_set_pinsel(32, 8, 8, 4); /* NFALE -> NFALE */ |
||||
sg_set_pinsel(33, 8, 8, 4); /* NFCLE -> NFCLE */ |
||||
sg_set_pinsel(34, 8, 8, 4); /* XNFWP -> XNFWP */ |
||||
sg_set_pinsel(35, 8, 8, 4); /* XNFCE0 -> XNFCE0 */ |
||||
sg_set_pinsel(36, 8, 8, 4); /* NRYBY0 -> NRYBY0 */ |
||||
sg_set_pinsel(37, 8, 8, 4); /* XNFCE1 -> NRYBY1 */ |
||||
sg_set_pinsel(38, 8, 8, 4); /* NRYBY1 -> XNFCE1 */ |
||||
sg_set_pinsel(39, 8, 8, 4); /* NFD0 -> NFD0 */ |
||||
sg_set_pinsel(40, 8, 8, 4); /* NFD1 -> NFD1 */ |
||||
sg_set_pinsel(41, 8, 8, 4); /* NFD2 -> NFD2 */ |
||||
sg_set_pinsel(42, 8, 8, 4); /* NFD3 -> NFD3 */ |
||||
sg_set_pinsel(43, 8, 8, 4); /* NFD4 -> NFD4 */ |
||||
sg_set_pinsel(44, 8, 8, 4); /* NFD5 -> NFD5 */ |
||||
sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */ |
||||
sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USB_XHCI_UNIPHIER |
||||
sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */ |
||||
sg_set_pinsel(57, 8, 8, 4); /* USB0OD -> USB0OD */ |
||||
sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */ |
||||
sg_set_pinsel(59, 8, 8, 4); /* USB1OD -> USB1OD */ |
||||
sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */ |
||||
sg_set_pinsel(61, 8, 8, 4); /* USB2OD -> USB2OD */ |
||||
sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */ |
||||
sg_set_pinsel(63, 8, 8, 4); /* USB3OD -> USB3OD */ |
||||
#endif |
||||
} |
||||
@ -1,48 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
void uniphier_sld3_pin_init(void) |
||||
{ |
||||
#ifdef CONFIG_USB_EHCI |
||||
sg_set_pinsel(13, 0, 4, 4); /* USB0OC */ |
||||
sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */ |
||||
|
||||
sg_set_pinsel(15, 0, 4, 4); /* USB1OC */ |
||||
sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */ |
||||
|
||||
sg_set_pinsel(17, 0, 4, 4); /* USB2OC */ |
||||
sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */ |
||||
|
||||
sg_set_pinsel(19, 0, 4, 4); /* USB3OC */ |
||||
sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_NAND_DENALI |
||||
sg_set_pinsel(38, 1, 4, 4); /* NFALE_GB, NFCLE_GB */ |
||||
sg_set_pinsel(39, 1, 4, 4); /* XNFRYBY0_GB */ |
||||
sg_set_pinsel(40, 1, 4, 4); /* XNFCE0_GB, XNFRE_GB, XNFWE_GB, XNFWP_GB */ |
||||
sg_set_pinsel(41, 1, 4, 4); /* XNFRYBY1_GB, XNFCE1_GB */ |
||||
sg_set_pinsel(58, 1, 4, 4); /* NFD[0-3]_GB */ |
||||
sg_set_pinsel(59, 1, 4, 4); /* NFD[4-7]_GB */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MMC_UNIPHIER |
||||
/* eMMC */ |
||||
sg_set_pinsel(55, 1, 4, 4); /* XERST */ |
||||
sg_set_pinsel(56, 1, 4, 4); /* MMCDAT[0-3] */ |
||||
sg_set_pinsel(57, 1, 4, 4); /* MMCDAT[4-7] */ |
||||
sg_set_pinsel(60, 1, 4, 4); /* MMCCLK, MMCCMD */ |
||||
|
||||
/* SD card */ |
||||
sg_set_pinsel(42, 1, 4, 4); /* SD1CLK, SD1CMD, SD1DAT[0-3] */ |
||||
sg_set_pinsel(43, 1, 4, 4); /* SD1CD */ |
||||
sg_set_pinsel(44, 1, 4, 4); /* SD1WP */ |
||||
sg_set_pinsel(45, 1, 4, 4); /* SDVTCG */ |
||||
#endif |
||||
} |
||||
@ -1,35 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
void uniphier_sld8_pin_init(void) |
||||
{ |
||||
/* Comment format: PAD Name -> Function Name */ |
||||
|
||||
#ifdef CONFIG_NAND_DENALI |
||||
sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */ |
||||
sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */ |
||||
sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */ |
||||
sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */ |
||||
sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */ |
||||
sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */ |
||||
sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */ |
||||
sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */ |
||||
sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */ |
||||
sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */ |
||||
sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */ |
||||
sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */ |
||||
sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */ |
||||
sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */ |
||||
sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */ |
||||
sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */ |
||||
sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */ |
||||
#endif |
||||
} |
||||
@ -1,8 +0,0 @@ |
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pll-init-sld3.o pll-spectrum-sld3.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-init-ld4.o pll-spectrum-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pll-init-pro4.o pll-spectrum-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-init-sld8.o pll-spectrum-ld4.o
|
||||
@ -1,205 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sc-regs.h" |
||||
#include "../sg-regs.h" |
||||
|
||||
static void dpll_init(void) |
||||
{ |
||||
u32 tmp; |
||||
/*
|
||||
* Set DPLL SSC parameters for DPLLCTRL3 |
||||
* [23] DIVN_TEST 0x1 |
||||
* [22:16] DIVN 0x50 |
||||
* [10] FREFSEL_TEST 0x1 |
||||
* [9:8] FREFSEL 0x2 |
||||
* [4] ICPD_TEST 0x1 |
||||
* [3:0] ICPD 0xb |
||||
*/ |
||||
tmp = readl(SC_DPLLCTRL3); |
||||
tmp &= ~0x00ff0717; |
||||
tmp |= 0x00d0061b; |
||||
writel(tmp, SC_DPLLCTRL3); |
||||
|
||||
/*
|
||||
* Set DPLL SSC parameters for DPLLCTRL |
||||
* <-1%> <-2%> |
||||
* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) |
||||
* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) |
||||
*/ |
||||
tmp = readl(SC_DPLLCTRL); |
||||
tmp &= ~0x3ff07fff; |
||||
#ifdef CONFIG_DPLL_SSC_RATE_1PER |
||||
tmp |= 0x084018bf; |
||||
#else |
||||
tmp |= 0x084031a6; |
||||
#endif |
||||
writel(tmp, SC_DPLLCTRL); |
||||
|
||||
/*
|
||||
* Set DPLL SSC parameters for DPLLCTRL2 |
||||
* [31:29] SSC_STEP 0 |
||||
* [27] SSC_REG_REF 1 |
||||
* [26:20] SSC_M 79 (0x4f) |
||||
* [19:0] SSC_K 964689 (0xeb851) |
||||
*/ |
||||
tmp = readl(SC_DPLLCTRL2); |
||||
tmp &= ~0xefffffff; |
||||
tmp |= 0x0cfeb851; |
||||
writel(tmp, SC_DPLLCTRL2); |
||||
} |
||||
|
||||
static void upll_init(void) |
||||
{ |
||||
u32 tmp, clk_mode_upll, clk_mode_axosel; |
||||
|
||||
tmp = readl(SG_PINMON0); |
||||
clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; |
||||
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; |
||||
|
||||
/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ |
||||
tmp = readl(SC_UPLLCTRL); |
||||
tmp &= ~0x18000000; |
||||
writel(tmp, SC_UPLLCTRL); |
||||
|
||||
if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { |
||||
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || |
||||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { |
||||
/* AXO: 25MHz */ |
||||
tmp &= ~0x07ffffff; |
||||
tmp |= 0x0228f5c0; |
||||
} else { |
||||
/* AXO: default 24.576MHz */ |
||||
tmp &= ~0x07ffffff; |
||||
tmp |= 0x02328000; |
||||
} |
||||
} |
||||
|
||||
writel(tmp, SC_UPLLCTRL); |
||||
|
||||
/* set 1 to K_LD(UPLLCTRL.bit[27]) */ |
||||
tmp |= 0x08000000; |
||||
writel(tmp, SC_UPLLCTRL); |
||||
|
||||
/* wait 10 usec */ |
||||
udelay(10); |
||||
|
||||
/* set 1 to SNRT(UPLLCTRL.bit[28]) */ |
||||
tmp |= 0x10000000; |
||||
writel(tmp, SC_UPLLCTRL); |
||||
} |
||||
|
||||
static void vpll_init(void) |
||||
{ |
||||
u32 tmp, clk_mode_axosel; |
||||
|
||||
tmp = readl(SG_PINMON0); |
||||
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; |
||||
|
||||
/* set 1 to VPLA27WP and VPLA27WP */ |
||||
tmp = readl(SC_VPLL27ACTRL); |
||||
tmp |= 0x00000001; |
||||
writel(tmp, SC_VPLL27ACTRL); |
||||
tmp = readl(SC_VPLL27BCTRL); |
||||
tmp |= 0x00000001; |
||||
writel(tmp, SC_VPLL27BCTRL); |
||||
|
||||
/* Set 0 to VPLA_K_LD and VPLB_K_LD */ |
||||
tmp = readl(SC_VPLL27ACTRL3); |
||||
tmp &= ~0x10000000; |
||||
writel(tmp, SC_VPLL27ACTRL3); |
||||
tmp = readl(SC_VPLL27BCTRL3); |
||||
tmp &= ~0x10000000; |
||||
writel(tmp, SC_VPLL27BCTRL3); |
||||
|
||||
/* Set 0 to VPLA_SNRST and VPLB_SNRST */ |
||||
tmp = readl(SC_VPLL27ACTRL2); |
||||
tmp &= ~0x10000000; |
||||
writel(tmp, SC_VPLL27ACTRL2); |
||||
tmp = readl(SC_VPLL27BCTRL2); |
||||
tmp &= ~0x10000000; |
||||
writel(tmp, SC_VPLL27BCTRL2); |
||||
|
||||
/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ |
||||
tmp = readl(SC_VPLL27ACTRL2); |
||||
tmp &= ~0x0000007f; |
||||
tmp |= 0x00000020; |
||||
writel(tmp, SC_VPLL27ACTRL2); |
||||
tmp = readl(SC_VPLL27BCTRL2); |
||||
tmp &= ~0x0000007f; |
||||
tmp |= 0x00000020; |
||||
writel(tmp, SC_VPLL27BCTRL2); |
||||
|
||||
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || |
||||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { |
||||
/* AXO: 25MHz */ |
||||
tmp = readl(SC_VPLL27ACTRL3); |
||||
tmp &= ~0x000fffff; |
||||
tmp |= 0x00066664; |
||||
writel(tmp, SC_VPLL27ACTRL3); |
||||
tmp = readl(SC_VPLL27BCTRL3); |
||||
tmp &= ~0x000fffff; |
||||
tmp |= 0x00066664; |
||||
writel(tmp, SC_VPLL27BCTRL3); |
||||
} else { |
||||
/* AXO: default 24.576MHz */ |
||||
tmp = readl(SC_VPLL27ACTRL3); |
||||
tmp &= ~0x000fffff; |
||||
tmp |= 0x000f5800; |
||||
writel(tmp, SC_VPLL27ACTRL3); |
||||
tmp = readl(SC_VPLL27BCTRL3); |
||||
tmp &= ~0x000fffff; |
||||
tmp |= 0x000f5800; |
||||
writel(tmp, SC_VPLL27BCTRL3); |
||||
} |
||||
|
||||
/* Set 1 to VPLA_K_LD and VPLB_K_LD */ |
||||
tmp = readl(SC_VPLL27ACTRL3); |
||||
tmp |= 0x10000000; |
||||
writel(tmp, SC_VPLL27ACTRL3); |
||||
tmp = readl(SC_VPLL27BCTRL3); |
||||
tmp |= 0x10000000; |
||||
writel(tmp, SC_VPLL27BCTRL3); |
||||
|
||||
/* wait 10 usec */ |
||||
udelay(10); |
||||
|
||||
/* Set 0 to VPLA_SNRST and VPLB_SNRST */ |
||||
tmp = readl(SC_VPLL27ACTRL2); |
||||
tmp |= 0x10000000; |
||||
writel(tmp, SC_VPLL27ACTRL2); |
||||
tmp = readl(SC_VPLL27BCTRL2); |
||||
tmp |= 0x10000000; |
||||
writel(tmp, SC_VPLL27BCTRL2); |
||||
|
||||
/* set 0 to VPLA27WP and VPLA27WP */ |
||||
tmp = readl(SC_VPLL27ACTRL); |
||||
tmp &= ~0x00000001; |
||||
writel(tmp, SC_VPLL27ACTRL); |
||||
tmp = readl(SC_VPLL27BCTRL); |
||||
tmp |= ~0x00000001; |
||||
writel(tmp, SC_VPLL27BCTRL); |
||||
} |
||||
|
||||
int uniphier_sld8_pll_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
dpll_init(); |
||||
upll_init(); |
||||
vpll_init(); |
||||
|
||||
/*
|
||||
* Wait 500 usec until dpll get stable |
||||
* We wait 10 usec in upll_init() and vpll_init() |
||||
* so 20 usec can be saved here. |
||||
*/ |
||||
udelay(480); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,21 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sc-regs.h" |
||||
|
||||
int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
tmp = readl(SC_DPLLCTRL); |
||||
tmp |= SC_DPLLCTRL_SSC_EN; |
||||
writel(tmp, SC_DPLLCTRL); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,22 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "../sc-regs.h" |
||||
|
||||
int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
tmp = readl(SC_DPLLCTRL); |
||||
tmp |= SC_DPLLCTRL_SSC_EN; |
||||
writel(tmp, SC_DPLLCTRL); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,12 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "micro-support-card.h" |
||||
|
||||
int misc_init_f(void) |
||||
{ |
||||
return check_support_card(); |
||||
} |
||||
@ -0,0 +1,128 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <dm/device.h> |
||||
#include <dm/pinctrl.h> |
||||
|
||||
#include "pinctrl-uniphier.h" |
||||
|
||||
static const unsigned emmc_pins[] = {55, 56, 60}; |
||||
static const int emmc_muxvals[] = {1, 1, 1}; |
||||
static const unsigned emmc_dat8_pins[] = {57}; |
||||
static const int emmc_dat8_muxvals[] = {1}; |
||||
static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112, |
||||
113}; |
||||
static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2}; |
||||
static const unsigned ether_rmii_pins[] = {35}; |
||||
static const int ether_rmii_muxvals[] = {1}; |
||||
static const unsigned i2c0_pins[] = {36}; |
||||
static const int i2c0_muxvals[] = {0}; |
||||
static const unsigned nand_pins[] = {38, 39, 40, 58, 59}; |
||||
static const int nand_muxvals[] = {1, 1, 1, 1, 1}; |
||||
static const unsigned nand_cs1_pins[] = {41}; |
||||
static const int nand_cs1_muxvals[] = {1}; |
||||
static const unsigned sd_pins[] = {42, 43, 44, 45}; |
||||
static const int sd_muxvals[] = {1, 1, 1, 1}; |
||||
static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76, |
||||
77, 78, 79, 80, 88, 89, 91, 92, 99}; |
||||
static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
||||
1, 1, 1, 1, 1}; |
||||
static const unsigned system_bus_cs0_pins[] = {93}; |
||||
static const int system_bus_cs0_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs1_pins[] = {94}; |
||||
static const int system_bus_cs1_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs2_pins[] = {95}; |
||||
static const int system_bus_cs2_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs3_pins[] = {96}; |
||||
static const int system_bus_cs3_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs4_pins[] = {81}; |
||||
static const int system_bus_cs4_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs5_pins[] = {82}; |
||||
static const int system_bus_cs5_muxvals[] = {1}; |
||||
static const unsigned uart0_pins[] = {63, 64}; |
||||
static const int uart0_muxvals[] = {0, 1}; |
||||
static const unsigned uart1_pins[] = {65, 66}; |
||||
static const int uart1_muxvals[] = {0, 1}; |
||||
static const unsigned uart2_pins[] = {96, 102}; |
||||
static const int uart2_muxvals[] = {2, 2}; |
||||
static const unsigned usb0_pins[] = {13, 14}; |
||||
static const int usb0_muxvals[] = {0, 1}; |
||||
static const unsigned usb1_pins[] = {15, 16}; |
||||
static const int usb1_muxvals[] = {0, 1}; |
||||
static const unsigned usb2_pins[] = {17, 18}; |
||||
static const int usb2_muxvals[] = {0, 1}; |
||||
static const unsigned usb3_pins[] = {19, 20}; |
||||
static const int usb3_muxvals[] = {0, 1}; |
||||
|
||||
static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = { |
||||
UNIPHIER_PINCTRL_GROUP_SPL(emmc), |
||||
UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8), |
||||
UNIPHIER_PINCTRL_GROUP(ether_mii), |
||||
UNIPHIER_PINCTRL_GROUP(ether_rmii), |
||||
UNIPHIER_PINCTRL_GROUP(i2c0), |
||||
UNIPHIER_PINCTRL_GROUP(nand), |
||||
UNIPHIER_PINCTRL_GROUP(nand_cs1), |
||||
UNIPHIER_PINCTRL_GROUP(sd), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs0), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs1), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs2), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs3), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs4), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs5), |
||||
UNIPHIER_PINCTRL_GROUP_SPL(uart0), |
||||
UNIPHIER_PINCTRL_GROUP_SPL(uart1), |
||||
UNIPHIER_PINCTRL_GROUP_SPL(uart2), |
||||
UNIPHIER_PINCTRL_GROUP(usb0), |
||||
UNIPHIER_PINCTRL_GROUP(usb1), |
||||
UNIPHIER_PINCTRL_GROUP(usb2), |
||||
UNIPHIER_PINCTRL_GROUP(usb3) |
||||
}; |
||||
|
||||
static const char * const uniphier_sld3_functions[] = { |
||||
UNIPHIER_PINMUX_FUNCTION_SPL(emmc), |
||||
UNIPHIER_PINMUX_FUNCTION(ether_mii), |
||||
UNIPHIER_PINMUX_FUNCTION(ether_rmii), |
||||
UNIPHIER_PINMUX_FUNCTION(i2c0), |
||||
UNIPHIER_PINMUX_FUNCTION(nand), |
||||
UNIPHIER_PINMUX_FUNCTION(sd), |
||||
UNIPHIER_PINMUX_FUNCTION(system_bus), |
||||
UNIPHIER_PINMUX_FUNCTION_SPL(uart0), |
||||
UNIPHIER_PINMUX_FUNCTION_SPL(uart1), |
||||
UNIPHIER_PINMUX_FUNCTION_SPL(uart2), |
||||
UNIPHIER_PINMUX_FUNCTION(usb0), |
||||
UNIPHIER_PINMUX_FUNCTION(usb1), |
||||
UNIPHIER_PINMUX_FUNCTION(usb2), |
||||
UNIPHIER_PINMUX_FUNCTION(usb3), |
||||
}; |
||||
|
||||
static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = { |
||||
.groups = uniphier_sld3_groups, |
||||
.groups_count = ARRAY_SIZE(uniphier_sld3_groups), |
||||
.functions = uniphier_sld3_functions, |
||||
.functions_count = ARRAY_SIZE(uniphier_sld3_functions), |
||||
.caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT, |
||||
}; |
||||
|
||||
static int uniphier_sld3_pinctrl_probe(struct udevice *dev) |
||||
{ |
||||
return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata); |
||||
} |
||||
|
||||
static const struct udevice_id uniphier_sld3_pinctrl_match[] = { |
||||
{ .compatible = "socionext,uniphier-sld3-pinctrl" }, |
||||
{ /* sentinel */ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(uniphier_sld3_pinctrl) = { |
||||
.name = "uniphier-sld3-pinctrl", |
||||
.id = UCLASS_PINCTRL, |
||||
.of_match = of_match_ptr(uniphier_sld3_pinctrl_match), |
||||
.probe = uniphier_sld3_pinctrl_probe, |
||||
.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), |
||||
.ops = &uniphier_pinctrl_ops, |
||||
}; |
||||
@ -1,85 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/err.h> |
||||
#include <linux/io.h> |
||||
#include <usb.h> |
||||
#include <fdtdec.h> |
||||
#include "xhci.h" |
||||
|
||||
static int get_uniphier_xhci_base(int index, struct xhci_hccr **base) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
int node_list[2]; |
||||
fdt_addr_t addr; |
||||
int count; |
||||
|
||||
count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb", |
||||
COMPAT_SOCIONEXT_XHCI, node_list, |
||||
ARRAY_SIZE(node_list)); |
||||
|
||||
if (index >= count) |
||||
return -ENODEV; |
||||
|
||||
addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg"); |
||||
if (addr == FDT_ADDR_T_NONE) |
||||
return -ENODEV; |
||||
|
||||
*base = (struct xhci_hccr *)addr; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#define USB3_RST_CTRL 0x00100040 |
||||
#define IOMMU_RST_N (1 << 5) |
||||
#define LINK_RST_N (1 << 4) |
||||
|
||||
static void uniphier_xhci_reset(void __iomem *base, int on) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
tmp = readl(base + USB3_RST_CTRL); |
||||
|
||||
if (on) |
||||
tmp &= ~(IOMMU_RST_N | LINK_RST_N); |
||||
else |
||||
tmp |= IOMMU_RST_N | LINK_RST_N; |
||||
|
||||
writel(tmp, base + USB3_RST_CTRL); |
||||
} |
||||
|
||||
int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) |
||||
{ |
||||
int ret; |
||||
struct xhci_hccr *cr; |
||||
struct xhci_hcor *or; |
||||
|
||||
ret = get_uniphier_xhci_base(index, &cr); |
||||
if (ret < 0) |
||||
return ret; |
||||
|
||||
uniphier_xhci_reset(cr, 0); |
||||
|
||||
or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase)); |
||||
|
||||
*hccr = cr; |
||||
*hcor = or; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void xhci_hcd_stop(int index) |
||||
{ |
||||
int ret; |
||||
struct xhci_hccr *cr; |
||||
|
||||
ret = get_uniphier_xhci_base(index, &cr); |
||||
if (ret < 0) |
||||
return; |
||||
|
||||
uniphier_xhci_reset(cr, 1); |
||||
} |
||||
Loading…
Reference in new issue