Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>master
York Sun
12 years ago
parent
9a17eb5b7e
commit
9ac4ffbde1
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Derived from mpc85xx_ddr_gen3.c, removed all workarounds |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <fsl_ddr_sdram.h> |
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#include <asm/processor.h> |
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#include <fsl_immap.h> |
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#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) |
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#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL |
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#endif |
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/*
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* regs has the to-be-set values for DDR controller registers |
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* ctrl_num is the DDR controller number |
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* step: 0 goes through the initialization in one pass |
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* 1 sets registers and returns before enabling controller |
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* 2 resumes from step 1 and continues to initialize |
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* Dividing the initialization to two steps to deassert DDR reset signal |
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* to comply with JEDEC specs for RDIMMs. |
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*/ |
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void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, |
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unsigned int ctrl_num, int step) |
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{ |
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unsigned int i, bus_width; |
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struct ccsr_ddr __iomem *ddr; |
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u32 temp_sdram_cfg; |
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u32 total_gb_size_per_controller; |
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int timeout; |
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switch (ctrl_num) { |
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case 0: |
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ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
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break; |
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) |
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case 1: |
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ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; |
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break; |
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#endif |
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) |
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case 2: |
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ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; |
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break; |
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#endif |
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) |
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case 3: |
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ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; |
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break; |
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#endif |
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default: |
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printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); |
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return; |
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} |
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if (step == 2) |
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goto step2; |
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if (regs->ddr_eor) |
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out_be32(&ddr->eor, regs->ddr_eor); |
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
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if (i == 0) { |
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out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); |
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out_be32(&ddr->cs0_config, regs->cs[i].config); |
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out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); |
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} else if (i == 1) { |
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out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); |
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out_be32(&ddr->cs1_config, regs->cs[i].config); |
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out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); |
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} else if (i == 2) { |
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out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); |
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out_be32(&ddr->cs2_config, regs->cs[i].config); |
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out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); |
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} else if (i == 3) { |
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out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); |
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out_be32(&ddr->cs3_config, regs->cs[i].config); |
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out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); |
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} |
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} |
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out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); |
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out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); |
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out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); |
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); |
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out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); |
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out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); |
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out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); |
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out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); |
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out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); |
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out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); |
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out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); |
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out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); |
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out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); |
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out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); |
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); |
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out_be32(&ddr->sdram_data_init, regs->ddr_data_init); |
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out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); |
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out_be32(&ddr->init_addr, regs->ddr_init_addr); |
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out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); |
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out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); |
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out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); |
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out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); |
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out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); |
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#ifndef CONFIG_SYS_FSL_DDR_EMU |
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/*
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* Skip these two registers if running on emulator |
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* because emulator doesn't have skew between bytes. |
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*/ |
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if (regs->ddr_wrlvl_cntl_2) |
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out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); |
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if (regs->ddr_wrlvl_cntl_3) |
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out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); |
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#endif |
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out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); |
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out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); |
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out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); |
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out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); |
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out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); |
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out_be32(&ddr->err_disable, regs->err_disable); |
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out_be32(&ddr->err_int_en, regs->err_int_en); |
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for (i = 0; i < 32; i++) { |
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if (regs->debug[i]) { |
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debug("Write to debug_%d as %08x\n", i + 1, |
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regs->debug[i]); |
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out_be32(&ddr->debug[i], regs->debug[i]); |
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} |
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} |
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/*
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* For RDIMMs, JEDEC spec requires clocks to be stable before reset is |
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* deasserted. Clocks start when any chip select is enabled and clock |
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* control register is set. Because all DDR components are connected to |
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* one reset signal, this needs to be done in two steps. Step 1 is to |
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* get the clocks started. Step 2 resumes after reset signal is |
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* deasserted. |
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*/ |
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if (step == 1) { |
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udelay(200); |
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return; |
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} |
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step2: |
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/* Set, but do not enable the memory */ |
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temp_sdram_cfg = regs->ddr_sdram_cfg; |
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temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); |
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg); |
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/*
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* 500 painful micro-seconds must elapse between |
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* the DDR clock setup and the DDR config enable. |
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* DDR2 need 200 us, and DDR3 need 500 us from spec, |
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* we choose the max, that is 500 us for all of case. |
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*/ |
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udelay(500); |
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asm volatile("dsb sy;isb"); |
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/* Let the controller go */ |
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temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; |
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); |
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asm volatile("dsb sy;isb"); |
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total_gb_size_per_controller = 0; |
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { |
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if (!(regs->cs[i].config & 0x80000000)) |
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continue; |
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total_gb_size_per_controller += 1 << ( |
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((regs->cs[i].config >> 14) & 0x3) + 2 + |
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((regs->cs[i].config >> 8) & 0x7) + 12 + |
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((regs->cs[i].config >> 0) & 0x7) + 8 + |
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3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - |
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26); /* minus 26 (count of 64M) */ |
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} |
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if (regs->cs[0].config & 0x20000000) { |
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/* 2-way interleaving */ |
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total_gb_size_per_controller <<= 1; |
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} |
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/*
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* total memory / bus width = transactions needed |
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* transactions needed / data rate = seconds |
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* to add plenty of buffer, double the time |
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* For example, 2GB on 666MT/s 64-bit bus takes about 402ms |
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* Let's wait for 800ms |
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*/ |
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bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) |
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>> SDRAM_CFG_DBW_SHIFT); |
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timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / |
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(get_ddr_freq(0) >> 20)) << 1; |
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total_gb_size_per_controller >>= 4; /* shift down to gb size */ |
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debug("total %d GB\n", total_gb_size_per_controller); |
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debug("Need to wait up to %d * 10ms\n", timeout); |
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/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ |
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while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && |
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(timeout >= 0)) { |
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udelay(10000); /* throttle polling rate */ |
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timeout--; |
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} |
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if (timeout <= 0) |
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printf("Waiting for D_INIT timeout. Memory may not work.\n"); |
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} |
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