@ -31,13 +31,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY ( 0 , CONFIG_SYS_INIT_RAM_ADDR , CONFIG_SYS_INIT_RAM_ADDR ,
MAS3_SX | MAS3_SW | MAS3_SR , 0 ,
0 , 0 , BOOKE_PAGESZ_4K , 0 ) ,
SET_TLB_ENTRY ( 0 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
SET_TLB_ENTRY ( 0 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
MAS3_SX | MAS3_SW | MAS3_SR , 0 ,
0 , 0 , BOOKE_PAGESZ_4K , 0 ) ,
SET_TLB_ENTRY ( 0 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
SET_TLB_ENTRY ( 0 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
MAS3_SX | MAS3_SW | MAS3_SR , 0 ,
0 , 0 , BOOKE_PAGESZ_4K , 0 ) ,
SET_TLB_ENTRY ( 0 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
SET_TLB_ENTRY ( 0 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
MAS3_SX | MAS3_SW | MAS3_SR , 0 ,
0 , 0 , BOOKE_PAGESZ_4K , 0 ) ,
@ -62,7 +65,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2 : 256 M Non - cacheable , guarded
* 0x90000000 256 M PCI1 MEM Second half
*/
SET_TLB_ENTRY ( 1 , CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000 , CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000 ,
SET_TLB_ENTRY ( 1 , CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000 ,
CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000 ,
MAS3_SX | MAS3_SW | MAS3_SR , MAS2_I | MAS2_G ,
0 , 2 , BOOKE_PAGESZ_256M , 1 ) ,