Correct addessing errors in platform files. Split off common core module data from Integrator header files to include/armcoremodule.h. Patch by Peter Pearse, 04 Oct 2005master
Wolfgang Denk
19 years ago
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1820d4c73b
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9b880bd4d8
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/*
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* (C) Copyright 2005 |
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* ARM Ltd. |
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* Peter Pearse, <Peter.Pearse@arm.com> |
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* Configuration for ARM Core Modules. |
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* No standalonw port yet available |
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* - this file is included by both integratorap.h & integratorcp.h |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __ARMCOREMODULE_H |
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#define __ARMCOREMODULE_H |
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#define CM_BASE 0x10000000 |
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/* CM registers common to all CMs */ |
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/* Note that observed values after reboot into the ARM Boot Monitor
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have been used as defaults, rather than the POR values */ |
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#define OS_CTRL 0x0000000C |
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#define CMMASK_REMAP 0x00000005 /* set remap & led */ |
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#define CMMASK_RESET 0x00000008 |
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#define OS_LOCK 0x00000014 |
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#define CMVAL_LOCK1 0x0000A000 /* locking value */ |
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#define CMVAL_LOCK2 0x0000005F /* locking value */ |
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#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */ |
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#define OS_SDRAM 0x00000020 |
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#define OS_INIT 0x00000024 |
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#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ |
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#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ |
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#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */ |
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#define CMMASK_LE 0xFFFFFFF7 /* little endian */ |
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#define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */ |
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/* - observed reset value of */ |
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/* CM926EJ-S */ |
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/* CM1136-EJ-S */ |
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#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) |
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#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */ |
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/* - PLL test clock bypassed */ |
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/* - bus clock ratio 2 */ |
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/* - little endian */ |
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/* - vectors at zero */ |
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#endif /* CM1022xx */ |
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/* Determine CM characteristics */ |
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#undef CONFIG_CM_MULTIPLE_SSRAM |
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#undef CONFIG_CM_SPD_DETECT |
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#undef CONFIG_CM_REMAP |
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#undef CONFIG_CM_INIT |
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#undef CONFIG_CM_TCRAM |
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#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S) |
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#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */ |
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#endif |
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/* Excalibur core module has reduced functionality */ |
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#ifndef CONFIG_CM922T_XA10 |
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#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */ |
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#define OS_SPD 0x00000100 /* Address of SPD data */ |
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#define CONFIG_CM_REMAP /* CM supports remapping */ |
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#define CONFIG_CM_INIT /* CM has initialization reg */ |
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#endif /* NOT EXCALIBUR */ |
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#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \ |
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defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
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defined(CONFIG_CM1136JF_S) |
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#define CONFIG_CM_TCRAM /* CM has TCRAM */ |
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#endif |
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#ifdef CONFIG_CM_SPD_DETECT |
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#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */ |
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#endif |
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#endif /* __ARMCOREMODULE_H */ |
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