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@ -19,7 +19,10 @@ BOOT_FROM spi |
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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# Configure RGMII-0/1 interface pad voltage to 1.8V |
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DATA 0xFFD100e0 0x1b1b9b9b |
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DATA 0xFFD100e0 0x1b1b1b9b |
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DATA 0xFFD20134 0xbbbbbbbb |
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DATA 0xFFD20138 0x00bbbbbb |
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz |
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DATA 0xFFD01400 0x43000c30 # DDR Configuration register |
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@ -30,7 +33,7 @@ DATA 0xFFD01400 0x43000c30 # DDR Configuration register |
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# bit29-26: zero |
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# bit31-30: 01 |
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DATA 0xFFD01404 0x37543000 # DDR Controller Control Low |
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DATA 0xFFD01404 0x39543000 # DDR Controller Control Low |
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# bit 4: 0=addr/cmd in smame cycle |
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# bit 5: 0=clk is driven during self refresh, we don't care for APX |
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# bit 6: 0=use recommended falling edge of clk for addr/cmd |
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@ -52,14 +55,14 @@ DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) |
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# bit27-24: TRRD |
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# bit31-28: TRTP |
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DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) |
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DATA 0xFFD0140C 0x00000833 # DDR Timing (High) |
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# bit6-0: TRFC |
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# bit8-7: TR2R |
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# bit10-9: TR2W |
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# bit12-11: TW2W |
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# bit31-13: zero required |
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DATA 0xFFD01410 0x000000cc # DDR Address Control |
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DATA 0xFFD01410 0x0000000d # DDR Address Control |
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# bit1-0: 01, Cs0width=x8 |
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# bit3-2: 10, Cs0size=1Gb |
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# bit5-4: 01, Cs1width=x8 |
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@ -92,7 +95,7 @@ DATA 0xFFD0141C 0x00000C52 # DDR Mode |
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# bit12: 0, PD must be zero |
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# bit31-13: 0 required |
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DATA 0xFFD01420 0x00000040 # DDR Extended Mode |
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DATA 0xFFD01420 0x00000042 # DDR Extended Mode |
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# bit0: 0, DDR DLL enabled |
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# bit1: 0, DDR drive strenght normal |
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# bit2: 0, DDR ODT control lsd (disabled) |
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@ -104,7 +107,7 @@ DATA 0xFFD01420 0x00000040 # DDR Extended Mode |
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# bit12: 0, DDR output buffer enabled |
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# bit31-13: 0 required |
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DATA 0xFFD01424 0x0000F17F # DDR Controller Control High |
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DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High |
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# bit2-0: 111, required |
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# bit3 : 1 , MBUS Burst Chop disabled |
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# bit6-4: 111, required |
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@ -120,26 +123,28 @@ DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) |
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DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) |
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 |
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DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size |
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DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size |
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# bit0: 1, Window enabled |
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# bit1: 0, Write Protect disabled |
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# bit3-2: 00, CS0 hit selected |
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# bit23-4: ones, required |
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# bit31-24: 0x0F, Size (i.e. 256MB) |
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# bit31-24: 0x07, Size (i.e. 128MB) |
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DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb |
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DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 |
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DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled |
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DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb |
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
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DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb |
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
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DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) |
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DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low) |
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) |
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# bit1-0: 00, ODT0 controlled by ODT Control (low) register above |
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# bit3-2: 01, ODT1 active NEVER! |
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# bit31-4: zero, required |
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DATA 0xFFD0149C 0x0000E803 # CPU ODT Control |
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DATA 0xFFD0149C 0x0000F80F # CPU ODT Control |
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
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#bit0=1, enable DDR init upon this register write |
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