QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>master
Prabhakar Kushwaha
8 years ago
committed by
York Sun
parent
16dacb26a5
commit
9d044fcb8c
@ -0,0 +1,14 @@ |
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/* |
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* Copyright 2016 Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/dts-v1/; |
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#include "fsl-ls1012a-qds.dtsi" |
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|
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/ { |
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chosen { |
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stdout-path = &duart0; |
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}; |
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}; |
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@ -0,0 +1,123 @@ |
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/* |
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* Copyright 2016 Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/include/ "fsl-ls1012a.dtsi" |
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|
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/ { |
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model = "LS1012A QDS Board"; |
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aliases { |
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spi0 = &qspi; |
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spi1 = &dspi0; |
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}; |
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}; |
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|
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&dspi0 { |
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bus-num = <0>; |
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status = "okay"; |
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|
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dflash0: n25q128a { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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reg = <0>; |
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spi-max-frequency = <1000000>; /* input clock */ |
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}; |
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|
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dflash1: sst25wf040b { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <3500000>; |
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reg = <1>; |
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}; |
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|
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dflash2: en25s64 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <3500000>; |
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reg = <2>; |
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}; |
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}; |
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|
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&qspi { |
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bus-num = <0>; |
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status = "okay"; |
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|
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qflash0: s25fl128s@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <20000000>; |
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reg = <0>; |
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}; |
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}; |
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|
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&i2c0 { |
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status = "okay"; |
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pca9547@77 { |
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compatible = "philips,pca9547"; |
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reg = <0x77>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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i2c@0 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0>; |
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|
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rtc@68 { |
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compatible = "dallas,ds3232"; |
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reg = <0x68>; |
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/* IRQ10_B */ |
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interrupts = <0 150 0x4>; |
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}; |
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}; |
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|
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i2c@2 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x2>; |
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|
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ina220@40 { |
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compatible = "ti,ina220"; |
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reg = <0x40>; |
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shunt-resistor = <1000>; |
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}; |
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|
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ina220@41 { |
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compatible = "ti,ina220"; |
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reg = <0x41>; |
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shunt-resistor = <1000>; |
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}; |
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}; |
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|
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i2c@3 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x3>; |
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|
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eeprom@56 { |
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compatible = "at24,24c512"; |
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reg = <0x56>; |
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}; |
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|
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eeprom@57 { |
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compatible = "at24,24c512"; |
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reg = <0x57>; |
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}; |
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|
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adt7461a@4c { |
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compatible = "adt7461a"; |
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reg = <0x4c>; |
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}; |
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}; |
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}; |
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}; |
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|
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&duart0 { |
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status = "okay"; |
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}; |
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@ -0,0 +1,119 @@ |
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/* |
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* Copyright 2016 Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/include/ "skeleton64.dtsi" |
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/ { |
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compatible = "fsl,ls1012a"; |
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interrupt-parent = <&gic>; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x0>; |
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clocks = <&clockgen 1 0>; |
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}; |
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|
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}; |
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sysclk: sysclk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <100000000>; |
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clock-output-names = "sysclk"; |
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}; |
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gic: interrupt-controller@1400000 { |
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compatible = "arm,gic-400"; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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reg = <0x0 0x1401000 0 0x1000>, /* GICD */ |
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<0x0 0x1402000 0 0x2000>, /* GICC */ |
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<0x0 0x1404000 0 0x2000>, /* GICH */ |
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<0x0 0x1406000 0 0x2000>; /* GICV */ |
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interrupts = <1 9 0xf08>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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clockgen: clocking@1ee1000 { |
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compatible = "fsl,ls1012a-clockgen"; |
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reg = <0x0 0x1ee1000 0x0 0x1000>; |
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#clock-cells = <2>; |
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clocks = <&sysclk>; |
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}; |
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dspi0: dspi@2100000 { |
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compatible = "fsl,vf610-dspi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2100000 0x0 0x10000>; |
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interrupts = <0 64 0x4>; |
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clock-names = "dspi"; |
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clocks = <&clockgen 4 0>; |
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num-cs = <6>; |
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big-endian; |
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status = "disabled"; |
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}; |
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i2c0: i2c@2180000 { |
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compatible = "fsl,vf610-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2180000 0x0 0x10000>; |
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interrupts = <0 56 0x4>; |
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clock-names = "i2c"; |
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clocks = <&clockgen 4 0>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@2190000 { |
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compatible = "fsl,vf610-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2190000 0x0 0x10000>; |
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interrupts = <0 57 0x4>; |
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clock-names = "i2c"; |
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clocks = <&clockgen 4 0>; |
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status = "disabled"; |
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}; |
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duart0: serial@21c0500 { |
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compatible = "fsl,ns16550", "ns16550a"; |
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reg = <0x00 0x21c0500 0x0 0x100>; |
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interrupts = <0 54 0x4>; |
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clocks = <&clockgen 4 0>; |
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}; |
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duart1: serial@21c0600 { |
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compatible = "fsl,ns16550", "ns16550a"; |
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reg = <0x00 0x21c0600 0x0 0x100>; |
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interrupts = <0 54 0x4>; |
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clocks = <&clockgen 4 0>; |
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}; |
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qspi: quadspi@1550000 { |
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compatible = "fsl,vf610-qspi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x1550000 0x0 0x10000>, |
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<0x0 0x40000000 0x0 0x4000000>; |
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reg-names = "QuadSPI", "QuadSPI-memory"; |
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num-cs = <2>; |
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big-endian; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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@ -0,0 +1,15 @@ |
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if TARGET_LS1012AQDS |
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config SYS_BOARD |
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default "ls1012aqds" |
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config SYS_VENDOR |
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default "freescale" |
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config SYS_SOC |
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default "fsl-layerscape" |
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config SYS_CONFIG_NAME |
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default "ls1012aqds" |
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endif |
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@ -0,0 +1,6 @@ |
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LS1012AQDS BOARD |
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M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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S: Maintained |
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F: board/freescale/ls1012aqds/ |
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F: include/configs/ls1012aqds.h |
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F: configs/ls1012aqds_qspi_defconfig |
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@ -0,0 +1,7 @@ |
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#
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# Copyright 2016 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += ls1012aqds.o
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@ -0,0 +1,59 @@ |
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Overview |
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-------- |
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QorIQ LS1012A Development System (LS1012AQDS) is a high-performance |
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development platform, with a complete debugging environment. |
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The LS1012AQDS board supports the QorIQ LS1012A processor and is |
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optimized to support the high-bandwidth DDR3L memory and |
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a full complement of high-speed SerDes ports. |
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|
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LS1012A SoC Overview |
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-------------------- |
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A |
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SoC overview. |
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|
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LS1012AQDS board Overview |
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----------------------- |
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- SERDES Connections, 4 lanes supporting: |
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- PCI Express - 3.0 |
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- SGMII, SGMII 2.5 |
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- SATA 3.0 |
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- DDR Controller |
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- 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s |
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- QSPI Controller |
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- A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select |
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signals to QSPI NOR flash memory (2 virtual banks) and the QSPI |
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emulator |
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- USB 3.0 |
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- One USB 3.0 controller with integrated PHY |
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- One high-speed USB 3.0 port |
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- USB 2.0 |
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- One USB 2.0 controller with ULPI interface |
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- Two enhanced secure digital host controllers: |
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- SDHC1 controller can be connected to onboard SDHC connector |
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- SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices |
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- 2 I2C controllers |
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- One SATA onboard connectors |
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- UART |
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- 5 SAI |
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- One SAI port with audio codec SGTL5000: |
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• Provides MIC bias |
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• Provides headphone and line output |
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- One SAI port terminated at 2x6 header |
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- Three SAI Tx/Rx ports terminated at 2x3 headers |
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- ARM JTAG support |
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Booting Options |
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--------------- |
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a) QSPI Flash Emu Boot |
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b) QSPI Flash 1 |
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c) QSPI Flash 2 |
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QSPI flash map |
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-------------- |
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Images | Size |QSPI Flash Address |
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------------------------------------------ |
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RCW + PBI | 1MB | 0x4000_0000 |
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U-boot | 1MB | 0x4010_0000 |
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U-boot Env | 1MB | 0x4020_0000 |
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PPA FIT image | 2MB | 0x4050_0000 |
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Linux ITB | ~53MB | 0x40A0_0000 |
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@ -0,0 +1,234 @@ |
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/*
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <fdt_support.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/fsl_serdes.h> |
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#include <asm/arch/fdt.h> |
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#include <asm/arch/soc.h> |
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#include <ahci.h> |
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#include <hwconfig.h> |
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#include <mmc.h> |
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#include <scsi.h> |
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#include <fm_eth.h> |
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#include <fsl_csu.h> |
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#include <fsl_esdhc.h> |
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#include <fsl_mmdc.h> |
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#include <spl.h> |
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#include <netdev.h> |
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#include "../common/qixis.h" |
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#include "ls1012aqds_qixis.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) |
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{ |
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int timeout = 1000; |
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out_be32(ptr, value); |
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while (in_be32(ptr) & bits) { |
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udelay(100); |
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timeout--; |
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} |
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if (timeout <= 0) |
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puts("Error: wait for clear timeout.\n"); |
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} |
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int checkboard(void) |
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{ |
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char buf[64]; |
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u8 sw; |
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sw = QIXIS_READ(arch); |
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printf("Board Arch: V%d, ", sw >> 4); |
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printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); |
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sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); |
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if (sw & QIXIS_LBMAP_ALTBANK) |
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printf("flash: 2\n"); |
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else |
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printf("flash: 1\n"); |
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printf("FPGA: v%d (%s), build %d", |
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(int)QIXIS_READ(scver), qixis_read_tag(buf), |
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(int)qixis_read_minor()); |
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/* the timestamp string contains "\n" at the end */ |
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printf(" on %s", qixis_read_time(buf)); |
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return 0; |
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} |
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|
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void mmdc_init(void) |
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{ |
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struct mmdc_p_regs *mmdc = |
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(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; |
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out_be32(&mmdc->mdscr, CONFIGURATION_REQ); |
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|
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/* configure timing parms */ |
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out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); |
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out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); |
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out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); |
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out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); |
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|
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/* other parms */ |
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out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); |
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out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); |
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out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); |
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out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); |
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|
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/* out of reset delays */ |
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out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); |
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|
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/* physical parms */ |
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out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); |
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out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); |
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|
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/* Enable MMDC */ |
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out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); |
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|
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/* dram init sequence: update MRs */ |
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); |
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | |
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CMD_BANK_ADDR_3)); |
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); |
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | |
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CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); |
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|
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/* dram init sequence: ZQCL */ |
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | |
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CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); |
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set_wait_for_bits_clear(&mmdc->mpzqhwctrl, |
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CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, |
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FORCE_ZQ_AUTO_CALIBRATION); |
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|
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/* Calibrations now: wr lvl */ |
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | |
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CONFIGURATION_REQ | CMD_LOAD_MODE_REG | |
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CMD_BANK_ADDR_1)); |
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); |
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set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); |
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|
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mdelay(1); |
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|
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); |
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out_be32(&mmdc->mdscr, CONFIGURATION_REQ); |
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|
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mdelay(1); |
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|
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/* Calibrations now: Read DQS gating calibration */ |
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); |
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); |
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out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); |
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out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); |
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set_wait_for_bits_clear(&mmdc->mpdgctrl0, |
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AUTO_RD_DQS_GATING_CALIBRATION_EN, |
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AUTO_RD_DQS_GATING_CALIBRATION_EN); |
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|
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | |
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CMD_BANK_ADDR_3)); |
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|
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/* Calibrations now: Read calibration */ |
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out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); |
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out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); |
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out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); |
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set_wait_for_bits_clear(&mmdc->mprddlhwctl, |
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AUTO_RD_CALIBRATION_EN, |
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AUTO_RD_CALIBRATION_EN); |
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|
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out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | |
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CMD_BANK_ADDR_3)); |
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|
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/* PD, SR */ |
||||
out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); |
||||
out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); |
||||
|
||||
/* refresh scheme */ |
||||
set_wait_for_bits_clear(&mmdc->mdref, |
||||
CONFIG_SYS_MMDC_CORE_REFRESH_CTL, |
||||
START_REFRESH); |
||||
|
||||
/* disable CON_REQ */ |
||||
out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
mmdc_init(); |
||||
|
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
fsl_lsch2_early_init_f(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_MISC_INIT_R |
||||
int misc_init_r(void) |
||||
{ |
||||
u8 mux_sdhc_cd = 0x80; |
||||
|
||||
i2c_set_bus_num(0); |
||||
|
||||
i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int board_init(void) |
||||
{ |
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *) |
||||
CONFIG_SYS_CCI400_ADDR; |
||||
|
||||
/* Set CCI-400 control override register to enable barrier
|
||||
* transaction */ |
||||
out_le32(&cci->ctrl_ord, |
||||
CCI400_CTRLORD_EN_BARRIER); |
||||
|
||||
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
||||
enable_layerscape_ns_access(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ENV_IS_NOWHERE |
||||
gd->env_addr = (ulong)&default_environment[0]; |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return pci_eth_init(bis); |
||||
} |
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP |
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
arch_fixup_fdt(blob); |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,35 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __LS1043AQDS_QIXIS_H__ |
||||
#define __LS1043AQDS_QIXIS_H__ |
||||
|
||||
/* Definitions of QIXIS Registers for LS1043AQDS */ |
||||
|
||||
/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ |
||||
#define BRDCFG4_EMISEL_MASK 0xe0 |
||||
#define BRDCFG4_EMISEL_SHIFT 5 |
||||
|
||||
/* SYSCLK */ |
||||
#define QIXIS_SYSCLK_66 0x0 |
||||
#define QIXIS_SYSCLK_83 0x1 |
||||
#define QIXIS_SYSCLK_100 0x2 |
||||
#define QIXIS_SYSCLK_125 0x3 |
||||
#define QIXIS_SYSCLK_133 0x4 |
||||
|
||||
/* DDRCLK */ |
||||
#define QIXIS_DDRCLK_66 0x0 |
||||
#define QIXIS_DDRCLK_100 0x1 |
||||
#define QIXIS_DDRCLK_125 0x2 |
||||
#define QIXIS_DDRCLK_133 0x3 |
||||
|
||||
/* BRDCFG2 - SD clock*/ |
||||
#define QIXIS_SDCLK1_100 0x0 |
||||
#define QIXIS_SDCLK1_125 0x1 |
||||
#define QIXIS_SDCLK1_165 0x2 |
||||
#define QIXIS_SDCLK1_100_SP 0x3 |
||||
|
||||
#endif |
||||
@ -0,0 +1,32 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1012AQDS=y |
||||
# CONFIG_SYS_MALLOC_F is not set |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_DM_SPI_FLASH=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_OF_BOARD_SETUP=y |
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_GREPENV=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_USB=y |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_DM=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_E1000=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_FSL_DSPI=y |
||||
@ -0,0 +1,145 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __LS1012A_COMMON_H |
||||
#define __LS1012A_COMMON_H |
||||
|
||||
#define CONFIG_FSL_LAYERSCAPE |
||||
#define CONFIG_FSL_LSCH2 |
||||
#define CONFIG_LS1012A |
||||
#define CONFIG_GICV2 |
||||
|
||||
#define CONFIG_SYS_HAS_SERDES |
||||
|
||||
#include <asm/arch/config.h> |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_SUPPORT_RAW_INITRD |
||||
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40100000 |
||||
|
||||
#define CONFIG_SYS_FSL_CLK |
||||
#define CONFIG_SYS_CLK_FREQ 100000000 |
||||
#define CONFIG_DDR_CLK_FREQ 125000000 |
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 |
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) |
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) |
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 |
||||
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||
|
||||
/* Generic Timer Definitions */ |
||||
#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */ |
||||
|
||||
/* CSU */ |
||||
#define CONFIG_LAYERSCAPE_NS_ACCESS |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
||||
|
||||
/*SPI device */ |
||||
#ifdef CONFIG_QSPI_BOOT |
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH |
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 |
||||
#define CONFIG_ENV_SPI_BUS 0 |
||||
#define CONFIG_ENV_SPI_CS 0 |
||||
#define CONFIG_ENV_SPI_MAX_HZ 1000000 |
||||
#define CONFIG_ENV_SPI_MODE 0x03 |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#define CONFIG_FSL_SPI_INTERFACE |
||||
#define CONFIG_SF_DATAFLASH |
||||
|
||||
#define CONFIG_FSL_QSPI |
||||
#define QSPI0_AMBA_BASE 0x40000000 |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#define CONFIG_SPI_FLASH_BAR |
||||
|
||||
#define FSL_QSPI_FLASH_SIZE (1 << 24) |
||||
#define FSL_QSPI_FLASH_NUM 2 |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SIZE 0x40000 /* 256KB */ |
||||
#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
||||
|
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/* Command line configuration */ |
||||
#define CONFIG_CMD_ENV |
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#define CONFIG_ARCH_EARLY_INIT_R |
||||
|
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
#define CONFIG_HWCONFIG |
||||
#define HWCONFIG_BUFFER_SIZE 128 |
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
|
||||
/* Initial environment variables */ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"initrd_high=0xffffffff\0" \
|
||||
"verify=no\0" \
|
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
"loadaddr=0x80100000\0" \
|
||||
"kernel_addr=0x100000\0" \
|
||||
"ramdisk_addr=0x800000\0" \
|
||||
"ramdisk_size=0x2000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"kernel_start=0xa00000\0" \
|
||||
"kernel_load=0xa0000000\0" \
|
||||
"kernel_size=0x2800000\0" \
|
||||
"console=ttyAMA0,38400n8\0" |
||||
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ |
||||
"earlycon=uart8250,mmio,0x21c0500" |
||||
#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ |
||||
"$kernel_start $kernel_size && "\
|
||||
"bootm $kernel_load" |
||||
#define CONFIG_BOOTDELAY 10 |
||||
|
||||
/* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_MAXARGS 64 /* max command args */ |
||||
|
||||
#define CONFIG_PANIC_HANG |
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
||||
|
||||
#include <asm/fsl_secure_boot.h> |
||||
|
||||
#endif /* __LS1012A_COMMON_H */ |
||||
@ -0,0 +1,191 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __LS1012AQDS_H__ |
||||
#define __LS1012AQDS_H__ |
||||
|
||||
#include "ls1012a_common.h" |
||||
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1 |
||||
#define CONFIG_NR_DRAM_BANKS 2 |
||||
#define CONFIG_SYS_SDRAM_SIZE 0x40000000 |
||||
|
||||
#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 |
||||
#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000 |
||||
|
||||
/*
|
||||
* QIXIS Definitions |
||||
*/ |
||||
#define CONFIG_FSL_QIXIS |
||||
|
||||
#ifdef CONFIG_FSL_QIXIS |
||||
#define CONFIG_QIXIS_I2C_ACCESS |
||||
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 |
||||
#define QIXIS_LBMAP_BRDCFG_REG 0x04 |
||||
#define QIXIS_LBMAP_SWITCH 6 |
||||
#define QIXIS_LBMAP_MASK 0xf7 |
||||
#define QIXIS_LBMAP_SHIFT 0 |
||||
#define QIXIS_LBMAP_DFLTBANK 0x00 |
||||
#define QIXIS_LBMAP_ALTBANK 0x08 |
||||
#define QIXIS_RST_CTL_RESET 0x41 |
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 |
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 |
||||
#endif |
||||
|
||||
/*
|
||||
* I2C bus multiplexer |
||||
*/ |
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 |
||||
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ |
||||
#define I2C_RETIMER_ADDR 0x18 |
||||
#define I2C_MUX_CH_DEFAULT 0x8 |
||||
#define I2C_MUX_CH_CH7301 0xC |
||||
#define I2C_MUX_CH5 0xD |
||||
#define I2C_MUX_CH7 0xF |
||||
|
||||
#define I2C_MUX_CH_VOL_MONITOR 0xa |
||||
|
||||
/*
|
||||
* RTC configuration |
||||
*/ |
||||
#define RTC |
||||
#define CONFIG_RTC_PCF8563 1 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ |
||||
#define CONFIG_CMD_DATE |
||||
|
||||
/* EEPROM */ |
||||
#define CONFIG_ID_EEPROM |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_SYS_I2C_EEPROM_NXID |
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 |
||||
|
||||
|
||||
/* Voltage monitor on channel 2*/ |
||||
#define I2C_VOL_MONITOR_ADDR 0x40 |
||||
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 |
||||
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 |
||||
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 |
||||
|
||||
/* DSPI */ |
||||
#define CONFIG_FSL_DSPI1 |
||||
#define CONFIG_DEFAULT_SPI_BUS 1 |
||||
|
||||
#define CONFIG_CMD_SPI |
||||
#define MMAP_DSPI DSPI1_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_DSPI_CTAR0 1 |
||||
|
||||
#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ |
||||
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
|
||||
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
|
||||
DSPI_CTAR_DT(0)) |
||||
#define CONFIG_SPI_FLASH_SST /* cs1 */ |
||||
|
||||
#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ |
||||
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
|
||||
DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
|
||||
DSPI_CTAR_DT(0)) |
||||
#define CONFIG_SPI_FLASH_STMICRO /* cs2 */ |
||||
|
||||
#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ |
||||
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
|
||||
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
|
||||
DSPI_CTAR_DT(0)) |
||||
#define CONFIG_SPI_FLASH_EON /* cs3 */ |
||||
|
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000 |
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
||||
#define CONFIG_SF_DEFAULT_BUS 1 |
||||
#define CONFIG_SF_DEFAULT_CS 0 |
||||
|
||||
/*
|
||||
* USB |
||||
*/ |
||||
/* EHCI Support - disbaled by default */ |
||||
/*#define CONFIG_HAS_FSL_DR_USB*/ |
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_FSL |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#endif |
||||
|
||||
/*XHCI Support - enabled by default*/ |
||||
#define CONFIG_HAS_FSL_XHCI_USB |
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB |
||||
#define CONFIG_USB_XHCI |
||||
#define CONFIG_USB_XHCI_FSL |
||||
#define CONFIG_USB_XHCI_DWC3 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
||||
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
||||
#define CONFIG_USB_STORAGE |
||||
#endif |
||||
|
||||
/* MMC */ |
||||
#define CONFIG_MMC |
||||
#ifdef CONFIG_MMC |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
/* SATA */ |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_SCSI |
||||
#define CONFIG_SCSI_AHCI |
||||
#define CONFIG_SCSI_AHCI_PLAT |
||||
#define CONFIG_CMD_SCSI |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
#define CONFIG_SYS_SATA AHCI_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 |
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1 |
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
||||
CONFIG_SYS_SCSI_MAX_LUN) |
||||
#define CONFIG_PCI /* Enable PCI/PCIE */ |
||||
#define CONFIG_PCIE1 /* PCIE controller 1 */ |
||||
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
||||
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" |
||||
|
||||
#define CONFIG_SYS_PCI_64BIT |
||||
|
||||
#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 |
||||
#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ |
||||
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 |
||||
#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ |
||||
|
||||
#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 |
||||
#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 |
||||
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 |
||||
#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP |
||||
#define CONFIG_PCI_SCAN_SHOW |
||||
#define CONFIG_CMD_PCI |
||||
|
||||
#define CONFIG_CMD_MEMINFO |
||||
#define CONFIG_CMD_MEMTEST |
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x9fffffff |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#endif /* __LS1012AQDS_H__ */ |
||||
Loading…
Reference in new issue