Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>master
Andreas Bießmann
9 years ago
parent
fb1e3eb9ea
commit
9eb45aabe0
@ -1,15 +0,0 @@ |
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if TARGET_FAVR_32_EZKIT |
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config SYS_BOARD |
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default "favr-32-ezkit" |
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config SYS_VENDOR |
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default "earthlcd" |
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config SYS_SOC |
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default "at32ap700x" |
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config SYS_CONFIG_NAME |
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default "favr-32-ezkit" |
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endif |
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@ -1,6 +0,0 @@ |
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FAVR-32-EZKIT BOARD |
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#M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> |
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S: Orphan (since 2014-06) |
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F: board/earthlcd/favr-32-ezkit/ |
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F: include/configs/favr-32-ezkit.h |
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F: configs/favr-32-ezkit_defconfig |
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@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2008 Atmel Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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obj-y := favr-32-ezkit.o flash.o
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@ -1,81 +0,0 @@ |
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/*
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* Copyright (C) 2008 Atmel Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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|
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#include <asm/io.h> |
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#include <asm/sdram.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/hmatrix.h> |
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#include <asm/arch/mmu.h> |
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#include <asm/arch/portmux.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { |
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{ |
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.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, |
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.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, |
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.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) |
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| MMU_VMR_CACHE_NONE, |
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}, { |
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.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, |
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.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, |
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.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) |
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| MMU_VMR_CACHE_WRBACK, |
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}, |
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}; |
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static const struct sdram_config sdram_config = { |
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/* MT48LC4M32B2P-6 (16 MB) */ |
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.data_bits = SDRAM_DATA_32BIT, |
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.row_bits = 12, |
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.col_bits = 8, |
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.bank_bits = 2, |
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.cas = 3, |
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.twr = 2, |
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.trc = 7, |
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.trp = 2, |
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.trcd = 2, |
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.tras = 5, |
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.txsr = 5, |
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/* 15.6 us */ |
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.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, |
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}; |
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int board_early_init_f(void) |
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{ |
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/* Enable SDRAM in the EBI mux */ |
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); |
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portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); |
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sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); |
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portmux_enable_usart3(PORTMUX_DRIVE_MIN); |
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#if defined(CONFIG_MACB) |
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portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); |
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#endif |
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#if defined(CONFIG_MMC) |
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portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); |
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#endif |
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return 0; |
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} |
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int board_early_init_r(void) |
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{ |
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gd->bd->bi_phy_id[0] = 0x01; |
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return 0; |
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} |
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#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) |
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int board_eth_init(bd_t *bi) |
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{ |
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return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, |
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bi->bi_phy_id[0]); |
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} |
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#endif |
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@ -1,216 +0,0 @@ |
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/*
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* Copyright (C) 2008 Atmel Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH |
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#include <asm/arch/cacheflush.h> |
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#include <asm/io.h> |
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#include <asm/sections.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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flash_info_t flash_info[1]; |
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static void flash_identify(uint16_t *flash, flash_info_t *info) |
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{ |
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unsigned long flags; |
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flags = disable_interrupts(); |
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dcache_flush_unlocked(); |
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writew(0xaa, flash + 0x555); |
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writew(0x55, flash + 0xaaa); |
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writew(0x90, flash + 0x555); |
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info->flash_id = readl(flash); |
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writew(0xff, flash); |
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readw(flash); |
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if (flags) |
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enable_interrupts(); |
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} |
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unsigned long flash_init(void) |
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{ |
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unsigned long addr; |
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unsigned int i; |
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flash_info[0].size = CONFIG_SYS_FLASH_SIZE; |
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flash_info[0].sector_count = 135; |
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flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]); |
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for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) |
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flash_info[0].start[i] = addr; |
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for (; i < flash_info[0].sector_count; i++, addr += 0x10000) |
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flash_info[0].start[i] = addr; |
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return CONFIG_SYS_FLASH_SIZE; |
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} |
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void flash_print_info(flash_info_t *info) |
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{ |
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printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n", |
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info->flash_id >> 16, info->flash_id & 0xffff); |
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printf("Size: %ld MB in %d sectors\n", |
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info->size >> 10, info->sector_count); |
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} |
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int flash_erase(flash_info_t *info, int s_first, int s_last) |
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{ |
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unsigned long flags; |
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unsigned long start_time; |
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uint16_t *fb, *sb; |
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unsigned int i; |
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int ret; |
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uint16_t status; |
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if ((s_first < 0) || (s_first > s_last) |
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|| (s_last >= info->sector_count)) { |
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puts("Error: first and/or last sector out of range\n"); |
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return ERR_INVAL; |
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} |
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for (i = s_first; i < s_last; i++) |
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if (info->protect[i]) { |
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printf("Error: sector %d is protected\n", i); |
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return ERR_PROTECTED; |
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} |
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fb = (uint16_t *)uncached(info->start[0]); |
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dcache_flush_unlocked(); |
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for (i = s_first; (i <= s_last) && !ctrlc(); i++) { |
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printf("Erasing sector %3d...", i); |
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sb = (uint16_t *)uncached(info->start[i]); |
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flags = disable_interrupts(); |
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start_time = get_timer(0); |
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/* Unlock sector */ |
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writew(0xaa, fb + 0x555); |
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writew(0x70, sb); |
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/* Erase sector */ |
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writew(0xaa, fb + 0x555); |
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writew(0x55, fb + 0xaaa); |
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writew(0x80, fb + 0x555); |
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writew(0xaa, fb + 0x555); |
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writew(0x55, fb + 0xaaa); |
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writew(0x30, sb); |
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/* Wait for completion */ |
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ret = ERR_OK; |
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do { |
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/* TODO: Timeout */ |
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status = readw(sb); |
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} while ((status != 0xffff) && !(status & 0x28)); |
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writew(0xf0, fb); |
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/*
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* Make sure the command actually makes it to the bus |
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* before we re-enable interrupts. |
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*/ |
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readw(fb); |
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if (flags) |
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enable_interrupts(); |
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if (status != 0xffff) { |
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printf("Flash erase error at address 0x%p: 0x%02x\n", |
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sb, status); |
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ret = ERR_PROG_ERROR; |
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break; |
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} |
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} |
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if (ctrlc()) |
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printf("User interrupt!\n"); |
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return ERR_OK; |
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} |
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int write_buff(flash_info_t *info, uchar *src, |
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ulong addr, ulong count) |
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{ |
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unsigned long flags; |
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uint16_t *base, *p, *s, *end; |
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uint16_t word, status, status1; |
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int ret = ERR_OK; |
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if (addr < info->start[0] |
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|| (addr + count) > (info->start[0] + info->size) |
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|| (addr + count) < addr) { |
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puts("Error: invalid address range\n"); |
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return ERR_INVAL; |
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} |
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if (addr & 1 || count & 1 || (unsigned int)src & 1) { |
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puts("Error: misaligned source, destination or count\n"); |
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return ERR_ALIGN; |
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} |
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base = (uint16_t *)uncached(info->start[0]); |
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end = (uint16_t *)uncached(addr + count); |
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flags = disable_interrupts(); |
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dcache_flush_unlocked(); |
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sync_write_buffer(); |
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for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; |
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p < end && !ctrlc(); p++, s++) { |
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word = *s; |
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writew(0xaa, base + 0x555); |
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writew(0x55, base + 0xaaa); |
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writew(0xa0, base + 0x555); |
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writew(word, p); |
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sync_write_buffer(); |
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/* Wait for completion */ |
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status1 = readw(p); |
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do { |
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/* TODO: Timeout */ |
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status = status1; |
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status1 = readw(p); |
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} while (((status ^ status1) & 0x40) /* toggled */ |
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&& !(status1 & 0x28)); /* error bits */ |
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/*
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* We'll need to check once again for toggle bit |
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* because the toggle bit may stop toggling as I/O5 |
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* changes to "1" (ref at49bv642.pdf p9) |
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*/ |
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status1 = readw(p); |
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status = readw(p); |
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if ((status ^ status1) & 0x40) { |
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printf("Flash write error at address 0x%p: " |
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"0x%02x != 0x%02x\n", |
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p, status,word); |
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ret = ERR_PROG_ERROR; |
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writew(0xf0, base); |
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readw(base); |
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break; |
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} |
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writew(0xf0, base); |
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readw(base); |
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} |
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if (flags) |
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enable_interrupts(); |
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return ret; |
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} |
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#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */ |
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@ -1,7 +0,0 @@ |
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CONFIG_AVR32=y |
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CONFIG_CMD_NET=y |
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CONFIG_TARGET_FAVR_32_EZKIT=y |
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CONFIG_AUTOBOOT_KEYED=y |
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CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" |
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CONFIG_AUTOBOOT_DELAY_STR="d" |
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CONFIG_AUTOBOOT_STOP_STR=" " |
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@ -1,171 +0,0 @@ |
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/*
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* Copyright (C) 2008 Atmel Corporation |
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* |
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* Configuration settings for the Favr-32 EarthLCD LCD kit. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <asm/arch/hardware.h> |
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#define CONFIG_AT32AP |
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#define CONFIG_AT32AP7000 |
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#define CONFIG_FAVR32_EZKIT |
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#define CONFIG_FAVR32_EZKIT_EXT_FLASH |
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/*
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* Set up the PLL to run at 140 MHz, the CPU to run at the PLL |
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* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the |
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* PLL frequency. |
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* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz |
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*/ |
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#define CONFIG_PLL |
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#define CONFIG_SYS_POWER_MANAGER |
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#define CONFIG_SYS_OSC0_HZ 20000000 |
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#define CONFIG_SYS_PLL0_DIV 1 |
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#define CONFIG_SYS_PLL0_MUL 7 |
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#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 |
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/*
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* Set the CPU running at: |
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* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz |
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*/ |
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#define CONFIG_SYS_CLKDIV_CPU 0 |
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/*
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* Set the HSB running at: |
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* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz |
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*/ |
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#define CONFIG_SYS_CLKDIV_HSB 1 |
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/*
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* Set the PBA running at: |
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* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz |
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*/ |
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#define CONFIG_SYS_CLKDIV_PBA 2 |
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/*
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* Set the PBB running at: |
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* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz |
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*/ |
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#define CONFIG_SYS_CLKDIV_PBB 1 |
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/* Reserve VM regions for SDRAM and NOR flash */ |
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#define CONFIG_SYS_NR_VM_REGIONS 2 |
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/*
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* The PLLOPT register controls the PLL like this: |
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* icp = PLLOPT<2> |
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* ivco = PLLOPT<1:0> |
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* |
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). |
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*/ |
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#define CONFIG_SYS_PLL0_OPT 0x04 |
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#define CONFIG_USART_BASE ATMEL_BASE_USART3 |
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#define CONFIG_USART_ID 3 |
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/* User serviceable stuff */ |
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#define CONFIG_DOS_PARTITION |
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#define CONFIG_CMDLINE_TAG |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_INITRD_TAG |
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#define CONFIG_STACKSIZE (2048) |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_BOOTARGS \ |
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"root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k" |
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#define CONFIG_BOOTCOMMAND \ |
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"fsload; bootm $(fileaddr)" |
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#define CONFIG_BOOTDELAY 1 |
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/*
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* After booting the board for the first time, new ethernet addresses |
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* should be generated and assigned to the environment variables |
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* "ethaddr" and "eth1addr". This is normally done during production. |
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*/ |
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#define CONFIG_OVERWRITE_ETHADDR_ONCE |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_SUBNETMASK |
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#define CONFIG_BOOTP_GATEWAY |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_ASKENV |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_JFFS2 |
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#define CONFIG_CMD_MMC |
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#undef CONFIG_CMD_FPGA |
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#undef CONFIG_CMD_SETGETDCR |
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#undef CONFIG_CMD_SOURCE |
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#undef CONFIG_CMD_XIMG |
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#define CONFIG_ATMEL_USART |
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#define CONFIG_MACB |
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#define CONFIG_PORTMUX_PIO |
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#define CONFIG_SYS_NR_PIOS 5 |
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#define CONFIG_SYS_HSDRAMC |
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#define CONFIG_MMC |
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#define CONFIG_GENERIC_ATMEL_MCI |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_SYS_DCACHE_LINESZ 32 |
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#define CONFIG_SYS_ICACHE_LINESZ 32 |
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#define CONFIG_NR_DRAM_BANKS 1 |
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/* External flash on Favr-32 */ |
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#if 0 |
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#define CONFIG_SYS_FLASH_CFI 1 |
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#define CONFIG_FLASH_CFI_DRIVER 1 |
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#endif |
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#define CONFIG_SYS_FLASH_BASE 0x00000000 |
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#define CONFIG_SYS_FLASH_SIZE 0x800000 |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_SYS_MAX_FLASH_SECT 135 |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_TEXT_BASE 0x00000000 |
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#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE |
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#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE |
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#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE |
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#define CONFIG_ENV_IS_IN_FLASH |
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#define CONFIG_ENV_SIZE 65536 |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) |
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#define CONFIG_SYS_MALLOC_LEN (256*1024) |
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/* Allow 4MB for the kernel run-time image */ |
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#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) |
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#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) |
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/* Other configuration settings that shouldn't have to change all that often */ |
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#define CONFIG_SYS_PROMPT "U-Boot> " |
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#define CONFIG_SYS_CBSIZE 256 |
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#define CONFIG_SYS_MAXARGS 16 |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
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#define CONFIG_SYS_LONGHELP |
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#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE |
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) |
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } |
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#endif /* __CONFIG_H */ |
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