Tom Rini
11 years ago
commit
9f3fe6da27
@ -1,34 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(CPU).o
|
||||
|
||||
START = start.o
|
||||
|
||||
COBJS += cpu.o
|
||||
COBJS += omap925.o
|
||||
COBJS += timer.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
|
||||
all: $(obj).depend $(START) $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -1,15 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -march=armv4
|
||||
# =========================================================================
|
||||
#
|
||||
# Supply options according to compiler version
|
||||
#
|
||||
# =========================================================================
|
||||
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
|
||||
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
|
||||
@ -1,50 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* CPU specific code |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <arm925t.h> |
||||
#include <asm/system.h> |
||||
|
||||
static void cache_flush(void); |
||||
|
||||
int cleanup_before_linux (void) |
||||
{ |
||||
/*
|
||||
* this function is called just before we call linux |
||||
* it prepares the processor for linux |
||||
* |
||||
* we turn off caches etc ... |
||||
*/ |
||||
|
||||
disable_interrupts (); |
||||
|
||||
|
||||
/* turn off I/D-cache */ |
||||
icache_disable(); |
||||
dcache_disable(); |
||||
/* flush I/D-cache */ |
||||
cache_flush(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* flush I/D-cache */ |
||||
static void cache_flush (void) |
||||
{ |
||||
unsigned long i = 0; |
||||
|
||||
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); |
||||
} |
||||
@ -1,23 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Texas Instruments <www.ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <arm925t.h> |
||||
|
||||
#define MIF_CONFIG_REG 0xFFFECC0C |
||||
#define FLASH_GLOBAL_CTRL_NWP 1 |
||||
|
||||
void archflashwp (void *archdata, int wp) |
||||
{ |
||||
ulong *fgc = (ulong *) MIF_CONFIG_REG; |
||||
|
||||
if (wp == 1) |
||||
*fgc &= ~FLASH_GLOBAL_CTRL_NWP; |
||||
else |
||||
*fgc |= FLASH_GLOBAL_CTRL_NWP; |
||||
} |
||||
@ -1,382 +0,0 @@ |
||||
/* |
||||
* armboot - Startup Code for ARM925 CPU-core |
||||
* |
||||
* Copyright (c) 2003 Texas Instruments |
||||
* |
||||
* ----- Adapted for OMAP1510 from ARM920 code ------ |
||||
* |
||||
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
||||
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
||||
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
|
||||
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm-offsets.h> |
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Jump vector table as in table 3.1 in [1] |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
|
||||
.globl _start
|
||||
_start: b reset |
||||
ldr pc, _undefined_instruction |
||||
ldr pc, _software_interrupt |
||||
ldr pc, _prefetch_abort |
||||
ldr pc, _data_abort |
||||
ldr pc, _not_used |
||||
ldr pc, _irq |
||||
ldr pc, _fiq |
||||
|
||||
_undefined_instruction: .word undefined_instruction |
||||
_software_interrupt: .word software_interrupt |
||||
_prefetch_abort: .word prefetch_abort |
||||
_data_abort: .word data_abort |
||||
_not_used: .word not_used |
||||
_irq: .word irq |
||||
_fiq: .word fiq |
||||
|
||||
.balignl 16,0xdeadbeef |
||||
|
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Startup Code (reset vector) |
||||
* |
||||
* do important init only if we don't start from memory! |
||||
* setup Memory and board specific bits prior to relocation. |
||||
* relocate armboot to ram |
||||
* setup stack |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
.globl _TEXT_BASE
|
||||
_TEXT_BASE: |
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) |
||||
.word CONFIG_SPL_TEXT_BASE
|
||||
#else |
||||
.word CONFIG_SYS_TEXT_BASE
|
||||
#endif |
||||
|
||||
/* |
||||
* These are defined in the board-specific linker script. |
||||
* Subtracting _start from them lets the linker put their |
||||
* relative position in the executable instead of leaving |
||||
* them null. |
||||
*/ |
||||
.globl _bss_start_ofs
|
||||
_bss_start_ofs: |
||||
.word __bss_start - _start |
||||
|
||||
.globl _bss_end_ofs
|
||||
_bss_end_ofs: |
||||
.word __bss_end - _start |
||||
|
||||
.globl _end_ofs
|
||||
_end_ofs: |
||||
.word _end - _start |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl IRQ_STACK_START
|
||||
IRQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl FIQ_STACK_START
|
||||
FIQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
#endif |
||||
|
||||
/* IRQ stack memory (calculated at run-time) + 8 bytes */ |
||||
.globl IRQ_STACK_START_IN
|
||||
IRQ_STACK_START_IN: |
||||
.word 0x0badc0de
|
||||
|
||||
/* |
||||
* the actual reset code |
||||
*/ |
||||
|
||||
reset: |
||||
/* |
||||
* set the cpu to SVC32 mode |
||||
*/ |
||||
mrs r0,cpsr |
||||
bic r0,r0,#0x1f |
||||
orr r0,r0,#0xd3 |
||||
msr cpsr,r0 |
||||
|
||||
/* |
||||
* Set up 925T mode |
||||
*/ |
||||
mov r1, #0x81 /* Set ARM925T configuration. */ |
||||
mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */ |
||||
|
||||
/* |
||||
* turn off the watchdog, unlock/diable sequence |
||||
*/ |
||||
mov r1, #0xF5 |
||||
ldr r0, =WDTIM_MODE |
||||
strh r1, [r0] |
||||
mov r1, #0xA0 |
||||
strh r1, [r0] |
||||
|
||||
/* |
||||
* mask all IRQs by setting all bits in the INTMR - default |
||||
*/ |
||||
mov r1, #0xffffffff |
||||
ldr r0, =REG_IHL1_MIR |
||||
str r1, [r0] |
||||
ldr r0, =REG_IHL2_MIR |
||||
str r1, [r0] |
||||
|
||||
/* |
||||
* wait for dpll to lock |
||||
*/ |
||||
ldr r0, =CK_DPLL1 |
||||
mov r1, #0x10 |
||||
strh r1, [r0] |
||||
poll1: |
||||
ldrh r1, [r0] |
||||
ands r1, r1, #0x01 |
||||
beq poll1 |
||||
|
||||
/* |
||||
* we do sys-critical inits only at reboot, |
||||
* not when booting from ram! |
||||
*/ |
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
||||
bl cpu_init_crit |
||||
#endif |
||||
|
||||
bl _main |
||||
|
||||
/*------------------------------------------------------------------------------*/ |
||||
|
||||
.globl c_runtime_cpu_setup
|
||||
c_runtime_cpu_setup: |
||||
|
||||
mov pc, lr |
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* CPU_init_critical registers |
||||
* |
||||
* setup important registers |
||||
* setup memory timing |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
|
||||
cpu_init_crit: |
||||
/* |
||||
* flush v4 I/D caches |
||||
*/ |
||||
mov r0, #0 |
||||
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
||||
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
||||
|
||||
/* |
||||
* disable MMU stuff and caches |
||||
*/ |
||||
mrc p15, 0, r0, c1, c0, 0 |
||||
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
|
||||
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
|
||||
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
|
||||
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
||||
mcr p15, 0, r0, c1, c0, 0 |
||||
|
||||
/* |
||||
* Go setup Memory and board specific bits prior to relocation. |
||||
*/ |
||||
mov ip, lr /* perserve link reg across call */ |
||||
bl lowlevel_init /* go setup pll,mux,memory */ |
||||
mov lr, ip /* restore link */ |
||||
mov pc, lr /* back to my caller */ |
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Interrupt handling |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
@
|
||||
@ IRQ stack frame.
|
||||
@
|
||||
#define S_FRAME_SIZE 72 |
||||
|
||||
#define S_OLD_R0 68 |
||||
#define S_PSR 64 |
||||
#define S_PC 60 |
||||
#define S_LR 56 |
||||
#define S_SP 52 |
||||
|
||||
#define S_IP 48 |
||||
#define S_FP 44 |
||||
#define S_R10 40 |
||||
#define S_R9 36 |
||||
#define S_R8 32 |
||||
#define S_R7 28 |
||||
#define S_R6 24 |
||||
#define S_R5 20 |
||||
#define S_R4 16 |
||||
#define S_R3 12 |
||||
#define S_R2 8 |
||||
#define S_R1 4 |
||||
#define S_R0 0 |
||||
|
||||
#define MODE_SVC 0x13 |
||||
#define I_BIT 0x80 |
||||
|
||||
/* |
||||
* use bad_save_user_regs for abort/prefetch/undef/swi ... |
||||
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling |
||||
*/ |
||||
|
||||
.macro bad_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack |
||||
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
||||
|
||||
ldr r2, IRQ_STACK_START_IN |
||||
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
|
||||
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack |
||||
|
||||
add r5, sp, #S_SP |
||||
mov r1, lr |
||||
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
|
||||
mov r0, sp @ save current stack into r0 (param register)
|
||||
.endm |
||||
|
||||
.macro irq_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE |
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. |
||||
stmdb r8, {sp, lr}^ @ Calling SP, LR
|
||||
str lr, [r8, #0] @ Save calling PC
|
||||
mrs r6, spsr |
||||
str r6, [r8, #4] @ Save CPSR
|
||||
str r0, [r8, #8] @ Save OLD_R0
|
||||
mov r0, sp |
||||
.endm |
||||
|
||||
.macro irq_restore_user_regs
|
||||
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
||||
mov r0, r0 |
||||
ldr lr, [sp, #S_PC] @ Get PC |
||||
add sp, sp, #S_FRAME_SIZE |
||||
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
||||
.endm |
||||
|
||||
.macro get_bad_stack
|
||||
ldr r13, IRQ_STACK_START_IN |
||||
|
||||
str lr, [r13] @ save caller lr in position 0 of saved stack
|
||||
mrs lr, spsr @ get the spsr
|
||||
str lr, [r13, #4] @ save spsr in position 1 of saved stack
|
||||
|
||||
mov r13, #MODE_SVC @ prepare SVC-Mode |
||||
@ msr spsr_c, r13
|
||||
msr spsr, r13 @ switch modes, make sure moves will execute
|
||||
mov lr, pc @ capture return pc
|
||||
movs pc, lr @ jump to next instruction & switch modes.
|
||||
.endm |
||||
|
||||
.macro get_irq_stack @ setup IRQ stack
|
||||
ldr sp, IRQ_STACK_START |
||||
.endm |
||||
|
||||
.macro get_fiq_stack @ setup FIQ stack
|
||||
ldr sp, FIQ_STACK_START |
||||
.endm |
||||
|
||||
/* |
||||
* exception handlers |
||||
*/ |
||||
.align 5
|
||||
undefined_instruction: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_undefined_instruction |
||||
|
||||
.align 5
|
||||
software_interrupt: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_software_interrupt |
||||
|
||||
.align 5
|
||||
prefetch_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_prefetch_abort |
||||
|
||||
.align 5
|
||||
data_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_data_abort |
||||
|
||||
.align 5
|
||||
not_used: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_not_used |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_irq_stack |
||||
irq_save_user_regs |
||||
bl do_irq |
||||
irq_restore_user_regs |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_fiq_stack |
||||
/* someone ought to write a more effiction fiq_save_user_regs */ |
||||
irq_save_user_regs |
||||
bl do_fiq |
||||
irq_restore_user_regs |
||||
|
||||
#else |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_irq |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_fiq |
||||
|
||||
#endif |
||||
|
||||
.align 5
|
||||
.globl reset_cpu
|
||||
reset_cpu: |
||||
ldr r1, rstctl1 /* get clkm1 reset ctl */ |
||||
mov r3, #0x3 /* dsp_en + arm_rst = global reset */ |
||||
strh r3, [r1] /* force reset */ |
||||
mov r0, r0 |
||||
_loop_forever: |
||||
b _loop_forever |
||||
rstctl1: |
||||
.word 0xfffece10
|
||||
@ -1,104 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* 2N Telekomunikace, <www.2n.cz> |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <arm925t.h> |
||||
#include <configs/omap1510.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define TIMER_LOAD_VAL 0xffffffff |
||||
#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) |
||||
|
||||
static uint32_t timestamp; |
||||
static uint32_t lastdec; |
||||
|
||||
/* nothing really to do with interrupts, just starts up a counter. */ |
||||
int timer_init (void) |
||||
{ |
||||
/* Start the decrementer ticking down from 0xffffffff */ |
||||
__raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM); |
||||
__raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | |
||||
(CONFIG_SYS_PTV << MPUTIM_PTV_BIT), |
||||
CONFIG_SYS_TIMERBASE + CNTL_TIMER); |
||||
|
||||
/* init the timestamp and lastdec value */ |
||||
lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / |
||||
(TIMER_CLOCK / CONFIG_SYS_HZ); |
||||
timestamp = 0; /* start "advancing" time stamp from 0 */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* timer without interrupts |
||||
*/ |
||||
ulong get_timer (ulong base) |
||||
{ |
||||
return get_timer_masked () - base; |
||||
} |
||||
|
||||
/* delay x useconds AND preserve advance timestamp value */ |
||||
void __udelay (unsigned long usec) |
||||
{ |
||||
int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000; |
||||
uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); |
||||
|
||||
while (tmo > 0) { |
||||
now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); |
||||
if (last < now) /* count down timer underflow */ |
||||
tmo -= TIMER_LOAD_VAL - now + last; |
||||
else |
||||
tmo -= last - now; |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
ulong get_timer_masked (void) |
||||
{ |
||||
uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / |
||||
(TIMER_CLOCK / CONFIG_SYS_HZ); |
||||
if (lastdec < now) /* count down timer underflow */ |
||||
timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) - |
||||
now + lastdec; |
||||
else |
||||
timestamp += lastdec - now; |
||||
lastdec = now; |
||||
|
||||
return timestamp; |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long). |
||||
* On ARM it just returns the timer value. |
||||
*/ |
||||
unsigned long long get_ticks(void) |
||||
{ |
||||
return get_timer(0); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency). |
||||
* On ARM it returns the number of timer ticks per second. |
||||
*/ |
||||
ulong get_tbclk (void) |
||||
{ |
||||
return CONFIG_SYS_HZ; |
||||
} |
||||
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/system_manager.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Configure all the pin muxes |
||||
*/ |
||||
void sysmgr_pinmux_init(void) |
||||
{ |
||||
unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET; |
||||
|
||||
const unsigned long *pval = sys_mgr_init_table; |
||||
unsigned long i; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); |
||||
i++, offset += sizeof(unsigned long)) { |
||||
writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset)); |
||||
} |
||||
} |
||||
@ -0,0 +1,22 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _SYSTEM_MANAGER_H_ |
||||
#define _SYSTEM_MANAGER_H_ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
void sysmgr_pinmux_init(void); |
||||
|
||||
/* declaration for handoff table type */ |
||||
extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; |
||||
|
||||
#endif |
||||
|
||||
|
||||
#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400) |
||||
|
||||
#endif /* _SYSTEM_MANAGER_H_ */ |
||||
@ -0,0 +1,214 @@ |
||||
/* This file is generated by Preloader Generator */ |
||||
|
||||
#include "pinmux_config.h" |
||||
|
||||
/* pin mux configuration data */ |
||||
unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { |
||||
0, /* EMACIO0 - Unused */ |
||||
2, /* EMACIO1 - USB */ |
||||
2, /* EMACIO2 - USB */ |
||||
2, /* EMACIO3 - USB */ |
||||
2, /* EMACIO4 - USB */ |
||||
2, /* EMACIO5 - USB */ |
||||
2, /* EMACIO6 - USB */ |
||||
2, /* EMACIO7 - USB */ |
||||
2, /* EMACIO8 - USB */ |
||||
0, /* EMACIO9 - Unused */ |
||||
2, /* EMACIO10 - USB */ |
||||
2, /* EMACIO11 - USB */ |
||||
2, /* EMACIO12 - USB */ |
||||
2, /* EMACIO13 - USB */ |
||||
0, /* EMACIO14 - N/A */ |
||||
0, /* EMACIO15 - N/A */ |
||||
0, /* EMACIO16 - N/A */ |
||||
0, /* EMACIO17 - N/A */ |
||||
0, /* EMACIO18 - N/A */ |
||||
0, /* EMACIO19 - N/A */ |
||||
3, /* FLASHIO0 - SDMMC */ |
||||
3, /* FLASHIO1 - SDMMC */ |
||||
3, /* FLASHIO2 - SDMMC */ |
||||
3, /* FLASHIO3 - SDMMC */ |
||||
0, /* FLASHIO4 - SDMMC */ |
||||
0, /* FLASHIO5 - SDMMC */ |
||||
0, /* FLASHIO6 - SDMMC */ |
||||
0, /* FLASHIO7 - SDMMC */ |
||||
0, /* FLASHIO8 - SDMMC */ |
||||
3, /* FLASHIO9 - SDMMC */ |
||||
3, /* FLASHIO10 - SDMMC */ |
||||
3, /* FLASHIO11 - SDMMC */ |
||||
3, /* GENERALIO0 - TRACE */ |
||||
3, /* GENERALIO1 - TRACE */ |
||||
3, /* GENERALIO2 - TRACE */ |
||||
3, /* GENERALIO3 - TRACE */ |
||||
3, /* GENERALIO4 - TRACE */ |
||||
3, /* GENERALIO5 - TRACE */ |
||||
3, /* GENERALIO6 - TRACE */ |
||||
3, /* GENERALIO7 - TRACE */ |
||||
3, /* GENERALIO8 - TRACE */ |
||||
3, /* GENERALIO9 - SPIM0 */ |
||||
3, /* GENERALIO10 - SPIM0 */ |
||||
3, /* GENERALIO11 - SPIM0 */ |
||||
3, /* GENERALIO12 - SPIM0 */ |
||||
2, /* GENERALIO13 - CAN0 */ |
||||
2, /* GENERALIO14 - CAN0 */ |
||||
3, /* GENERALIO15 - I2C0 */ |
||||
3, /* GENERALIO16 - I2C0 */ |
||||
2, /* GENERALIO17 - UART0 */ |
||||
2, /* GENERALIO18 - UART0 */ |
||||
0, /* GENERALIO19 - N/A */ |
||||
0, /* GENERALIO20 - N/A */ |
||||
0, /* GENERALIO21 - N/A */ |
||||
0, /* GENERALIO22 - N/A */ |
||||
0, /* GENERALIO23 - N/A */ |
||||
0, /* GENERALIO24 - N/A */ |
||||
0, /* GENERALIO25 - N/A */ |
||||
0, /* GENERALIO26 - N/A */ |
||||
0, /* GENERALIO27 - N/A */ |
||||
0, /* GENERALIO28 - N/A */ |
||||
0, /* GENERALIO29 - N/A */ |
||||
0, /* GENERALIO30 - N/A */ |
||||
0, /* GENERALIO31 - N/A */ |
||||
2, /* MIXED1IO0 - EMAC */ |
||||
2, /* MIXED1IO1 - EMAC */ |
||||
2, /* MIXED1IO2 - EMAC */ |
||||
2, /* MIXED1IO3 - EMAC */ |
||||
2, /* MIXED1IO4 - EMAC */ |
||||
2, /* MIXED1IO5 - EMAC */ |
||||
2, /* MIXED1IO6 - EMAC */ |
||||
2, /* MIXED1IO7 - EMAC */ |
||||
2, /* MIXED1IO8 - EMAC */ |
||||
2, /* MIXED1IO9 - EMAC */ |
||||
2, /* MIXED1IO10 - EMAC */ |
||||
2, /* MIXED1IO11 - EMAC */ |
||||
2, /* MIXED1IO12 - EMAC */ |
||||
2, /* MIXED1IO13 - EMAC */ |
||||
0, /* MIXED1IO14 - Unused */ |
||||
3, /* MIXED1IO15 - QSPI */ |
||||
3, /* MIXED1IO16 - QSPI */ |
||||
3, /* MIXED1IO17 - QSPI */ |
||||
3, /* MIXED1IO18 - QSPI */ |
||||
3, /* MIXED1IO19 - QSPI */ |
||||
3, /* MIXED1IO20 - QSPI */ |
||||
0, /* MIXED1IO21 - GPIO */ |
||||
0, /* MIXED2IO0 - N/A */ |
||||
0, /* MIXED2IO1 - N/A */ |
||||
0, /* MIXED2IO2 - N/A */ |
||||
0, /* MIXED2IO3 - N/A */ |
||||
0, /* MIXED2IO4 - N/A */ |
||||
0, /* MIXED2IO5 - N/A */ |
||||
0, /* MIXED2IO6 - N/A */ |
||||
0, /* MIXED2IO7 - N/A */ |
||||
0, /* GPLINMUX48 */ |
||||
0, /* GPLINMUX49 */ |
||||
0, /* GPLINMUX50 */ |
||||
0, /* GPLINMUX51 */ |
||||
0, /* GPLINMUX52 */ |
||||
0, /* GPLINMUX53 */ |
||||
0, /* GPLINMUX54 */ |
||||
0, /* GPLINMUX55 */ |
||||
0, /* GPLINMUX56 */ |
||||
0, /* GPLINMUX57 */ |
||||
0, /* GPLINMUX58 */ |
||||
0, /* GPLINMUX59 */ |
||||
0, /* GPLINMUX60 */ |
||||
0, /* GPLINMUX61 */ |
||||
0, /* GPLINMUX62 */ |
||||
0, /* GPLINMUX63 */ |
||||
0, /* GPLINMUX64 */ |
||||
0, /* GPLINMUX65 */ |
||||
0, /* GPLINMUX66 */ |
||||
0, /* GPLINMUX67 */ |
||||
0, /* GPLINMUX68 */ |
||||
0, /* GPLINMUX69 */ |
||||
0, /* GPLINMUX70 */ |
||||
1, /* GPLMUX0 */ |
||||
1, /* GPLMUX1 */ |
||||
1, /* GPLMUX2 */ |
||||
1, /* GPLMUX3 */ |
||||
1, /* GPLMUX4 */ |
||||
1, /* GPLMUX5 */ |
||||
1, /* GPLMUX6 */ |
||||
1, /* GPLMUX7 */ |
||||
1, /* GPLMUX8 */ |
||||
1, /* GPLMUX9 */ |
||||
1, /* GPLMUX10 */ |
||||
1, /* GPLMUX11 */ |
||||
1, /* GPLMUX12 */ |
||||
1, /* GPLMUX13 */ |
||||
1, /* GPLMUX14 */ |
||||
1, /* GPLMUX15 */ |
||||
1, /* GPLMUX16 */ |
||||
1, /* GPLMUX17 */ |
||||
1, /* GPLMUX18 */ |
||||
1, /* GPLMUX19 */ |
||||
1, /* GPLMUX20 */ |
||||
1, /* GPLMUX21 */ |
||||
1, /* GPLMUX22 */ |
||||
1, /* GPLMUX23 */ |
||||
1, /* GPLMUX24 */ |
||||
1, /* GPLMUX25 */ |
||||
1, /* GPLMUX26 */ |
||||
1, /* GPLMUX27 */ |
||||
1, /* GPLMUX28 */ |
||||
1, /* GPLMUX29 */ |
||||
1, /* GPLMUX30 */ |
||||
1, /* GPLMUX31 */ |
||||
1, /* GPLMUX32 */ |
||||
1, /* GPLMUX33 */ |
||||
1, /* GPLMUX34 */ |
||||
1, /* GPLMUX35 */ |
||||
1, /* GPLMUX36 */ |
||||
1, /* GPLMUX37 */ |
||||
1, /* GPLMUX38 */ |
||||
1, /* GPLMUX39 */ |
||||
1, /* GPLMUX40 */ |
||||
1, /* GPLMUX41 */ |
||||
1, /* GPLMUX42 */ |
||||
1, /* GPLMUX43 */ |
||||
1, /* GPLMUX44 */ |
||||
1, /* GPLMUX45 */ |
||||
1, /* GPLMUX46 */ |
||||
1, /* GPLMUX47 */ |
||||
1, /* GPLMUX48 */ |
||||
1, /* GPLMUX49 */ |
||||
1, /* GPLMUX50 */ |
||||
1, /* GPLMUX51 */ |
||||
1, /* GPLMUX52 */ |
||||
1, /* GPLMUX53 */ |
||||
1, /* GPLMUX54 */ |
||||
1, /* GPLMUX55 */ |
||||
1, /* GPLMUX56 */ |
||||
1, /* GPLMUX57 */ |
||||
1, /* GPLMUX58 */ |
||||
1, /* GPLMUX59 */ |
||||
1, /* GPLMUX60 */ |
||||
1, /* GPLMUX61 */ |
||||
1, /* GPLMUX62 */ |
||||
1, /* GPLMUX63 */ |
||||
1, /* GPLMUX64 */ |
||||
1, /* GPLMUX65 */ |
||||
1, /* GPLMUX66 */ |
||||
1, /* GPLMUX67 */ |
||||
1, /* GPLMUX68 */ |
||||
1, /* GPLMUX69 */ |
||||
1, /* GPLMUX70 */ |
||||
0, /* NANDUSEFPGA */ |
||||
0, /* UART0USEFPGA */ |
||||
0, /* RGMII1USEFPGA */ |
||||
0, /* SPIS0USEFPGA */ |
||||
0, /* CAN0USEFPGA */ |
||||
0, /* I2C0USEFPGA */ |
||||
0, /* SDMMCUSEFPGA */ |
||||
0, /* QSPIUSEFPGA */ |
||||
0, /* SPIS1USEFPGA */ |
||||
0, /* RGMII0USEFPGA */ |
||||
0, /* UART1USEFPGA */ |
||||
0, /* CAN1USEFPGA */ |
||||
0, /* USB1USEFPGA */ |
||||
0, /* I2C3USEFPGA */ |
||||
0, /* I2C2USEFPGA */ |
||||
0, /* I2C1USEFPGA */ |
||||
0, /* SPIM1USEFPGA */ |
||||
0, /* USB0USEFPGA */ |
||||
0 /* SPIM0USEFPGA */ |
||||
}; |
||||
@ -0,0 +1,54 @@ |
||||
/* This file is generated by Preloader Generator */ |
||||
|
||||
#ifndef _PRELOADER_PINMUX_CONFIG_H_ |
||||
#define _PRELOADER_PINMUX_CONFIG_H_ |
||||
|
||||
/*
|
||||
* State of enabling for which IP connected out through the muxing. |
||||
* Value 1 mean the IP connection is muxed out |
||||
*/ |
||||
#define CONFIG_HPS_EMAC0 (0) |
||||
#define CONFIG_HPS_EMAC1 (1) |
||||
#define CONFIG_HPS_USB0 (0) |
||||
#define CONFIG_HPS_USB1 (1) |
||||
#define CONFIG_HPS_NAND (0) |
||||
#define CONFIG_HPS_SDMMC (1) |
||||
#define CONFIG_HPS_QSPI (1) |
||||
#define CONFIG_HPS_UART0 (1) |
||||
#define CONFIG_HPS_UART1 (0) |
||||
#define CONFIG_HPS_TRACE (1) |
||||
#define CONFIG_HPS_I2C0 (1) |
||||
#define CONFIG_HPS_I2C1 (0) |
||||
#define CONFIG_HPS_I2C2 (0) |
||||
#define CONFIG_HPS_I2C3 (0) |
||||
#define CONFIG_HPS_SPIM0 (1) |
||||
#define CONFIG_HPS_SPIM1 (0) |
||||
#define CONFIG_HPS_SPIS0 (0) |
||||
#define CONFIG_HPS_SPIS1 (0) |
||||
#define CONFIG_HPS_CAN0 (1) |
||||
#define CONFIG_HPS_CAN1 (0) |
||||
|
||||
/* IP attribute value (which affected by pin muxing configuration) */ |
||||
#define CONFIG_HPS_SDMMC_BUSWIDTH (4) |
||||
|
||||
/* 1 if the pins are connected out */ |
||||
#define CONFIG_HPS_QSPI_CS0 (1) |
||||
#define CONFIG_HPS_QSPI_CS1 (0) |
||||
#define CONFIG_HPS_QSPI_CS2 (0) |
||||
#define CONFIG_HPS_QSPI_CS3 (0) |
||||
|
||||
/* UART */ |
||||
/* 1 means the pin is mux out or available */ |
||||
#define CONFIG_HPS_UART0_TX (1) |
||||
#define CONFIG_HPS_UART0_RX (1) |
||||
#define CONFIG_HPS_UART0_CTS (0) |
||||
#define CONFIG_HPS_UART0_RTS (0) |
||||
#define CONFIG_HPS_UART1_TX (0) |
||||
#define CONFIG_HPS_UART1_RX (0) |
||||
#define CONFIG_HPS_UART1_CTS (0) |
||||
#define CONFIG_HPS_UART1_RTS (0) |
||||
|
||||
/* Pin mux data */ |
||||
#define CONFIG_HPS_PINMUX_NUM (207) |
||||
|
||||
#endif /* _PRELOADER_PINMUX_CONFIG_H_ */ |
||||
@ -1,29 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := omap1510innovator.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -1,25 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Texas Instruments, <www.ti.com>
|
||||
# Kshitij Gupta <Kshitij@ti.com>
|
||||
#
|
||||
# TI Innovator board with OMAP1510 (ARM925T) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Insturments
|
||||
#
|
||||
# Innovator has 1 bank of 256 MB SDRAM
|
||||
# Physical Address:
|
||||
# 1000'0000 to 2000'0000
|
||||
#
|
||||
#
|
||||
# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved)
|
||||
#
|
||||
# we load ourself to 1108'0000
|
||||
#
|
||||
#
|
||||
|
||||
|
||||
CONFIG_SYS_TEXT_BASE = 0x11080000
|
||||
@ -1,380 +0,0 @@ |
||||
/* |
||||
* Board specific setup info |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* -- Some bits of code used from rrload's head_OMAP1510.s -- |
||||
* Copyright (C) 2002 RidgeRun, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
#if defined(CONFIG_OMAP1510) |
||||
#include <./configs/omap1510.h> |
||||
#endif |
||||
|
||||
#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK)) |
||||
|
||||
|
||||
_TEXT_BASE: |
||||
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
|
||||
/* |
||||
* Configure 1510 pins functions to match our board. |
||||
*/ |
||||
ldr r0, REG_PULL_DWN_CTRL_0 |
||||
ldr r1, VAL_PULL_DWN_CTRL_0 |
||||
str r1, [r0] |
||||
ldr r0, REG_PULL_DWN_CTRL_1 |
||||
ldr r1, VAL_PULL_DWN_CTRL_1 |
||||
str r1, [r0] |
||||
ldr r0, REG_PULL_DWN_CTRL_2 |
||||
ldr r1, VAL_PULL_DWN_CTRL_2 |
||||
str r1, [r0] |
||||
ldr r0, REG_PULL_DWN_CTRL_3 |
||||
ldr r1, VAL_PULL_DWN_CTRL_3 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_4 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_4 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_5 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_5 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_6 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_6 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_7 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_7 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_8 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_8 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_9 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_9 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_A |
||||
ldr r1, VAL_FUNC_MUX_CTRL_A |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_B |
||||
ldr r1, VAL_FUNC_MUX_CTRL_B |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_C |
||||
ldr r1, VAL_FUNC_MUX_CTRL_C |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_D |
||||
ldr r1, VAL_FUNC_MUX_CTRL_D |
||||
str r1, [r0] |
||||
ldr r0, REG_VOLTAGE_CTRL_0 |
||||
ldr r1, VAL_VOLTAGE_CTRL_0 |
||||
str r1, [r0] |
||||
ldr r0, REG_TEST_DBG_CTRL_0 |
||||
ldr r1, VAL_TEST_DBG_CTRL_0 |
||||
str r1, [r0] |
||||
ldr r0, REG_MOD_CONF_CTRL_0 |
||||
ldr r1, VAL_MOD_CONF_CTRL_0 |
||||
str r1, [r0] |
||||
|
||||
/* Move to 1510 mode */ |
||||
ldr r0, REG_COMP_MODE_CTRL_0 |
||||
ldr r1, VAL_COMP_MODE_CTRL_0 |
||||
str r1, [r0] |
||||
|
||||
/* Set up Traffic Ctlr*/ |
||||
ldr r0, REG_TC_IMIF_PRIO |
||||
mov r1, #0x0 |
||||
str r1, [r0] |
||||
ldr r0, REG_TC_EMIFS_PRIO |
||||
str r1, [r0] |
||||
ldr r0, REG_TC_EMIFF_PRIO |
||||
str r1, [r0] |
||||
|
||||
ldr r0, REG_TC_EMIFS_CONFIG |
||||
ldr r1, [r0] |
||||
bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */ |
||||
bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */ |
||||
str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */ |
||||
|
||||
/* Setup some clock domains */ |
||||
ldr r1, =OMAP1510_CLKS |
||||
ldr r0, REG_ARM_IDLECT2 |
||||
strh r1, [r0] /* CLKM, Clock domain control. */ |
||||
|
||||
mov r1, #0x01 /* PER_EN bit */ |
||||
ldr r0, REG_ARM_RSTCT2 |
||||
strh r1, [r0] /* CLKM; Peripheral reset. */
|
||||
|
||||
/* Set CLKM to Sync-Scalable */ |
||||
/* I supposidly need to enable the dsp clock before switching */ |
||||
mov r1, #0x1000 |
||||
ldr r0, REG_ARM_SYSST |
||||
strh r1, [r0] |
||||
mov r0, #0x400 |
||||
1: |
||||
subs r0, r0, #0x1 /* wait for any bubbles to finish */ |
||||
bne 1b |
||||
|
||||
ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */ |
||||
ldr r0, REG_ARM_CKCTL |
||||
strh r1, [r0] |
||||
|
||||
/* setup DPLL 1 */ |
||||
ldr r1, VAL_DPLL1_CTL |
||||
ldr r0, REG_DPLL1_CTL |
||||
strh r1, [r0] |
||||
ands r1, r1, #0x10 /* Check if PLL is enabled. */ |
||||
beq lock_end /* Do not look for lock if BYPASS selected */ |
||||
2: |
||||
ldrh r1, [r0] |
||||
ands r1, r1, #0x01 /* Check the LOCK bit. */ |
||||
beq 2b /* ...loop until bit goes hi. */ |
||||
lock_end: |
||||
|
||||
/* Set memory timings corresponding to the new clock speed */ |
||||
|
||||
/* Check execution location to determine current execution location |
||||
* and branch to appropriate initialization code. |
||||
*/ |
||||
mov r0, #0x10000000 /* Load physical SDRAM base. */ |
||||
mov r1, pc /* Get current execution location. */ |
||||
/* Zero all but top 6 bits of PC, as they alone detect whether an |
||||
* address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized |
||||
* valid range for SDRAM on the OMAP 1510/5910. |
||||
*/ |
||||
and r1, r1, #0xfc000000 |
||||
cmp r1, r0 /* Compare. */ |
||||
beq skip_sdram /* Skip over EMIF-fast initialization |
||||
* if running from SDRAM. |
||||
*/ |
||||
|
||||
/* |
||||
* Delay for SDRAM initialization. |
||||
*/ |
||||
mov r3, #0x1800 /* value should be checked */ |
||||
3: |
||||
subs r3, r3, #0x1 /* Decrement count */ |
||||
bne 3b |
||||
|
||||
/* |
||||
* Set SDRAM control values. Disable refresh before MRS command. |
||||
*/ |
||||
ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */ |
||||
bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */ |
||||
orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */ |
||||
orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */ |
||||
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
||||
str r3, [r2] /* Store the passed value with AR disabled. */ |
||||
|
||||
ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */ |
||||
ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */ |
||||
str r1, [r2] /* Store the passed value.*/ |
||||
|
||||
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
||||
str r0, [r2] /* Store the passed value. */ |
||||
|
||||
/* |
||||
* Delay for SDRAM initialization. |
||||
*/ |
||||
mov r3, #0x1800 |
||||
4: |
||||
subs r3, r3, #1 /* Decrement count. */ |
||||
bne 4b |
||||
|
||||
skip_sdram: |
||||
|
||||
/* slow interface */ |
||||
ldr r1, VAL_TC_EMIFS_CS0_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS0_CONFIG |
||||
str r1, [r0] /* Chip Select 0 */ |
||||
ldr r1, VAL_TC_EMIFS_CS1_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS1_CONFIG |
||||
str r1, [r0] /* Chip Select 1 */ |
||||
ldr r1, VAL_TC_EMIFS_CS2_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS2_CONFIG |
||||
str r1, [r0] /* Chip Select 2 */ |
||||
ldr r1, VAL_TC_EMIFS_CS3_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS3_CONFIG |
||||
str r1, [r0] /* Chip Select 3 */ |
||||
|
||||
/* Next, Enable the RS232 Line Drivers in the FPGA. */ |
||||
/* Also, power on the audio CODEC's amplifier here, */ |
||||
/* which will make a noise on the audio output. */ |
||||
/* This is done here instead of in the kernel so there */ |
||||
/* isn't a loud popping noise at the start of each */ |
||||
/* song. */ |
||||
/* Also, disable the CODEC's clocks. */ |
||||
/* omap1510-HelenP1 [specific] */ |
||||
|
||||
ldr r0, REG_FPGA_POWER |
||||
mov r1, #0 |
||||
ldr r2, REG_FPGA_DIP_SWITCH |
||||
ldrb r3, [r2] |
||||
cmp r3, #0x8 |
||||
movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */ |
||||
strb r1, [r0] |
||||
ldr r0, REG_FPGA_AUDIO |
||||
mov r1, #0x0 /* Disable sound driver (CODEC clocks) */ |
||||
strb r1, [r0] |
||||
|
||||
/* back to arch calling code */ |
||||
mov pc, lr |
||||
|
||||
/* the literal pools origin */ |
||||
.ltorg |
||||
|
||||
/* OMAP configuration registers */ |
||||
REG_FUNC_MUX_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1000
|
||||
REG_FUNC_MUX_CTRL_1: /* 32 bits */ |
||||
.word 0xfffe1004
|
||||
REG_FUNC_MUX_CTRL_2: /* 32 bits */ |
||||
.word 0xfffe1008
|
||||
REG_COMP_MODE_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe100c
|
||||
REG_FUNC_MUX_CTRL_3: /* 32 bits */ |
||||
.word 0xfffe1010
|
||||
REG_FUNC_MUX_CTRL_4: /* 32 bits */ |
||||
.word 0xfffe1014
|
||||
REG_FUNC_MUX_CTRL_5: /* 32 bits */ |
||||
.word 0xfffe1018
|
||||
REG_FUNC_MUX_CTRL_6: /* 32 bits */ |
||||
.word 0xfffe101c
|
||||
REG_FUNC_MUX_CTRL_7: /* 32 bits */ |
||||
.word 0xfffe1020
|
||||
REG_FUNC_MUX_CTRL_8: /* 32 bits */ |
||||
.word 0xfffe1024
|
||||
REG_FUNC_MUX_CTRL_9: /* 32 bits */ |
||||
.word 0xfffe1028
|
||||
REG_FUNC_MUX_CTRL_A: /* 32 bits */ |
||||
.word 0xfffe102C
|
||||
REG_FUNC_MUX_CTRL_B: /* 32 bits */ |
||||
.word 0xfffe1030
|
||||
REG_FUNC_MUX_CTRL_C: /* 32 bits */ |
||||
.word 0xfffe1034
|
||||
REG_FUNC_MUX_CTRL_D: /* 32 bits */ |
||||
.word 0xfffe1038
|
||||
REG_PULL_DWN_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1040
|
||||
REG_PULL_DWN_CTRL_1: /* 32 bits */ |
||||
.word 0xfffe1044
|
||||
REG_PULL_DWN_CTRL_2: /* 32 bits */ |
||||
.word 0xfffe1048
|
||||
REG_PULL_DWN_CTRL_3: /* 32 bits */ |
||||
.word 0xfffe104c
|
||||
REG_VOLTAGE_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1060
|
||||
REG_TEST_DBG_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1070
|
||||
REG_MOD_CONF_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1080
|
||||
REG_TC_IMIF_PRIO: /* 32 bits */ |
||||
.word 0xfffecc00
|
||||
REG_TC_EMIFS_PRIO: /* 32 bits */ |
||||
.word 0xfffecc04
|
||||
REG_TC_EMIFF_PRIO: /* 32 bits */ |
||||
.word 0xfffecc08
|
||||
REG_TC_EMIFS_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc0c
|
||||
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc10
|
||||
REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc14
|
||||
REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc18
|
||||
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc1c
|
||||
REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc20
|
||||
REG_TC_EMIFF_MRS: /* 32 bits */ |
||||
.word 0xfffecc24
|
||||
/* MPU clock/reset/power mode control registers */ |
||||
REG_ARM_CKCTL: /* 16 bits */ |
||||
.word 0xfffece00
|
||||
REG_ARM_IDLECT2: /* 16 bits */ |
||||
.word 0xfffece08
|
||||
REG_ARM_RSTCT2: /* 16 bits */ |
||||
.word 0xfffece14
|
||||
REG_ARM_SYSST: /* 16 bits */ |
||||
.word 0xfffece18
|
||||
/* DPLL control registers */ |
||||
REG_DPLL1_CTL: /* 16 bits */ |
||||
.word 0xfffecf00
|
||||
/* identification code register */ |
||||
REG_IDCODE: /* 32 bits */ |
||||
.word 0xfffed404
|
||||
|
||||
/* Innovator specific */ |
||||
REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */ |
||||
.word 0x08000003
|
||||
REG_FPGA_POWER: /* 8 bits */ |
||||
.word 0x08000005
|
||||
REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */ |
||||
.word 0x0800000c
|
||||
REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */ |
||||
.word 0x0800000e
|
||||
|
||||
VAL_COMP_MODE_CTRL_0: |
||||
.word 0x0000eaef
|
||||
VAL_FUNC_MUX_CTRL_4: |
||||
.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_5: |
||||
.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_6: |
||||
.word 0x00000001
|
||||
VAL_FUNC_MUX_CTRL_7: |
||||
.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_8: |
||||
.word 0x10001200
|
||||
VAL_FUNC_MUX_CTRL_9: |
||||
.word 0x01201012
|
||||
VAL_FUNC_MUX_CTRL_A: |
||||
.word 0x00000248
|
||||
VAL_FUNC_MUX_CTRL_B: |
||||
.word 0x00000248
|
||||
VAL_FUNC_MUX_CTRL_C: |
||||
.word 0x09000000
|
||||
VAL_FUNC_MUX_CTRL_D: |
||||
.word 0x00000000
|
||||
VAL_PULL_DWN_CTRL_0: |
||||
.word 0x11a10000
|
||||
VAL_PULL_DWN_CTRL_1: |
||||
.word 0x2e047fff
|
||||
VAL_PULL_DWN_CTRL_2: |
||||
.word 0xffd603a6
|
||||
VAL_PULL_DWN_CTRL_3: |
||||
.word 0x00003e03
|
||||
VAL_VOLTAGE_CTRL_0: |
||||
.word 0x00000007
|
||||
VAL_TEST_DBG_CTRL_0: |
||||
/* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 . |
||||
* This slows down internal SRAM accesses. |
||||
*/ |
||||
.word 0x00000007
|
||||
VAL_MOD_CONF_CTRL_0: |
||||
.word 0x0b000008
|
||||
VAL_ARM_CKCTL: |
||||
.word 0x010f
|
||||
VAL_DPLL1_CTL: |
||||
.word 0x2710
|
||||
VAL_TC_EMIFS_CS1_CONFIG_PRELIM: |
||||
.word 0x00001149
|
||||
VAL_TC_EMIFS_CS2_CONFIG_PRELIM: |
||||
.word 0x00004158
|
||||
VAL_TC_EMIFS_CS0_CONFIG: |
||||
.word 0x002130b0
|
||||
VAL_TC_EMIFS_CS1_CONFIG: |
||||
.word 0x0000f559
|
||||
VAL_TC_EMIFS_CS2_CONFIG: |
||||
.word 0x000055f0
|
||||
VAL_TC_EMIFS_CS3_CONFIG: |
||||
.word 0x00003331
|
||||
VAL_TC_EMIFF_SDRAM_CONFIG: |
||||
.word 0x010290fc
|
||||
VAL_TC_EMIFF_MRS: |
||||
.word 0x00000027
|
||||
@ -1,125 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <netdev.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static void flash__init (void); |
||||
static void ether__init (void); |
||||
|
||||
static inline void delay (unsigned long loops) |
||||
{ |
||||
__asm__ volatile ("1:\n" |
||||
"subs %0, %1, #1\n" |
||||
"bne 1b":"=r" (loops):"0" (loops)); |
||||
} |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init (void) |
||||
{ |
||||
/* arch number of OMAP 1510-Board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x10000100; |
||||
|
||||
/* kk - this speeds up your boot a quite a bit. However to make it
|
||||
* work, you need make sure your kernel startup flush bug is fixed. |
||||
* ... rkw ... |
||||
*/ |
||||
icache_enable (); |
||||
|
||||
flash__init (); |
||||
ether__init (); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ |
||||
/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ |
||||
|
||||
/* setup gpio direction to match board (no floats!) */ |
||||
/**gdir = 0xCFF9; */ |
||||
/**mdir = 0x103F; */ |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
static void flash__init (void) |
||||
{ |
||||
#define CS0_CHIP_SELECT_REG 0xfffecc10 |
||||
#define CS3_CHIP_SELECT_REG 0xfffecc1c |
||||
#define EMIFS_GlB_Config_REG 0xfffecc0c |
||||
|
||||
{ |
||||
unsigned int regval; |
||||
|
||||
regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); |
||||
regval = regval | 0x0001; /* Turn off write protection for flash devices. */ |
||||
if (regval & 0x0002) { |
||||
regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ |
||||
/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ |
||||
/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ |
||||
/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ |
||||
} |
||||
*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; |
||||
} |
||||
} |
||||
|
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
static void ether__init (void) |
||||
{ |
||||
#define ETH_CONTROL_REG 0x0800000b |
||||
/* take the Ethernet controller out of reset and wait
|
||||
* for the EEPROM load to complete. |
||||
*/ |
||||
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; |
||||
udelay (3); |
||||
} |
||||
|
||||
|
||||
int dram_init (void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_NET |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int rc = 0; |
||||
#ifdef CONFIG_LAN91C96 |
||||
rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); |
||||
#endif |
||||
return rc; |
||||
} |
||||
#endif |
||||
@ -1,11 +0,0 @@ |
||||
/************************************************
|
||||
* NAME : arm925t.h |
||||
* Version : 23 June 2003 * |
||||
************************************************/ |
||||
|
||||
#ifndef __ARM925T_H__ |
||||
#define __ARM925T_H__ |
||||
|
||||
void archflashwp(void *archdata, int wp); |
||||
|
||||
#endif /*__ARM925T_H__*/ |
||||
@ -1,166 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Texas Instruments. |
||||
* Kshitij Gupta <kshitij@ti.com> |
||||
* Configuation settings for the TI OMAP Innovator board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ |
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||
#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ |
||||
#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */ |
||||
|
||||
/* input clock of PLL */ |
||||
#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */ |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
/*
|
||||
#define CONFIG_DRIVER_SMC9196 |
||||
#define CONFIG_SMC9196_BASE 0x08000300 |
||||
#define CONFIG_SMC9196_EXT_PHY |
||||
*/ |
||||
#define CONFIG_LAN91C96 |
||||
#define CONFIG_LAN91C96_BASE 0x08000300 |
||||
#define CONFIG_LAN91C96_EXT_PHY |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ |
||||
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */ |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
|
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
|
||||
|
||||
#include <configs/omap1510.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp" |
||||
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" |
||||
#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
||||
/* what's this ? it's not used anywhere */ |
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
||||
|
||||
/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
|
||||
* This time is further subdivided by a local divisor. |
||||
*/ |
||||
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */ |
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
#define PHYS_SRAM 0x20000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ |
||||
#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ |
||||
#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH driver setup |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ |
||||
|
||||
/* timeout values are in ticks */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue