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@ -51,7 +51,7 @@ |
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interrupt-parent = <&intc>; |
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ranges; |
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i2c0: zynq-i2c@e0004000 { |
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i2c0: i2c@e0004000 { |
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compatible = "cdns,i2c-r1p10"; |
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status = "disabled"; |
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clocks = <&clkc 38>; |
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@ -62,7 +62,7 @@ |
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#size-cells = <0>; |
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}; |
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i2c1: zynq-i2c@e0005000 { |
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i2c1: i2c@e0005000 { |
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compatible = "cdns,i2c-r1p10"; |
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status = "disabled"; |
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clocks = <&clkc 39>; |
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@ -82,7 +82,7 @@ |
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<0xF8F00100 0x100>; |
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}; |
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L2: cache-controller { |
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L2: cache-controller@f8f02000 { |
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compatible = "arm,pl310-cache"; |
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reg = <0xF8F02000 0x1000>; |
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arm,data-latency = <3 2 2>; |
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@ -91,7 +91,7 @@ |
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cache-level = <2>; |
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}; |
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uart0: uart@e0000000 { |
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uart0: serial@e0000000 { |
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compatible = "xlnx,xuartps"; |
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status = "disabled"; |
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clocks = <&clkc 23>, <&clkc 40>; |
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@ -100,7 +100,7 @@ |
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interrupts = <0 27 4>; |
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}; |
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uart1: uart@e0001000 { |
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uart1: serial@e0001000 { |
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compatible = "xlnx,xuartps"; |
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status = "disabled"; |
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clocks = <&clkc 24>, <&clkc 41>; |
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@ -153,7 +153,7 @@ |
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clock-names = "pclk", "hclk", "tx_clk"; |
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}; |
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sdhci0: ps7-sdhci@e0100000 { |
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sdhci0: sdhci@e0100000 { |
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compatible = "arasan,sdhci-8.9a"; |
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status = "disabled"; |
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clock-names = "clk_xin", "clk_ahb"; |
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@ -163,7 +163,7 @@ |
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reg = <0xe0100000 0x1000>; |
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} ; |
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sdhci1: ps7-sdhci@e0101000 { |
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sdhci1: sdhci@e0101000 { |
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compatible = "arasan,sdhci-8.9a"; |
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status = "disabled"; |
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clock-names = "clk_xin", "clk_ahb"; |
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@ -207,7 +207,7 @@ |
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clocks = <&clkc 4>; |
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}; |
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ttc0: ttc0@f8001000 { |
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ttc0: timer@f8001000 { |
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interrupt-parent = <&intc>; |
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interrupts = < 0 10 4 0 11 4 0 12 4 >; |
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compatible = "cdns,ttc"; |
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@ -215,14 +215,14 @@ |
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reg = <0xF8001000 0x1000>; |
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}; |
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ttc1: ttc1@f8002000 { |
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ttc1: timer@f8002000 { |
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interrupt-parent = <&intc>; |
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interrupts = < 0 37 4 0 38 4 0 39 4 >; |
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compatible = "cdns,ttc"; |
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clocks = <&clkc 6>; |
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reg = <0xF8002000 0x1000>; |
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}; |
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scutimer: scutimer@f8f00600 { |
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scutimer: timer@f8f00600 { |
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interrupt-parent = <&intc>; |
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interrupts = < 1 13 0x301 >; |
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compatible = "arm,cortex-a9-twd-timer"; |
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