Reset monitor size back to 256 so environment can be written to flash on MPC85xx ADS and CDS releases. * Patch by Paolo Broggini, 02 Sep 2004: Make BSS clearing on ARM systems more robust * Patch by Yue Hu and Joe, 01 Sep 2004: - add PCI support for ixp425; - add EEPRO100 suppor tfor ixdp425 board. * Fix problem with protected sector detection in driver/cfi_flash.cmaster
wdenk
20 years ago
parent
15c7a8efd2
commit
a1191902ca
@ -0,0 +1,613 @@ |
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/*
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* IXP PCI Init |
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* (C) Copyright 2004 eslab.whut.edu.cn |
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* Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#ifdef CONFIG_PCI |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <pci.h> |
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#include <asm/arch/ixp425.h> |
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#include <asm/arch/ixp425pci.h> |
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static void non_prefetch_read (unsigned int addr, unsigned int cmd, |
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unsigned int *data); |
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static void non_prefetch_write (unsigned int addr, unsigned int cmd, |
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unsigned int data); |
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static void configure_pins (void); |
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static void sys_pci_gpio_clock_config (void); |
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static void pci_bus_scan (void); |
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static int pci_device_exists (unsigned int deviceNo); |
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static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus, |
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unsigned int dev, unsigned int func); |
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static void sys_pci_device_bars_write (void); |
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static void calc_bars (PciBar * Bars[], unsigned int nBars, |
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unsigned int startAddr); |
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#define PCI_MEMORY_BUS 0x00000000 |
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#define PCI_MEMORY_PHY 0x48000000 |
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#define PCI_MEMORY_SIZE 0x04000000 |
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#define PCI_MEM_BUS 0x40000000 |
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#define PCI_MEM_PHY 0x00000000 |
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#define PCI_MEM_SIZE 0x04000000 |
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#define PCI_IO_BUS 0x40000000 |
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#define PCI_IO_PHY 0x50000000 |
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#define PCI_IO_SIZE 0x10000000 |
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struct pci_controller hose; |
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unsigned int nDevices; |
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unsigned int nMBars; |
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unsigned int nIOBars; |
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PciBar *memBars[IXP425_PCI_MAX_BAR]; |
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PciBar *ioBars[IXP425_PCI_MAX_BAR]; |
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PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS]; |
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extern void out_8 (volatile unsigned *addr, char val) |
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{ |
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*addr = val; |
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} |
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extern void out_le16 (volatile unsigned *addr, unsigned short val) |
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{ |
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*addr = cpu_to_le16 (val); |
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} |
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extern void out_le32 (volatile unsigned *addr, unsigned int val) |
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{ |
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*addr = cpu_to_le32 (val); |
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} |
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extern unsigned char in_8 (volatile unsigned *addr) |
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{ |
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unsigned char val; |
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val = *addr; |
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return val; |
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} |
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extern unsigned short in_le16 (volatile unsigned *addr) |
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{ |
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unsigned short val; |
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val = *addr; |
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val = le16_to_cpu (val); |
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return val; |
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} |
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extern unsigned in_le32 (volatile unsigned *addr) |
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{ |
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unsigned int val; |
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val = *addr; |
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val = le32_to_cpu (val); |
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return val; |
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} |
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int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val) |
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{ |
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unsigned int retval; |
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unsigned int addr; |
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/*address bits 31:28 specify the device 10:8 specify the function */ |
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/*Set the address to be read */ |
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addr = BIT ((31 - dev)) | (where & ~3); |
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non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval); |
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*val = retval; |
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return (OK); |
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} |
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int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val) |
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{ |
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unsigned int n; |
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unsigned int retval; |
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unsigned int addr; |
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unsigned int byteEnables; |
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n = where % 4; |
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/*byte enables are 4 bits active low, the position of each
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bit maps to the byte that it enables */ |
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byteEnables = |
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(~(BIT (n) | BIT ((n + 1)))) & |
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IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; |
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byteEnables = byteEnables << PCI_NP_CBE_BESL; |
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/*address bits 31:28 specify the device 10:8 specify the function */ |
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/*Set the address to be read */ |
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addr = BIT ((31 - dev)) | (where & ~3); |
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non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); |
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/*Pick out the word we are interested in */ |
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*val = (retval >> (8 * n)); |
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return (OK); |
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} |
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int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val) |
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{ |
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unsigned int retval; |
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unsigned int n; |
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unsigned int byteEnables; |
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unsigned int addr; |
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n = where % 4; |
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/*byte enables are 4 bits, active low, the position of each
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bit maps to the byte that it enables */ |
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byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; |
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byteEnables = byteEnables << PCI_NP_CBE_BESL; |
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/*address bits 31:28 specify the device, 10:8 specify the function */ |
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/*Set the address to be read */ |
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addr = BIT ((31 - dev)) | (where & ~3); |
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non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); |
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/*Pick out the byte we are interested in */ |
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*val = (retval >> (8 * n)); |
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return (OK); |
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} |
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int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val) |
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{ |
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unsigned int addr; |
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unsigned int byteEnables; |
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unsigned int n; |
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unsigned int ldata; |
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n = where % 4; |
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/*byte enables are 4 bits active low, the position of each
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bit maps to the byte that it enables */ |
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byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; |
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byteEnables = byteEnables << PCI_NP_CBE_BESL; |
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ldata = val << (8 * n); |
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/*address bits 31:28 specify the device 10:8 specify the function */ |
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/*Set the address to be written */ |
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addr = BIT ((31 - dev)) | (where & ~3); |
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non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); |
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return (OK); |
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} |
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int pci_write_config_word (pci_dev_t dev, int where, unsigned short val) |
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{ |
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unsigned int addr; |
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unsigned int byteEnables; |
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unsigned int n; |
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unsigned int ldata; |
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n = where % 4; |
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/*byte enables are 4 bits active low, the position of each
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bit maps to the byte that it enables */ |
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byteEnables = |
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(~(BIT (n) | BIT ((n + 1)))) & |
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IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; |
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byteEnables = byteEnables << PCI_NP_CBE_BESL; |
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ldata = val << (8 * n); |
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/*address bits 31:28 specify the device 10:8 specify the function */ |
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/*Set the address to be written */ |
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addr = BIT (31 - dev) | (where & ~3); |
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non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); |
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return (OK); |
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} |
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int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val) |
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{ |
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unsigned int addr; |
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/*address bits 31:28 specify the device 10:8 specify the function */ |
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/*Set the address to be written */ |
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addr = BIT (31 - dev) | (where & ~3); |
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non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val); |
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return (OK); |
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} |
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void non_prefetch_read (unsigned int addr, |
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unsigned int cmd, unsigned int *data) |
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{ |
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REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); |
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/*set up and execute the read */ |
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REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); |
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/*The result of the read is now in np_rdata */ |
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REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data); |
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return; |
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} |
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void non_prefetch_write (unsigned int addr, |
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unsigned int cmd, unsigned int data) |
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{ |
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REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); |
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/*set up the write */ |
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REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); |
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/*Execute the write by writing to NP_WDATA */ |
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REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data); |
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return; |
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} |
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/*
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* PCI controller config registers are accessed through these functions |
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* i.e. these allow us to set up our own BARs etc. |
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*/ |
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void crp_read (unsigned int offset, unsigned int *data) |
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{ |
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REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset); |
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REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data); |
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} |
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void crp_write (unsigned int offset, unsigned int data) |
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{ |
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/*The CRP address register bit 16 indicates that we want to do a write */ |
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REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, |
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PCI_CRP_WRITE | offset); |
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REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data); |
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} |
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/*struct pci_controller *hose*/ |
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void pci_ixp_init (struct pci_controller *hose) |
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{ |
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unsigned int regval; |
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hose->first_busno = 0; |
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hose->last_busno = 0x00; |
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/* System memory space */ |
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pci_set_region (hose->regions + 0, |
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PCI_MEMORY_BUS, |
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PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY); |
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/* PCI memory space */ |
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pci_set_region (hose->regions + 1, |
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PCI_MEM_BUS, |
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PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); |
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/* PCI I/O space */ |
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pci_set_region (hose->regions + 2, |
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PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); |
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hose->region_count = 3; |
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pci_register_hose (hose); |
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/*
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========================================================== |
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Init IXP PCI |
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========================================================== |
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*/ |
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REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); |
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regval |= 1 << 2; |
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REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); |
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configure_pins (); |
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READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); |
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WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13))); |
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udelay (533); |
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sys_pci_gpio_clock_config (); |
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REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0); |
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udelay (100); |
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READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); |
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WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13)); |
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udelay (533); |
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crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT); |
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crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT); |
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crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT); |
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crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT); |
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crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT); |
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crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT); |
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/*Setup PCI-AHB and AHB-PCI address mappings */ |
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REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET, |
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IXP425_PCI_AHBMEMBASE_DEFAULT); |
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REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET, |
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IXP425_PCI_AHBIOBASE_DEFAULT); |
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REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET, |
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IXP425_PCI_PCIMEMBASE_DEFAULT); |
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crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); |
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REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); |
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regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS; |
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REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); |
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crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); |
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udelay (1000); |
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pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD); |
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REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE |
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| PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); |
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#ifdef CONFIG_PCI_SCAN_SHOW |
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printf ("Device bus dev func deviceID vendorID \n"); |
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#endif |
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pci_bus_scan (); |
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} |
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void configure_pins (void) |
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{ |
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unsigned int regval; |
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/* Disable clock on GPIO PIN 14 */ |
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READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); |
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WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8))); |
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READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); |
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READ_GPIO_REG (IXP425_GPIO_GPOER, regval); |
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WRITE_GPIO_REG (IXP425_GPIO_GPOER, |
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(((~(3 << 13)) & regval) | (0xf << 8))); |
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READ_GPIO_REG (IXP425_GPIO_GPOER, regval); |
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READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); |
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WRITE_GPIO_REG (IXP425_GPIO_GPIT2R, |
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(regval & |
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((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1))); |
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READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); |
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READ_GPIO_REG (IXP425_GPIO_GPISR, regval); |
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WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8))); |
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READ_GPIO_REG (IXP425_GPIO_GPISR, regval); |
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} |
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void sys_pci_gpio_clock_config (void) |
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{ |
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unsigned int regval; |
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READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); |
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regval |= 0x1 << 4; |
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WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); |
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READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); |
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regval |= 0x1 << 8; |
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WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); |
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} |
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void pci_bus_scan (void) |
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{ |
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unsigned int bus = 0, dev, func = 0; |
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unsigned short data16; |
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unsigned int data32; |
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unsigned char intPin; |
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/* Assign first device to ourselves */ |
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devices[0].bus = 0; |
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devices[0].device = 0; |
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devices[0].func = 0; |
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crp_read (PCI_CFG_VENDOR_ID, &data32); |
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devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK; |
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devices[0].device_id = data32 >> 16; |
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devices[0].error = FALSE; |
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devices[0].bar[NO_BAR].size = 0; /*dummy - required */ |
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nDevices = 1; |
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nMBars = 0; |
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nIOBars = 0; |
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for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) { |
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/*Check whether a device is present */ |
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if (pci_device_exists (dev) != TRUE) { |
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/*Clear error bits in ISR, write 1 to clear */ |
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REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE |
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| PCI_ISR_PFE | PCI_ISR_PPE | |
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PCI_ISR_AHBE); |
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continue; |
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} |
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/*A device is present, add an entry to the array */ |
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devices[nDevices].bus = bus; |
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devices[nDevices].device = dev; |
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devices[nDevices].func = func; |
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pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16); |
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devices[nDevices].vendor_id = data16; |
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pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16); |
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devices[nDevices].device_id = data16; |
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/*The device is functioning correctly, set error to FALSE */ |
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devices[nDevices].error = FALSE; |
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/*Figure out what BARs are on this device */ |
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sys_pci_bar_info_get (nDevices, bus, dev, func); |
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/*Figure out what INTX# line the card uses */ |
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pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin); |
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/*assign the appropriate irq line */ |
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if (intPin > PCI_IRQ_LINES) { |
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devices[nDevices].error = TRUE; |
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} else if (intPin != 0) { |
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/*This device uses an interrupt line */ |
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/*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */ |
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devices[nDevices].irq = intPin; |
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} |
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#ifdef CONFIG_PCI_SCAN_SHOW |
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printf ("%06d %03d %03d %04d %08d %08x\n", nDevices, |
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devices[nDevices].vendor_id); |
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#endif |
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nDevices++; |
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} |
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calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE); |
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sys_pci_device_bars_write (); |
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REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE |
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| PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); |
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} |
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void sys_pci_bar_info_get (unsigned int devnum, |
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unsigned int bus, |
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unsigned int dev, unsigned int func) |
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{ |
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unsigned int data32; |
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unsigned int tmp; |
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unsigned int size; |
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pci_write_config_dword (devnum, |
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PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY); |
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pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32); |
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devices[devnum].bar[0].address = (data32 & 1); |
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if (data32 & 1) { |
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/* IO space */ |
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tmp = data32 & ~0x3; |
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size = ~(tmp - 1); |
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devices[devnum].bar[0].size = size; |
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if (nIOBars < IXP425_PCI_MAX_BAR) { |
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ioBars[nIOBars++] = &devices[devnum].bar[0]; |
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} |
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} else { |
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/* Mem space */ |
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tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; |
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size = ~(tmp - 1); |
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devices[devnum].bar[0].size = size; |
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|
||||
if (nMBars < IXP425_PCI_MAX_BAR) { |
||||
memBars[nMBars++] = &devices[devnum].bar[0]; |
||||
} else { |
||||
devices[devnum].error = TRUE; |
||||
} |
||||
|
||||
} |
||||
|
||||
devices[devnum].bar[1].size = 0; |
||||
} |
||||
|
||||
void sortBars (PciBar * Bars[], unsigned int nBars) |
||||
{ |
||||
unsigned int i, j; |
||||
PciBar *tmp; |
||||
|
||||
if (nBars == 0) { |
||||
return; |
||||
} |
||||
|
||||
/* Sort biggest to smallest */ |
||||
for (i = 0; i < nBars - 1; i++) { |
||||
for (j = i + 1; j < nBars; j++) { |
||||
if (Bars[j]->size > Bars[i]->size) { |
||||
/* swap them */ |
||||
tmp = Bars[i]; |
||||
Bars[i] = Bars[j]; |
||||
Bars[j] = tmp; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr) |
||||
{ |
||||
unsigned int i; |
||||
|
||||
if (nBars == 0) { |
||||
return; |
||||
} |
||||
|
||||
for (i = 0; i < nBars; i++) { |
||||
Bars[i]->address |= startAddr; |
||||
startAddr += Bars[i]->size; |
||||
} |
||||
} |
||||
|
||||
void sys_pci_device_bars_write (void) |
||||
{ |
||||
unsigned int i; |
||||
int addr; |
||||
|
||||
for (i = 1; i < nDevices; i++) { |
||||
if (devices[i].error) { |
||||
continue; |
||||
} |
||||
|
||||
pci_write_config_dword (devices[i].device, |
||||
PCI_CFG_BASE_ADDRESS_0, |
||||
devices[i].bar[0].address); |
||||
addr = BIT (31 - |
||||
devices[i]. |
||||
device) | (0 << PCI_NP_AD_FUNCSL) | |
||||
(PCI_CFG_BASE_ADDRESS_0) & ~3; |
||||
pci_write_config_dword (devices[i].device, |
||||
PCI_CFG_DEV_INT_LINE, devices[i].irq); |
||||
|
||||
pci_write_config_word (devices[i].device, |
||||
PCI_CFG_COMMAND, INITIAL_PCI_CMD); |
||||
|
||||
} |
||||
} |
||||
|
||||
|
||||
int pci_device_exists (unsigned int deviceNo) |
||||
{ |
||||
unsigned int vendorId; |
||||
unsigned int regval; |
||||
|
||||
pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId); |
||||
|
||||
/* There are two ways to find out an empty device.
|
||||
* 1. check Master Abort bit after the access. |
||||
* 2. check whether the vendor id read back is 0x0. |
||||
*/ |
||||
REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval); |
||||
if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) { |
||||
return TRUE; |
||||
} |
||||
/*no device present, make sure that the master abort bit is reset */ |
||||
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE); |
||||
return FALSE; |
||||
} |
||||
|
||||
pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo) |
||||
{ |
||||
unsigned int i; |
||||
unsigned int devdidvid; |
||||
unsigned int didvid; |
||||
unsigned int vendorId, deviceId; |
||||
|
||||
vendorId = ids->vendor; |
||||
deviceId = ids->device; |
||||
didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) | |
||||
(vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK); |
||||
|
||||
for (i = devNo + 1; i < nDevices; i++) { |
||||
|
||||
pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID, |
||||
&devdidvid); |
||||
|
||||
if (devdidvid == didvid) { |
||||
return devices[i].device; |
||||
} |
||||
} |
||||
return -1; |
||||
} |
||||
#endif /* CONFIG_PCI */ |
||||
@ -0,0 +1,312 @@ |
||||
/*
|
||||
* IXP PCI Init |
||||
* (C) Copyright 2004 eslab.whut.edu.cn |
||||
* Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _IXP425PCI_H_ |
||||
#define _IXP425PCI_H_ |
||||
|
||||
#define TRUE 1 |
||||
#define FALSE 0 |
||||
#define OK 0 |
||||
#define ERROR -1 |
||||
#define BOOL int |
||||
|
||||
#define IXP425_PCI_MAX_BAR_PER_FUNC 6 |
||||
#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ |
||||
IXP425_PCI_MAX_FUNC_ON_BUS) |
||||
|
||||
enum PciBarId |
||||
{ |
||||
CSR_BAR=0, |
||||
IO_BAR, |
||||
SD_BAR, |
||||
NO_BAR |
||||
}; |
||||
|
||||
/*Base address register descriptor*/ |
||||
typedef struct |
||||
{ |
||||
unsigned int size; |
||||
unsigned int address; |
||||
} PciBar; |
||||
|
||||
typedef struct |
||||
{ |
||||
unsigned int bus; |
||||
unsigned int device; |
||||
unsigned int func; |
||||
unsigned int irq; |
||||
BOOL error; |
||||
unsigned short vendor_id; |
||||
unsigned short device_id; |
||||
/*We need an extra entry in this array for dummy placeholder*/ |
||||
PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1]; |
||||
} PciDevice; |
||||
|
||||
/* Mask definitions*/ |
||||
#define IXP425_PCI_TOP_WORD_OF_LONG_MASK 0xffff0000 |
||||
#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK 0xff000000 |
||||
#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK 0x0000ffff |
||||
#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff |
||||
#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f |
||||
#define IXP425_PCI_MAX_UINT32 0xffffffff |
||||
|
||||
|
||||
#define IXP425_PCI_BAR_QUERY 0xffffffff |
||||
|
||||
#define IXP425_PCI_BAR_MEM_BASE 0x100000 |
||||
#define IXP425_PCI_BAR_IO_BASE 0x000000 |
||||
|
||||
/*define the maximum number of bus segments - we support a single segment*/ |
||||
#define IXP425_PCI_MAX_BUS 1 |
||||
/*define the maximum number of cards per bus segment*/ |
||||
#define IXP425_PCI_MAX_DEV 4 |
||||
/*define the maximum number of functions per device*/ |
||||
#define IXP425_PCI_MAX_FUNC 8 |
||||
/* define the maximum number of separate functions that we can
|
||||
potentially have on the bus*/ |
||||
#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC * \ |
||||
IXP425_PCI_MAX_DEV * \
|
||||
IXP425_PCI_MAX_BUS) |
||||
/*define the maximum number of BARs per function*/ |
||||
#define IXP425_PCI_MAX_BAR_PER_FUNC 6 |
||||
#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ |
||||
IXP425_PCI_MAX_FUNC_ON_BUS) |
||||
|
||||
#define PCI_NP_CBE_BESL (4) |
||||
#define PCI_NP_AD_FUNCSL (8) |
||||
|
||||
#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v)) |
||||
#define REG_READ(b,o,v) ((v)=(*(volatile unsigned int*)((b+o)))) |
||||
|
||||
#define PCI_DELAY 500 |
||||
#define USEC_LOOP_COUNT 533 |
||||
#define PCI_SETTLE_USEC 200 |
||||
#define PCI_MIN_RESET_ASSERT_USEC 2000 |
||||
|
||||
/*Register addressing definitions for PCI controller configuration
|
||||
and status registers*/ |
||||
|
||||
#define PCI_CSR_BASE (0xC0000000) |
||||
/*
|
||||
#define PCI_NP_AD_OFFSET (0x00) |
||||
#define PCI_NP_CBE_OFFSET (0x04) |
||||
#define PCI_NP_WDATA_OFFSET (0x08) |
||||
#define PCI_NP_RDATA_OFFSET (0x0C) |
||||
#define PCI_CRP_OFFSET (0x10) |
||||
#define PCI_CRP_WDATA_OFFSET (0x14) |
||||
#define PCI_CRP_RDATA_OFFSET (0x18) |
||||
#define PCI_CSR_OFFSET (0x1C) |
||||
#define PCI_ISR_OFFSET (0x20) |
||||
#define PCI_INTEN_OFFSET (0x24) |
||||
#define PCI_DMACTRL_OFFSET (0x28) |
||||
#define PCI_AHBMEMBASE_OFFSET (0x2C) |
||||
#define PCI_AHBIOBASE_OFFSET (0x30) |
||||
#define PCI_PCIMEMBASE_OFFSET (0x34) |
||||
#define PCI_AHBDOORBELL_OFFSET (0x38) |
||||
#define PCI_PCIDOORBELL_OFFSET (0x3C) |
||||
#define PCI_ATPDMA0_AHBADDR (0x40) |
||||
#define PCI_ATPDMA0_PCIADDR (0x44) |
||||
#define PCI_ATPDMA0_LENADDR (0x48) |
||||
#define PCI_ATPDMA1_AHBADDR (0x4C) |
||||
#define PCI_ATPDMA1_PCIADDR (0x50) |
||||
#define PCI_ATPDMA1_LENADDR (0x54) |
||||
#define PCI_PTADMA0_AHBADDR (0x58) |
||||
#define PCI_PTADMA0_PCIADDR (0x5C) |
||||
#define PCI_PTADMA0_LENADDR (0x60) |
||||
#define PCI_PTADMA1_AHBADDR (0x64) |
||||
#define PCI_PTADMA1_PCIADDR (0x68) |
||||
#define PCI_PTADMA1_LENADDR (0x6C) |
||||
*/ |
||||
/*Non prefetch registers bit definitions*/ |
||||
/*
|
||||
#define NP_CMD_INTACK (0x0) |
||||
#define NP_CMD_SPECIAL (0x1) |
||||
#define NP_CMD_IOREAD (0x2) |
||||
#define NP_CMD_IOWRITE (0x3) |
||||
#define NP_CMD_MEMREAD (0x6) |
||||
#define NP_CMD_MEMWRITE (0x7) |
||||
#define NP_CMD_CONFIGREAD (0xa) |
||||
#define NP_CMD_CONFIGWRITE (0xb) |
||||
*/ |
||||
|
||||
/*define the default setting of the AHB memory base reg*/ |
||||
#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203 |
||||
#define IXP425_PCI_AHBIOBASE_DEFAULT 0x0 |
||||
#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0 |
||||
|
||||
/*define the default settings for the controller's BARs*/ |
||||
#ifdef IXP425_PCI_SIMPLE_MAPPING |
||||
#define IXP425_PCI_BAR_0_DEFAULT 0x00000000 |
||||
#define IXP425_PCI_BAR_1_DEFAULT 0x01000000 |
||||
#define IXP425_PCI_BAR_2_DEFAULT 0x02000000 |
||||
#define IXP425_PCI_BAR_3_DEFAULT 0x03000000 |
||||
#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 |
||||
#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 |
||||
#else |
||||
#define IXP425_PCI_BAR_0_DEFAULT 0x40000000 |
||||
#define IXP425_PCI_BAR_1_DEFAULT 0x41000000 |
||||
#define IXP425_PCI_BAR_2_DEFAULT 0x42000000 |
||||
#define IXP425_PCI_BAR_3_DEFAULT 0x43000000 |
||||
#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 |
||||
#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 |
||||
#endif |
||||
|
||||
/*Configuration Port register bit definitions*/ |
||||
#define PCI_CRP_WRITE BIT(16) |
||||
|
||||
/*ISR (Interrupt status) Register bit definitions*/ |
||||
#define PCI_ISR_PSE BIT(0) |
||||
#define PCI_ISR_PFE BIT(1) |
||||
#define PCI_ISR_PPE BIT(2) |
||||
#define PCI_ISR_AHBE BIT(3) |
||||
#define PCI_ISR_APDC BIT(4) |
||||
#define PCI_ISR_PADC BIT(5) |
||||
#define PCI_ISR_ADB BIT(6) |
||||
#define PCI_ISR_PDB BIT(7) |
||||
|
||||
/*INTEN (Interrupt Enable) Register bit definitions*/ |
||||
#define PCI_INTEN_PSE BIT(0) |
||||
#define PCI_INTEN_PFE BIT(1) |
||||
#define PCI_INTEN_PPE BIT(2) |
||||
#define PCI_INTEN_AHBE BIT(3) |
||||
#define PCI_INTEN_APDC BIT(4) |
||||
#define PCI_INTEN_PADC BIT(5) |
||||
#define PCI_INTEN_ADB BIT(6) |
||||
#define PCI_INTEN_PDB BIT(7) |
||||
|
||||
/*PCI configuration regs.*/ |
||||
|
||||
#define PCI_CFG_VENDOR_ID 0x00 |
||||
#define PCI_CFG_DEVICE_ID 0x02 |
||||
#define PCI_CFG_COMMAND 0x04 |
||||
#define PCI_CFG_STATUS 0x06 |
||||
#define PCI_CFG_REVISION 0x08 |
||||
#define PCI_CFG_PROGRAMMING_IF 0x09 |
||||
#define PCI_CFG_SUBCLASS 0x0a |
||||
#define PCI_CFG_CLASS 0x0b |
||||
#define PCI_CFG_CACHE_LINE_SIZE 0x0c |
||||
#define PCI_CFG_LATENCY_TIMER 0x0d |
||||
#define PCI_CFG_HEADER_TYPE 0x0e |
||||
#define PCI_CFG_BIST 0x0f |
||||
#define PCI_CFG_BASE_ADDRESS_0 0x10 |
||||
#define PCI_CFG_BASE_ADDRESS_1 0x14 |
||||
#define PCI_CFG_BASE_ADDRESS_2 0x18 |
||||
#define PCI_CFG_BASE_ADDRESS_3 0x1c |
||||
#define PCI_CFG_BASE_ADDRESS_4 0x20 |
||||
#define PCI_CFG_BASE_ADDRESS_5 0x24 |
||||
#define PCI_CFG_CIS 0x28 |
||||
#define PCI_CFG_SUB_VENDOR_ID 0x2c |
||||
#define PCI_CFG_SUB_SYSTEM_ID 0x2e |
||||
#define PCI_CFG_EXPANSION_ROM 0x30 |
||||
#define PCI_CFG_RESERVED_0 0x34 |
||||
#define PCI_CFG_RESERVED_1 0x38 |
||||
#define PCI_CFG_DEV_INT_LINE 0x3c |
||||
#define PCI_CFG_DEV_INT_PIN 0x3d |
||||
#define PCI_CFG_MIN_GRANT 0x3e |
||||
#define PCI_CFG_MAX_LATENCY 0x3f |
||||
#define PCI_CFG_SPECIAL_USE 0x41 |
||||
#define PCI_CFG_MODE 0x43 |
||||
|
||||
/*Specify the initial command we send to PCI devices*/ |
||||
#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE \ |
||||
| PCI_CMD_MEM_ENABLE \
|
||||
| PCI_CMD_MASTER_ENABLE \
|
||||
| PCI_CMD_WI_ENABLE) |
||||
|
||||
/*define the sub vendor and subsystem to be used */ |
||||
#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000 |
||||
|
||||
#define PCI_IRQ_LINES 4 |
||||
|
||||
#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ |
||||
#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ |
||||
#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ |
||||
#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */ |
||||
#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */ |
||||
#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */ |
||||
#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */ |
||||
#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */ |
||||
#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */ |
||||
#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */ |
||||
|
||||
|
||||
/*CSR Register bit definitions*/ |
||||
#define PCI_CSR_HOST BIT(0) |
||||
#define PCI_CSR_ARBEN BIT(1) |
||||
#define PCI_CSR_ADS BIT(2) |
||||
#define PCI_CSR_PDS BIT(3) |
||||
#define PCI_CSR_ABE BIT(4) |
||||
#define PCI_CSR_DBT BIT(5) |
||||
#define PCI_CSR_ASE BIT(8) |
||||
#define PCI_CSR_IC BIT(15) |
||||
|
||||
/*Configuration command bit definitions*/ |
||||
#define PCI_CFG_CMD_IOAE BIT(0) |
||||
#define PCI_CFG_CMD_MAE BIT(1) |
||||
#define PCI_CFG_CMD_BME BIT(2) |
||||
#define PCI_CFG_CMD_MWIE BIT(4) |
||||
#define PCI_CFG_CMD_SER BIT(8) |
||||
#define PCI_CFG_CMD_FBBE BIT(9) |
||||
#define PCI_CFG_CMD_MDPE BIT(24) |
||||
#define PCI_CFG_CMD_STA BIT(27) |
||||
#define PCI_CFG_CMD_RTA BIT(28) |
||||
#define PCI_CFG_CMD_RMA BIT(29) |
||||
#define PCI_CFG_CMD_SSE BIT(30) |
||||
#define PCI_CFG_CMD_DPE BIT(31) |
||||
|
||||
/*DMACTRL DMA Control and status Register*/ |
||||
#define PCI_DMACTRL_APDCEN BIT(0) |
||||
#define PCI_DMACTRL_APDC0 BIT(4) |
||||
#define PCI_DMACTRL_APDE0 BIT(5) |
||||
#define PCI_DMACTRL_APDC1 BIT(6) |
||||
#define PCI_DMACTRL_APDE1 BIT(7) |
||||
#define PCI_DMACTRL_PADCEN BIT(8) |
||||
#define PCI_DMACTRL_PADC0 BIT(12) |
||||
#define PCI_DMACTRL_PADE0 BIT(13) |
||||
#define PCI_DMACTRL_PADC1 BIT(14) |
||||
#define PCI_DMACTRL_PADE1 BIT(15) |
||||
|
||||
/* GPIO related register */ |
||||
#undef IXP425_GPIO_GPOUTR |
||||
#undef IXP425_GPIO_GPOER |
||||
#undef IXP425_GPIO_GPINR |
||||
#undef IXP425_GPIO_GPISR |
||||
#undef IXP425_GPIO_GPIT1R |
||||
#undef IXP425_GPIO_GPIT2R |
||||
#undef IXP425_GPIO_GPCLKR |
||||
|
||||
#define IXP425_GPIO_GPOUTR 0xC8004000 |
||||
#define IXP425_GPIO_GPOER 0xC8004004 |
||||
#define IXP425_GPIO_GPINR 0xC8004008 |
||||
#define IXP425_GPIO_GPISR 0xC800400C |
||||
#define IXP425_GPIO_GPIT1R 0xC8004010 |
||||
#define IXP425_GPIO_GPIT2R 0xC8004014 |
||||
#define IXP425_GPIO_GPCLKR 0xC8004018 |
||||
|
||||
#define READ_GPIO_REG(addr,val) \ |
||||
(val) = *((volatile int *)(addr)); |
||||
#define WRITE_GPIO_REG(addr,val) \ |
||||
*((volatile int *)(addr)) = (val); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue