Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --master
parent
02032e8f14
commit
a11e06965e
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#
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# (C) Copyright 2002-2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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LIB = libpostppc4xx.a
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COBJS = fpu.o spr.o uart.o watchdog.o
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include $(TOPDIR)/post/rules.mk |
@ -0,0 +1,55 @@ |
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/*
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* Copyright (C) 2007 Wolfgang Denk <wd@denx.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#ifdef CONFIG_POST |
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#if defined(CONFIG_440EP) || \ |
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defined(CONFIG_440EPX) |
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#include <ppc4xx.h> |
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#include <asm/processor.h> |
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int fpu_status(void) |
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{ |
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if (mfspr(ccr0) & CCR0_DAPUIB) |
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return 0; /* Disabled */ |
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else |
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return 1; /* Enabled */ |
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} |
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void fpu_disable(void) |
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{ |
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mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB); |
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mtmsr(mfmsr() & ~MSR_FP); |
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} |
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void fpu_enable(void) |
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{ |
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mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB); |
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mtmsr(mfmsr() | MSR_FP); |
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} |
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#endif |
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#endif |
@ -0,0 +1,176 @@ |
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/*
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* (C) Copyright 2007 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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/*
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* SPR test |
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* |
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* The test checks the contents of Special Purpose Registers (SPR) listed |
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* in the spr_test_list array below. |
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* Each SPR value is read using mfspr instruction, some bits are masked |
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* according to the table and the resulting value is compared to the |
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* corresponding table value. |
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*/ |
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#ifdef CONFIG_POST |
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#include <post.h> |
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#if CONFIG_POST & CFG_POST_SPR |
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static struct |
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{ |
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int number; |
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char * name; |
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unsigned long mask; |
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unsigned long value; |
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} spr_test_list [] = { |
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/* Standard Special-Purpose Registers */ |
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{0x001, "XER", 0x00000000, 0x00000000}, |
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{0x008, "LR", 0x00000000, 0x00000000}, |
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{0x009, "CTR", 0x00000000, 0x00000000}, |
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{0x016, "DEC", 0x00000000, 0x00000000}, |
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{0x01a, "SRR0", 0x00000000, 0x00000000}, |
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{0x01b, "SRR1", 0x00000000, 0x00000000}, |
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{0x110, "SPRG0", 0x00000000, 0x00000000}, |
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{0x111, "SPRG1", 0x00000000, 0x00000000}, |
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{0x112, "SPRG2", 0x00000000, 0x00000000}, |
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{0x113, "SPRG3", 0x00000000, 0x00000000}, |
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{0x11f, "PVR", 0x00000000, 0x00000000}, |
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/* Additional Special-Purpose Registers */ |
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{0x30, "PID", 0x00000000, 0x00000000}, |
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{0x3a, "CSRR0", 0x00000000, 0x00000000}, |
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{0x3b, "CSRR1", 0x00000000, 0x00000000}, |
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{0x3d, "DEAR", 0x00000000, 0x00000000}, |
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{0x3e, "ESR", 0x00000000, 0x00000000}, |
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{0x3f, "IVPR", 0xffff0000, 0x00000000}, |
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{0x100, "USPRG0", 0x00000000, 0x00000000}, |
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{0x104, "SPRG4", 0x00000000, 0x00000000}, |
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{0x105, "SPRG5", 0x00000000, 0x00000000}, |
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{0x106, "SPRG6", 0x00000000, 0x00000000}, |
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{0x107, "SPRG7", 0x00000000, 0x00000000}, |
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{0x10c, "TBL", 0x00000000, 0x00000000}, |
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{0x10d, "TBU", 0x00000000, 0x00000000}, |
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{0x11e, "PIR", 0x0000000f, 0x00000000}, |
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{0x130, "DBSR", 0x00000000, 0x00000000}, |
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{0x134, "DBCR0", 0x00000000, 0x00000000}, |
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{0x135, "DBCR1", 0x00000000, 0x00000000}, |
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{0x136, "DBCR2", 0x00000000, 0x00000000}, |
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{0x138, "IAC1", 0x00000000, 0x00000000}, |
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{0x139, "IAC2", 0x00000000, 0x00000000}, |
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{0x13a, "IAC3", 0x00000000, 0x00000000}, |
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{0x13b, "IAC4", 0x00000000, 0x00000000}, |
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{0x13c, "DAC1", 0x00000000, 0x00000000}, |
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{0x13d, "DAC2", 0x00000000, 0x00000000}, |
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{0x13e, "DVC1", 0x00000000, 0x00000000}, |
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{0x13f, "DVC2", 0x00000000, 0x00000000}, |
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{0x150, "TSR", 0x00000000, 0x00000000}, |
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{0x154, "TCR", 0x00000000, 0x00000000}, |
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{0x190, "IVOR0", 0x00000000, 0x00000000}, |
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{0x191, "IVOR1", 0x00000000, 0x00000000}, |
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{0x192, "IVOR2", 0x00000000, 0x00000000}, |
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{0x193, "IVOR3", 0x00000000, 0x00000000}, |
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{0x194, "IVOR4", 0x00000000, 0x00000000}, |
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{0x195, "IVOR5", 0x00000000, 0x00000000}, |
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{0x196, "IVOR6", 0x00000000, 0x00000000}, |
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{0x197, "IVOR7", 0x00000000, 0x00000000}, |
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{0x198, "IVOR8", 0x00000000, 0x00000000}, |
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{0x199, "IVOR9", 0x00000000, 0x00000000}, |
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{0x19a, "IVOR10", 0x00000000, 0x00000000}, |
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{0x19b, "IVOR11", 0x00000000, 0x00000000}, |
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{0x19c, "IVOR12", 0x00000000, 0x00000000}, |
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{0x19d, "IVOR13", 0x00000000, 0x00000000}, |
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{0x19e, "IVOR14", 0x00000000, 0x00000000}, |
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{0x19f, "IVOR15", 0x00000000, 0x00000000}, |
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{0x23a, "MCSRR0", 0x00000000, 0x00000000}, |
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{0x23b, "MCSRR1", 0x00000000, 0x00000000}, |
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{0x23c, "MCSR", 0x00000000, 0x00000000}, |
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{0x370, "INV0", 0x00000000, 0x00000000}, |
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{0x371, "INV1", 0x00000000, 0x00000000}, |
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{0x372, "INV2", 0x00000000, 0x00000000}, |
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{0x373, "INV3", 0x00000000, 0x00000000}, |
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{0x374, "ITV0", 0x00000000, 0x00000000}, |
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{0x375, "ITV1", 0x00000000, 0x00000000}, |
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{0x376, "ITV2", 0x00000000, 0x00000000}, |
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{0x377, "ITV3", 0x00000000, 0x00000000}, |
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{0x378, "CCR1", 0x00000000, 0x00000000}, |
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{0x390, "DNV0", 0x00000000, 0x00000000}, |
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{0x391, "DNV1", 0x00000000, 0x00000000}, |
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{0x392, "DNV2", 0x00000000, 0x00000000}, |
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{0x393, "DNV3", 0x00000000, 0x00000000}, |
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{0x394, "DTV0", 0x00000000, 0x00000000}, |
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{0x395, "DTV1", 0x00000000, 0x00000000}, |
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{0x396, "DTV2", 0x00000000, 0x00000000}, |
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{0x397, "DTV3", 0x00000000, 0x00000000}, |
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{0x398, "DVLIM", 0x00000000, 0x00000000}, |
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{0x399, "IVLIM", 0x00000000, 0x00000000}, |
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{0x39b, "RSTCFG", 0x00000000, 0x00000000}, |
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{0x39c, "DCDBTRL", 0x00000000, 0x00000000}, |
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{0x39d, "DCDBTRH", 0x00000000, 0x00000000}, |
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{0x39e, "ICDBTRL", 0x00000000, 0x00000000}, |
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{0x39f, "ICDBTRH", 0x00000000, 0x00000000}, |
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{0x3b2, "MMUCR", 0x00000000, 0x00000000}, |
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{0x3b3, "CCR0", 0x00000000, 0x00000000}, |
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{0x3d3, "ICDBDR", 0x00000000, 0x00000000}, |
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{0x3f3, "DBDR", 0x00000000, 0x00000000}, |
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}; |
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static int spr_test_list_size = |
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sizeof (spr_test_list) / sizeof (spr_test_list[0]); |
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int spr_post_test (int flags) |
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{ |
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int ret = 0; |
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int i; |
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unsigned long code[] = { |
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0x7c6002a6, /* mfspr r3,SPR */ |
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0x4e800020 /* blr */ |
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}; |
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unsigned long (*get_spr) (void) = (void *) code; |
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for (i = 0; i < spr_test_list_size; i++) { |
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int num = spr_test_list[i].number; |
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/* mfspr r3,num */ |
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code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6); |
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asm volatile ("isync"); |
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if ((get_spr () & spr_test_list[i].mask) != |
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(spr_test_list[i].value & spr_test_list[i].mask)) { |
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post_log ("The value of %s special register " |
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"is incorrect: 0x%08X\n", |
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spr_test_list[i].name, get_spr ()); |
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ret = -1; |
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} |
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} |
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return ret; |
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} |
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#endif /* CONFIG_POST & CFG_POST_SPR */ |
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#endif /* CONFIG_POST */ |
@ -0,0 +1,214 @@ |
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/*
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* (C) Copyright 2007 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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/*
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* UART test |
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* |
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* The controllers are configured to loopback mode and several |
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* characters are transmitted. |
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*/ |
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#ifdef CONFIG_POST |
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#include <post.h> |
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#if CONFIG_POST & CFG_POST_UART |
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#include <asm/processor.h> |
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#include <serial.h> |
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#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 |
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#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 |
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#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500 |
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#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600 |
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#define CR0_MASK 0xdfffffff |
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#define CR0_EXTCLK_ENA 0x00800000 |
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#define CR0_UDIV_POS 0 |
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#define UDIV_SUBTRACT 0 |
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#define UART0_SDR sdr_uart0 |
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#define UART1_SDR sdr_uart1 |
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#define UART2_SDR sdr_uart2 |
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#define UART3_SDR sdr_uart3 |
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#define MFREG(a, d) mfsdr(a, d) |
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#define MTREG(a, d) mtsdr(a, d) |
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#define UART_RBR 0x00 |
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#define UART_THR 0x00 |
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#define UART_IER 0x01 |
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#define UART_IIR 0x02 |
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#define UART_FCR 0x02 |
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#define UART_LCR 0x03 |
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#define UART_MCR 0x04 |
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#define UART_LSR 0x05 |
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#define UART_MSR 0x06 |
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#define UART_SCR 0x07 |
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#define UART_DLL 0x00 |
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#define UART_DLM 0x01 |
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/*
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Line Status Register. |
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*/ |
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#define asyncLSRDataReady1 0x01 |
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#define asyncLSROverrunError1 0x02 |
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#define asyncLSRParityError1 0x04 |
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#define asyncLSRFramingError1 0x08 |
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#define asyncLSRBreakInterrupt1 0x10 |
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#define asyncLSRTxHoldEmpty1 0x20 |
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#define asyncLSRTxShiftEmpty1 0x40 |
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#define asyncLSRRxFifoError1 0x80 |
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DECLARE_GLOBAL_DATA_PTR; |
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static int uart_post_init (unsigned long dev_base) |
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{ |
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unsigned long reg; |
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unsigned long udiv; |
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unsigned short bdiv; |
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volatile char val; |
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#ifdef CFG_EXT_SERIAL_CLOCK |
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unsigned long tmp; |
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#endif |
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int i; |
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for (i = 0; i < 3500; i++) { |
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if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1) |
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break; |
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udelay (100); |
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} |
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MFREG(UART0_SDR, reg); |
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reg &= ~CR0_MASK; |
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#ifdef CFG_EXT_SERIAL_CLOCK |
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reg |= CR0_EXTCLK_ENA; |
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udiv = 1; |
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tmp = gd->baudrate * 16; |
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bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; |
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#else |
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/* For 440, the cpu clock is on divider chain A, UART on divider
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* chain B ... so cpu clock is irrelevant. Get the "optimized" |
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* values that are subject to the 1/2 opb clock constraint |
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*/ |
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serial_divs (gd->baudrate, &udiv, &bdiv); |
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#endif |
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reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ |
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/*
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* Configure input clock to baudrate generator for all |
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* available serial ports here |
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*/ |
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MTREG(UART0_SDR, reg); |
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#if defined(UART1_SDR) |
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MTREG(UART1_SDR, reg); |
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#endif |
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#if defined(UART2_SDR) |
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MTREG(UART2_SDR, reg); |
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#endif |
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#if defined(UART3_SDR) |
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MTREG(UART3_SDR, reg); |
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#endif |
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out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */ |
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out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */ |
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out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ |
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out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ |
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out8(dev_base + UART_FCR, 0x00); /* disable FIFO */ |
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out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */ |
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val = in8(dev_base + UART_LSR); /* clear line status */ |
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val = in8(dev_base + UART_RBR); /* read receive buffer */ |
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out8(dev_base + UART_SCR, 0x00); /* set scratchpad */ |
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out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */ |
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return 0; |
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} |
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static void uart_post_putc (unsigned long dev_base, char c) |
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{ |
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int i; |
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out8 (dev_base + UART_THR, c); /* put character out */ |
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/* Wait for transfer completion */ |
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for (i = 0; i < 3500; i++) { |
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if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1) |
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break; |
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udelay (100); |
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} |
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} |
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static int uart_post_getc (unsigned long dev_base) |
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{ |
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int i; |
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/* Wait for character available */ |
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for (i = 0; i < 3500; i++) { |
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if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1) |
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break; |
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udelay (100); |
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} |
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return 0xff & in8 (dev_base + UART_RBR); |
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} |
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static int test_ctlr (unsigned long dev_base, int index) |
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{ |
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int res = -1; |
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char test_str[] = "*** UART Test String ***\r\n"; |
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int i; |
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uart_post_init (dev_base); |
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for (i = 0; i < sizeof (test_str) - 1; i++) { |
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uart_post_putc (dev_base, test_str[i]); |
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if (uart_post_getc (dev_base) != test_str[i]) |
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goto done; |
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} |
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res = 0; |
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done: |
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if (res) |
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post_log ("uart%d test failed\n", index); |
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return res; |
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} |
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int uart_post_test (int flags) |
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{ |
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int i, res = 0; |
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static unsigned long base[] = { |
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UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE |
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}; |
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for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) { |
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if (test_ctlr (base[i], i)) |
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res = -1; |
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} |
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serial_reinit_all (); |
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return res; |
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} |
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#endif /* CONFIG_POST & CFG_POST_UART */ |
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#endif /* CONFIG_POST */ |
@ -0,0 +1,68 @@ |
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/*
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* (C) Copyright 2007 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
/*
|
||||
* Watchdog test |
||||
* |
||||
* The test verifies the watchdog timer operation. |
||||
* On the first iteration, the test routine disables interrupts and |
||||
* makes a 10-second delay. If the system does not reboot during this delay, |
||||
* the watchdog timer is not operational and the test fails. If the system |
||||
* reboots, on the second iteration the test routine reports a success. |
||||
*/ |
||||
|
||||
#ifdef CONFIG_POST |
||||
|
||||
#include <post.h> |
||||
#include <watchdog.h> |
||||
|
||||
#if CONFIG_POST & CFG_POST_WATCHDOG |
||||
|
||||
int watchdog_post_test (int flags) |
||||
{ |
||||
if (flags & POST_REBOOT) { |
||||
/* Test passed */ |
||||
|
||||
return 0; |
||||
} else { |
||||
/* 10-second delay */ |
||||
int ints = disable_interrupts (); |
||||
ulong base = post_time_ms (0); |
||||
|
||||
while (post_time_ms (base) < 10000) |
||||
; |
||||
if (ints) |
||||
enable_interrupts (); |
||||
|
||||
/*
|
||||
* If we have reached this point, the watchdog timer |
||||
* does not work |
||||
*/ |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
#endif /* CONFIG_POST & CFG_POST_WATCHDOG */ |
||||
#endif /* CONFIG_POST */ |
Loading…
Reference in new issue