Add serial for bf60x. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>master
Sonic Zhang
13 years ago
committed by
sonic
parent
a2979dcdbe
commit
a12c51f640
@ -0,0 +1,348 @@ |
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/*
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* serial.h - common serial defines for early debug and serial driver. |
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* any functions defined here must be always_inline since |
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* initcode cannot have function calls. |
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* |
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* Copyright (c) 2004-2011 Analog Devices Inc. |
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* |
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* Licensed under the GPL-2 or later. |
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*/ |
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#ifndef __BFIN_CPU_SERIAL1_H__ |
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#define __BFIN_CPU_SERIAL1_H__ |
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#include <asm/mach-common/bits/uart.h> |
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#ifndef __ASSEMBLY__ |
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#define MMR_UART(n) _PASTE_UART(n, UART, DLL) |
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#ifdef UART_DLL |
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# define UART0_DLL UART_DLL |
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# if CONFIG_UART_CONSOLE != 0 |
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# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART |
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# endif |
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#endif |
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#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) |
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#define LOB(x) ((x) & 0xFF) |
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#define HIB(x) (((x) >> 8) & 0xFF) |
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/*
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* All Blackfin system MMRs are padded to 32bits even if the register |
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* itself is only 16bits. So use a helper macro to streamline this. |
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*/ |
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struct bfin_mmr_serial { |
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#if BFIN_UART_HW_VER == 2 |
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u16 dll; |
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u16 __pad_0; |
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u16 dlh; |
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u16 __pad_1; |
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u16 gctl; |
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u16 __pad_2; |
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u16 lcr; |
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u16 __pad_3; |
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u16 mcr; |
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u16 __pad_4; |
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u16 lsr; |
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u16 __pad_5; |
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u16 msr; |
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u16 __pad_6; |
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u16 scr; |
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u16 __pad_7; |
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u16 ier_set; |
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u16 __pad_8; |
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u16 ier_clear; |
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u16 __pad_9; |
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u16 thr; |
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u16 __pad_10; |
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u16 rbr; |
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u16 __pad_11; |
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#else |
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union { |
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u16 dll; |
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u16 thr; |
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const u16 rbr; |
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}; |
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const u16 __spad0; |
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union { |
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u16 dlh; |
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u16 ier; |
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}; |
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const u16 __spad1; |
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const u16 iir; |
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u16 __pad_0; |
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u16 lcr; |
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u16 __pad_1; |
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u16 mcr; |
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u16 __pad_2; |
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u16 lsr; |
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u16 __pad_3; |
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u16 msr; |
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u16 __pad_4; |
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u16 scr; |
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u16 __pad_5; |
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const u32 __spad2; |
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u16 gctl; |
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u16 __pad_6; |
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#endif |
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}; |
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#define uart_lsr_t uint32_t |
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#define _lsr_read(p) bfin_read(&p->lsr) |
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#define _lsr_write(p, v) bfin_write(&p->lsr, v) |
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#if BFIN_UART_HW_VER == 2 |
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# define ACCESS_LATCH() |
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# define ACCESS_PORT_IER() |
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#else |
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# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB) |
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# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB) |
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#endif |
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__attribute__((always_inline)) |
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static inline void serial_early_do_mach_portmux(char port, int mux_mask, |
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int mux_func, int port_pin) |
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{ |
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switch (port) { |
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#if defined(__ADSPBF54x__) |
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case 'B': |
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bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() & |
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~mux_mask) | mux_func); |
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bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin); |
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break; |
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case 'E': |
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bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() & |
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~mux_mask) | mux_func); |
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bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin); |
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break; |
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#endif |
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#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__) |
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case 'F': |
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bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() & |
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~mux_mask) | mux_func); |
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin); |
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break; |
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case 'G': |
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bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & |
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~mux_mask) | mux_func); |
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bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin); |
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break; |
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case 'H': |
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bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() & |
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~mux_mask) | mux_func); |
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bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin); |
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break; |
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#endif |
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default: |
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break; |
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} |
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} |
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__attribute__((always_inline)) |
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static inline void serial_early_do_portmux(void) |
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{ |
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#if defined(__ADSPBF50x__) |
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switch (CONFIG_UART_CONSOLE) { |
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case 0: |
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serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, |
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PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */ |
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serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, |
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PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */ |
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break; |
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case 1: |
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serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, |
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PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */ |
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serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, |
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PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */ |
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break; |
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} |
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#elif defined(__ADSPBF51x__) |
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switch (CONFIG_UART_CONSOLE) { |
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case 0: |
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serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, |
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PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */ |
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serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, |
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PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */ |
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break; |
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case 1: |
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serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, |
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PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */ |
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serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, |
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PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */ |
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break; |
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} |
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#elif defined(__ADSPBF52x__) |
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switch (CONFIG_UART_CONSOLE) { |
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case 0: |
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serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, |
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PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */ |
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serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, |
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PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */ |
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break; |
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case 1: |
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serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, |
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PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */ |
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serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, |
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PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */ |
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break; |
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} |
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#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) |
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const uint16_t func[] = { PFDE, PFTE, }; |
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bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]); |
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() | |
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(1 << P_IDENT(P_UART(RX))) | |
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(1 << P_IDENT(P_UART(TX)))); |
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#elif defined(__ADSPBF54x__) |
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switch (CONFIG_UART_CONSOLE) { |
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case 0: |
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serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK, |
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PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */ |
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serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK, |
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PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */ |
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break; |
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case 1: |
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serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK, |
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PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */ |
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serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK, |
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PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */ |
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break; |
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case 2: |
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serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK, |
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PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */ |
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serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK, |
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PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */ |
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break; |
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case 3: |
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serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK, |
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PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */ |
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serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK, |
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PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */ |
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break; |
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} |
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#elif defined(__ADSPBF561__) |
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/* UART pins could be GPIO, but they aren't pin muxed. */ |
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#else |
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# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) |
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# error "missing portmux logic for UART" |
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# endif |
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#endif |
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SSYNC(); |
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} |
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__attribute__((always_inline)) |
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static inline uint32_t uart_sclk(void) |
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{ |
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#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL) |
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/* We cannot use get_sclk() early on as it uses
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* caches in external memory |
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*/ |
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return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV; |
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#else |
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return get_sclk(); |
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#endif |
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} |
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__attribute__((always_inline)) |
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static inline int uart_init(uint32_t uart_base) |
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{ |
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/* always enable UART -- avoids anomalies 05000309 and 05000350 */ |
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bfin_write(&pUART->gctl, UCEN); |
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/* Set LCR to Word Lengh 8-bit word select */ |
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bfin_write(&pUART->lcr, WLS_8); |
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SSYNC(); |
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return 0; |
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} |
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__attribute__((always_inline)) |
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static inline int serial_early_init(uint32_t uart_base) |
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{ |
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/* handle portmux crap on different Blackfins */ |
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serial_do_portmux(); |
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return uart_init(uart_base); |
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} |
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__attribute__((always_inline)) |
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static inline int serial_early_uninit(uint32_t uart_base) |
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{ |
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/* disable the UART by clearing UCEN */ |
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bfin_write(&pUART->gctl, 0); |
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return 0; |
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} |
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__attribute__((always_inline)) |
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static inline int serial_early_enabled(uint32_t uart_base) |
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{ |
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return bfin_read(&pUART->gctl) & UCEN; |
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} |
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__attribute__((always_inline)) |
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static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) |
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{ |
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/* Translate from baud into divisor in terms of SCLK. The
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* weird multiplication is to make sure we over sample just |
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* a little rather than under sample the incoming signals. |
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*/ |
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uint16_t divisor = (uart_sclk() + (baud * 8)) / (baud * 16) - |
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ANOMALY_05000230; |
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/* Set DLAB in LCR to Access DLL and DLH */ |
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ACCESS_LATCH(); |
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SSYNC(); |
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/* Program the divisor to get the baud rate we want */ |
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bfin_write(&pUART->dll, LOB(divisor)); |
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bfin_write(&pUART->dlh, HIB(divisor)); |
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SSYNC(); |
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/* Clear DLAB in LCR to Access THR RBR IER */ |
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ACCESS_PORT_IER(); |
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SSYNC(); |
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} |
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__attribute__((always_inline)) |
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static inline void serial_early_put_div(uint16_t divisor) |
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{ |
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uint32_t uart_base = UART_BASE; |
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/* Set DLAB in LCR to Access DLL and DLH */ |
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ACCESS_LATCH(); |
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SSYNC(); |
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/* Program the divisor to get the baud rate we want */ |
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bfin_write(&pUART->dll, LOB(divisor)); |
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bfin_write(&pUART->dlh, HIB(divisor)); |
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SSYNC(); |
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/* Clear DLAB in LCR to Access THR RBR IER */ |
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ACCESS_PORT_IER(); |
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SSYNC(); |
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} |
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__attribute__((always_inline)) |
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static inline uint16_t serial_early_get_div(void) |
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{ |
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uint32_t uart_base = UART_BASE; |
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/* Set DLAB in LCR to Access DLL and DLH */ |
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ACCESS_LATCH(); |
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SSYNC(); |
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uint8_t dll = bfin_read(&pUART->dll); |
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uint8_t dlh = bfin_read(&pUART->dlh); |
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uint16_t divisor = (dlh << 8) | dll; |
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/* Clear DLAB in LCR to Access THR RBR IER */ |
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ACCESS_PORT_IER(); |
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SSYNC(); |
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return divisor; |
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} |
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#endif |
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#endif |
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@ -0,0 +1,161 @@ |
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/*
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* serial.h - common serial defines for early debug and serial driver. |
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* any functions defined here must be always_inline since |
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* initcode cannot have function calls. |
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* |
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* Copyright (c) 2004-2011 Analog Devices Inc. |
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* |
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* Licensed under the GPL-2 or later. |
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*/ |
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#ifndef __BFIN_CPU_SERIAL4_H__ |
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#define __BFIN_CPU_SERIAL4_H__ |
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#include <asm/mach-common/bits/uart4.h> |
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#ifndef __ASSEMBLY__ |
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#define MMR_UART(n) _PASTE_UART(n, UART, REVID) |
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#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) |
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struct bfin_mmr_serial { |
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u32 revid; |
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u32 control; |
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u32 status; |
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u32 scr; |
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u32 clock; |
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u32 emask; |
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u32 emaskst; |
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u32 emaskcl; |
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u32 rbr; |
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u32 thr; |
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u32 taip; |
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u32 tsr; |
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u32 rsr; |
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u32 txdiv_cnt; |
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u32 rxdiv_cnt; |
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}; |
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#define uart_lsr_t uint32_t |
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#define _lsr_read(p) bfin_read(&p->status) |
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#define _lsr_write(p, v) bfin_write(&p->status, v) |
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__attribute__((always_inline)) |
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static inline void serial_early_do_mach_portmux(char port, int mux_mask, |
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int mux_func, int port_pin) |
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{ |
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switch (port) { |
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case 'D': |
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bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() & |
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~mux_mask) | mux_func); |
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bfin_write_PORTD_FER_SET(port_pin); |
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break; |
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case 'G': |
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bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & |
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~mux_mask) | mux_func); |
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bfin_write_PORTG_FER_SET(port_pin); |
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break; |
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} |
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} |
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__attribute__((always_inline)) |
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static inline void serial_early_do_portmux(void) |
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{ |
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#if defined(__ADSPBF60x__) |
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switch (CONFIG_UART_CONSOLE) { |
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case 0: |
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serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK, |
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PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */ |
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serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK, |
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PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */ |
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break; |
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case 1: |
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serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK, |
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PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */ |
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serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK, |
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PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */ |
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break; |
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} |
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#else |
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# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) |
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# error "missing portmux logic for UART" |
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# endif |
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#endif |
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SSYNC(); |
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} |
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__attribute__((always_inline)) |
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static inline uint32_t uart_sclk(void) |
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{ |
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#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL) |
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/* We cannot use get_sclk() early on as it uses caches in
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* external memory |
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*/ |
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return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV / |
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CONFIG_SCLK0_DIV; |
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#else |
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return get_sclk0(); |
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#endif |
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} |
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__attribute__((always_inline)) |
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static inline int uart_init(uint32_t uart_base) |
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{ |
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/* always enable UART to 8-bit mode */ |
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bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8); |
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SSYNC(); |
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return 0; |
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} |
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__attribute__((always_inline)) |
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static inline int serial_early_init(uint32_t uart_base) |
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{ |
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/* handle portmux crap on different Blackfins */ |
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serial_do_portmux(); |
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return uart_init(uart_base); |
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} |
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__attribute__((always_inline)) |
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static inline int serial_early_uninit(uint32_t uart_base) |
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{ |
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/* disable the UART by clearing UEN */ |
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bfin_write(&pUART->control, 0); |
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return 0; |
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} |
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__attribute__((always_inline)) |
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static inline int serial_early_enabled(uint32_t uart_base) |
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{ |
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return bfin_read(&pUART->control) & UEN; |
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} |
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__attribute__((always_inline)) |
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static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) |
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{ |
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uint32_t divisor = uart_sclk() / (baud * 16); |
||||
|
||||
/* Program the divisor to get the baud rate we want */ |
||||
bfin_write(&pUART->clock, divisor); |
||||
SSYNC(); |
||||
} |
||||
|
||||
__attribute__((always_inline)) |
||||
static inline void serial_early_put_div(uint32_t divisor) |
||||
{ |
||||
uint32_t uart_base = UART_BASE; |
||||
bfin_write(&pUART->clock, divisor); |
||||
} |
||||
|
||||
__attribute__((always_inline)) |
||||
static inline uint32_t serial_early_get_div(void) |
||||
{ |
||||
uint32_t uart_base = UART_BASE; |
||||
return bfin_read(&pUART->clock); |
||||
} |
||||
|
||||
#endif |
||||
|
||||
#endif |
||||
@ -0,0 +1,66 @@ |
||||
/*
|
||||
* UART4 Masks |
||||
*/ |
||||
|
||||
#ifndef __BFIN_PERIPHERAL_UART4__ |
||||
#define __BFIN_PERIPHERAL_UART4__ |
||||
|
||||
/* UART_CONTROL */ |
||||
#define UEN (1 << 0) |
||||
#define LOOP_ENA (1 << 1) |
||||
#define UMOD (3 << 4) |
||||
#define UMOD_UART (0 << 4) |
||||
#define UMOD_MDB (1 << 4) |
||||
#define UMOD_IRDA (1 << 4) |
||||
#define WLS (3 << 8) |
||||
#define WLS_5 (0 << 8) |
||||
#define WLS_6 (1 << 8) |
||||
#define WLS_7 (2 << 8) |
||||
#define WLS_8 (3 << 8) |
||||
#define STB (1 << 12) |
||||
#define STBH (1 << 13) |
||||
#define PEN (1 << 14) |
||||
#define EPS (1 << 15) |
||||
#define STP (1 << 16) |
||||
#define FPE (1 << 17) |
||||
#define FFE (1 << 18) |
||||
#define SB (1 << 19) |
||||
#define FCPOL (1 << 22) |
||||
#define RPOLC (1 << 23) |
||||
#define TPOLC (1 << 24) |
||||
#define MRTS (1 << 25) |
||||
#define XOFF (1 << 26) |
||||
#define ARTS (1 << 27) |
||||
#define ACTS (1 << 28) |
||||
#define RFIT (1 << 29) |
||||
#define RFRT (1 << 30) |
||||
|
||||
/* UART_STATUS */ |
||||
#define DR (1 << 0) |
||||
#define OE (1 << 1) |
||||
#define PE (1 << 2) |
||||
#define FE (1 << 3) |
||||
#define BI (1 << 4) |
||||
#define THRE (1 << 5) |
||||
#define TEMT (1 << 7) |
||||
#define TFI (1 << 8) |
||||
#define ASTKY (1 << 9) |
||||
#define ADDR (1 << 10) |
||||
#define RO (1 << 11) |
||||
#define SCTS (1 << 12) |
||||
#define CTS (1 << 16) |
||||
#define RFCS (1 << 17) |
||||
|
||||
/* UART_EMASK */ |
||||
#define ERBFI (1 << 0) |
||||
#define ETBEI (1 << 1) |
||||
#define ELSI (1 << 2) |
||||
#define EDSSI (1 << 3) |
||||
#define EDTPTI (1 << 4) |
||||
#define ETFI (1 << 5) |
||||
#define ERFCI (1 << 6) |
||||
#define EAWI (1 << 7) |
||||
#define ERXS (1 << 8) |
||||
#define ETXS (1 << 9) |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue